JP3139345B2 - Manufacturing method of nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device having a layer electrode structure.

[0002]

2. Description of the Related Art EPR as a nonvolatile semiconductor memory device
The OM is formed on a semiconductor substrate including at least a source / drain region of a second conductivity type formed electrically separated from each other on a surface of a substrate on which a well region of the first conductivity type is formed, and a channel region between these regions. A floating gate made of phosphorus-doped first polysilicon formed via a first gate insulating film, and a phosphorus-doped second polysilicon formed on the floating gate via a second gate insulating film. And a control gate.

Further, the floating gate and the control gate are covered with an oxide film, and BP is
An interlayer insulating film such as an SG film is formed. In such a configuration, in order to improve the data retention performance of the floating gate, it is necessary to improve insulation on the side wall of the floating gate. In Japanese Patent Application Laid-Open No. 4-65170, an oxide film covering a floating gate and a control gate is formed by a first oxide film formed by a CVD method and a first oxide film formed thereon by a thermal oxidation method. 2 to improve the data retention characteristics of the floating gate.

[0004]

However, according to the above publication, the first oxide film is formed by the CVD method, and the oxide film formed by the CVD method is a dense film. Therefore, a second oxide film is formed on the first oxide film by a thermal oxidation method.

Therefore, two steps are required for forming an oxide film, and there is a problem that the steps are complicated. The present invention has been made in view of the above problems, and has as its object to sufficiently improve the data retention characteristics of a floating gate by using an oxide film formed by one thermal oxidation.

[0006]

Means for Solving the Problems In order to achieve the above object, the present inventors have made intensive studies on an oxide film covering a floating gate and a control gate. That is, an oxide film covering the floating gate and the control gate was formed using a thermal oxidation method, and an experiment was conducted on the relationship between the oxide film thickness on the side wall of the floating gate and data retention failure, and the results shown in FIG. 4 were obtained.

[0007] The data retention failure rate shown in FIG.
The defective rate is defined as a case where the memory unit was left at 50 ° C. for 50 hours and the maximum operating voltage of the memory unit was reduced by 0.3 V and was regarded as defective. From the results shown in FIG. 4, it can be seen that the data retention failure rate is significantly reduced when the oxide film thickness on the side wall of the floating gate is 38 nm or more.

[0008] Claim 1 made based on the above study
According to the invention described above, the first and second polycrystalline silicon substrates are provided on a semiconductor substrate (1).
Has a two-layer electrode structure with recon electrodes (4, 6)
That in the manufacturing method of the nonvolatile semiconductor memory device, the half
First polycrystal doped with impurities on a conductive substrate (1)
A silicon film (14) is formed and the first
A second impurity-doped second layer on the polycrystalline silicon film (14).
Polycrystalline silicon film (15) is formed via insulating film (5)
A step of, said first polycrystalline silicon film (14), insulation
The film (5) and the second polycrystalline silicon film (15) are patterned.
The first and second polycrystalline silicon electrodes (4,
6) and forming them by one thermal oxidation
An oxide film covering the first polycrystalline silicon film;
The edge of (14) is the second polycrystalline silicon film (15)
Forming a structure protruding from the edge of the acid.
Forming the oxide film (7) on the side wall of the first polycrystalline silicon electrode (4).
Is formed to have a film thickness of at least 38 nm.
It is a sign. In the invention described in claim 2, the first multiple
The impurity concentration of the crystalline silicon film (14)
Lower than the impurity concentration of the polycrystalline silicon film (15).
It is characterized by. According to the third aspect of the present invention,
The feature is that thermal oxidation is performed in a dry oxidation atmosphere.
You. According to the fourth aspect of the present invention, the semiconductor substrate (1)
First and second polycrystalline silicon electrodes (4, 6) are formed
Method of manufacturing nonvolatile semiconductor memory device having two-layer electrode structure
In the method , impurities are doped on the semiconductor substrate (1).
To form a first polycrystalline silicon film (14)
First, an impurity is formed on the first polycrystalline silicon film (14).
Doped second polycrystalline silicon film (15) as an insulating film
(5) a step of forming via
The impurity concentration of the first polycrystalline silicon film (14).
From the impurity concentration of the second polycrystalline silicon film (15).
Lower than the first polycrystalline silicon film (1).
4), the insulating film (5), and a second Tayui crystal silicon film (1
5) patterning the first and second polycrystalline silicon
The electrodes (4, 6) are formed and a single thermal oxidation
A step of forming a structure in which they are covered with an oxide film (7).
Then, this oxide film (7) is connected to the first polycrystalline silicon electrode.
(4) Form so that the film thickness on the side wall is 38 nm or more
It is characterized by that. According to the above feature, an oxide film covering the first polysilicon electrode and the second polysilicon electrode is formed by one thermal oxidation, and the thickness of the oxide film on the sidewall of the first polysilicon electrode is reduced. It is set to be equal to or greater than 38nm. By setting the film thickness on the side wall of the first polycrystalline silicon electrode to 38 nm or more, even when the oxide film is formed once by using the thermal oxidation method, the film is held on the first polycrystalline silicon electrode. This can significantly improve the performance of retaining the data to be stored.

According to another feature of the present invention, the impurity concentration of the first polysilicon film is lower than that of the second polysilicon film. As a result , when forming an oxide film covering the first polysilicon electrode and the second polysilicon electrode, the oxidation rate of the first polysilicon electrode is lower than that of the first polysilicon electrode. 2
It protrudes from the edge of the polysilicon electrode. as a result,
It is possible to remarkably reduce a write failure rate at which data is lost during data writing.

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of the present invention. FIG. 1 shows a cross-sectional structure of an EPROM. In FIG. 1, a P-type well region 1a is formed in a P-type silicon substrate 1, a field oxide film 2 is formed in the well region 1a by a selective oxidation method, and an element region is formed.

On the element region, a first gate oxide film 3, a floating gate 4, a second gate oxide film 5, and a control gate 6 are sequentially laminated, and these are covered with an oxide film 7, and An interlayer insulating film (BPSG)
(Film) 8 is formed. Further, an N-type source region 9 and a drain region 10 are formed in the element region, and a channel region 11 is further formed.

An Al electrode wiring 12 is formed on the source region 9 and the drain region 10 (Al electrode wiring of the control gate 6 is not shown in FIG. 1), and a protective film is formed on the entire surface of the device. (For example, a plasma nitride film) 13 is formed. The method of manufacturing the EPROM will be described with reference to the process chart shown in FIG.

First, a P-type well region 1a is formed in a P-type silicon substrate 1 and then selectively oxidized to form a field oxide film 2. Next, the first gate oxide film 3 is formed by thermal oxidation, and ion implantation is performed to form the channel region 11 . Thereafter, a first film having a thickness of about 200 nm and a crystal grain size of about 40 nm is formed at a temperature of about 620 ° C. by a reduced pressure CVD method.
A polycrystalline silicon film 14 is deposited.

Next, POCl is added at a temperature of 850 ° C. for about 26 minutes.
₃ , the phosphorus concentration in the first polycrystalline silicon film 14 is approximately 3.1 × 10 ²⁰ cm ⁻³ , and the particle size is approximately 85 n.
m. The configuration shown in FIG. 2A is obtained by the above-described steps. Next, first polycrystalline silicon film 14 is patterned (patterned in a direction not shown in FIG. 2) in order to separate a portion to be floating gate 4. After this,
Thermal oxidation is performed at 1050 ° C. for about 20 minutes to form a second gate oxide film 5 of about 26 nm (FIG. 2B).

Next, a second polycrystalline silicon film 15 having a thickness of about 370 nm is formed at a temperature of about 620 ° C. by a low pressure CVD method, and is doped with POCl ₃ at a temperature of 900 ° C. for about 26 minutes. 2 The phosphorus concentration in the polycrystalline silicon film 15 is set to about 5.5 × 10 ²⁰ cm ⁻³ (FIG. 2C). Next, patterning is performed by photolithography to form a control gate, and the second polycrystalline silicon film 15, the second gate oxide film 5,
The first polycrystalline silicon film 14 is sequentially and continuously etched (FIG. 2D). Here, a substantially vertical shape is formed by anisotropic etching using the resist 16 as shown in the figure.

Next, after the resist 16 is removed, 100
Thermal oxidation is performed for about 15 minutes in a dry oxygen atmosphere at 0 ° C. to form a structure covered with the oxide film 7, and source / drain regions 9, 10 are formed by ion implantation (FIG. 2).
(E)). In the oxidation step, as shown in FIG. 3, an oxide film 7a of about 50 nm is formed on the side wall of the floating gate 4, and an oxide film 7b of about 80 nm is formed on the side wall of the control gate 6.

Thereafter, a BPSG film 8 having a phosphorus concentration of 4.5%, a boron concentration of 3.0% and a film thickness of about 670 nm is formed.
A heat treatment is performed at 950 ° C. for about 20 minutes to planarize. Then, a contact hole is formed, an Al electrode wiring 12 is formed, and finally a protective film 13 is formed to form an EPROM shown in FIG.
Is configured. In the EPROM manufactured as described above, the charge retention characteristic is determined by the insulating property of the insulating film surrounding the floating gate 4. There are three directions of the insulating film surrounding the floating gate 4. In the present embodiment, the following countermeasures are taken. (1) Floating gate 4 and control gate 6
This improves the dielectric strength of the second gate oxide film 5 by controlling the phosphorus concentration and the grain size of the first polycrystalline silicon film 14. That is, the first polycrystalline silicon film 14
When excessive phosphorus from the substrate is locally taken into the second gate oxide film 5, the withstand voltage of the second gate oxide film decreases, but the phosphorus concentration in the first polysilicon film 14 is reduced to about 3.1.
× 10 ²⁰ cm ^-3 and a particle size of about 85 nm,
Excess phosphorus in first polycrystalline silicon film 14 is dispersed at the grain boundaries, and excessive phosphorus is prevented from being locally incorporated into second gate oxide film 5. Therefore, the withstand voltage of the second gate oxide film 5 can be improved. (2) Floating gate 4 and Si substrate (P well 1)
Insulation with a) As in the case of (1), by controlling the phosphorus concentration and the particle size of the first polycrystalline silicon film 14, it is possible to secure a good withstand voltage. (3) Insulation between Floating Gate 4 and BPSG Film 8 By setting the thickness of the oxide film 7a on the side wall of the floating gate 4 to 50 nm, good insulation can be obtained (see FIG. 4).

In this case, the oxidation conditions (eg, high-temperature oxidation of 1000 ° C. or more, a method of reducing the oxygen concentration to 10% or less to reduce the oxidation rate, etc.) are optimized, and the thickness of the oxide film 7a is reduced to about 38 nm. You may make it. Note that, in the oxidation, in the case of the steam oxidation, a projection is generated at the edge of the floating gate and the electric field is easily concentrated.

In the above-described embodiment, since the phosphorus concentration of the first polysilicon film 14 is lower than the phosphorus concentration of the second polysilicon film 15, the control gate is formed when the oxide film 7 is formed. 6, the side wall oxidation rate of the floating gate 4 is different, and the edge of the floating gate 4 protrudes from the edge of the control gate 6, as shown in FIG. This protruding distance is indicated by X in FIG.

The relative positional relationship between the edges of the floating gate 4 and the control gate 6 is related to the occurrence rate of write disturb failure (drain disturb failure) in the nonvolatile semiconductor memory device. The drain disturb failure refers to a phenomenon in which a high voltage is applied to the drain at the time of data writing, and data is lost from the written bit.

FIG. 5 shows the relationship between the distance X from which the floating gate 4 protrudes and the drain disturb failure rate. As can be seen from this figure, the floating gate 4
Is protruded from the edge of the control gate 6 (that is, the distance X is made positive), the disturb failure rate can be suppressed, and a stable yield can be obtained.

The following configuration can be applied to the above embodiment. In addition to the oxide film, the first gate insulating film 3 may be an insulating film having a stacked structure of an oxide film and a nitride film or an oxynitride-based insulating film. In addition to the oxide film, the second gate insulating film 5 may be an insulating film having a stacked structure of an oxide film and a nitride film, an insulating film having a stacked structure of an oxide film, a nitride film and an oxide film, or an oxynitride-based insulating film. It may be a film. Also, the interlayer insulating film 8
However, a PSG film other than the BPSG film may be used.

As the impurity to be doped into the floating gate 4 and the control gate 6, other impurities such as arsenic may be used in addition to phosphorus. Further, the present invention can be applied to a semiconductor device having a two-layer electrode structure, such as an EEPROM and a FLASH memory, in addition to the EPROM.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of an EPROM showing one embodiment of the present invention.

FIG. 2 is a process chart showing a manufacturing process of the EPROM shown in FIG. 1;

FIG. 3 is an enlarged view of an EPROM structure part.

FIG. 4 is a diagram showing a relationship between a data retention failure rate and an oxide film thickness on a floating gate side wall.

FIG. 5 is a diagram showing a relationship between a distance from a control gate edge to a floating gate edge and a drain disturb failure rate.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Field oxide film, 3 ... First gate oxide film, 4 ... Floating gate, 5 ... Second gate oxide film, 6 ... Control gate, 7 ... Oxide film, 8 ... B
PSG film, 9: source region, 10: drain region, 11
... channel region, 14 ... first polycrystalline silicon film, 15 ...
Second polycrystalline silicon film.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-47672 (JP, A) JP-A-63-273336 (JP, A) JP-A-8-264666 (JP, A) JP-A 7-264 249697 (JP, A) JP-A-5-175508 (JP, A) JP-A-5-102490 (JP, A) JP-A-4-87374 (JP, A) JP-A-2-110977 (JP, A) JP-A-1-283880 (JP, A) JP-A-63-244685 (JP, A) JP-A-63-211768 (JP, A) JP-A-60-245253 (JP, A) (58) (Int.Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (4)

(57) [Claims] 1. A method for manufacturing a nonvolatile semiconductor memory device having a two-layer electrode structure in which first and second polycrystalline silicon electrodes (4, 6) are formed on a semiconductor substrate (1). 1) On top of the first doped impurity
A polycrystalline silicon film (14) is formed, and a second polycrystalline silicon film (15) doped with impurities is formed on the first polycrystalline silicon film (14) via an insulating film (5). Patterning the first polycrystalline silicon film (14), the insulating film (5), and the second polycrystalline silicon film (15) to form the first and second polycrystalline silicon electrodes (4, 6). As well as forming them into oxide films by one thermal oxidation (7)
In not covered, and edge of the first polycrystalline silicon film (14)
Is projected from the edge of the second polycrystalline silicon film (15).
And forming the oxide film (7) so that the film thickness on the side wall of the first polycrystalline silicon electrode (4) is 38 nm or more. A method for manufacturing a semiconductor storage device. The impurity concentration of claim 1, wherein the first polycrystalline silicon film (14), in claim 1, characterized in that the set lower than the impurity concentration of the second polycrystalline silicon film (15) serial
Of manufacturing the above-mentioned nonvolatile semiconductor memory device. 3. The method according to claim 1, wherein the thermal oxidation is performed in a dry oxidation atmosphere.
The nonvolatile semiconductor device according to claim 1, wherein:
A method for manufacturing a storage device. 4. A first and a second polycrystal on a semiconductor substrate (1).
Has a two-layer electrode structure with silicon electrodes (4, 6)
In the method for manufacturing a nonvolatile semiconductor memory device described above, the first semiconductor substrate (1) is doped with an impurity.
A polycrystalline silicon film (14) is formed.
(1) An impurity is doped on the polycrystalline silicon film (14).
The second polycrystalline silicon film (15) via the insulating film (5).
And forming the first plurality in this step.
The impurity concentration of the crystalline silicon film (14)
Lower than the impurity concentration of the polycrystalline silicon film (15), and the first polycrystalline silicon film (14)
(5) and the second polycrystalline silicon film (15)
The first and second polycrystalline silicon electrodes (4,
6) and forming them by one thermal oxidation
A step of forming a structure covered with an oxide film (7), and forming the oxide film (7) on the first polycrystalline silicon electrode.
(4) Form so that the film thickness on the side wall is 38 nm or more
Of manufacturing a nonvolatile semiconductor memory device characterized by the following:
Law.