JP3139633B2 - Method of manufacturing MOS type semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device, and more particularly to a method of manufacturing an electrically writable and erasable read only memory device (EEPROM).

[0002]

2. Description of the Related Art One typical conventional manufacturing method of the above-mentioned EEPROM will be described with reference to the drawings. That is, FIG.
1, a gate electrode 6 is formed on a semiconductor substrate 1 by sequentially stacking a first gate insulating film 2, a floating gate electrode 3, a second gate insulating film 4, and a control gate electrode 5. Next, in FIG. 3B, phosphorus ions 9 are vertically injected into the semiconductor substrate 1 with the photoresist 7 using the pattern opened on one side of the gate electrode 6 as a mask.
An n-type diffusion layer 8 is formed. Thereafter, except for the photoresist 7, in FIG. 3C, arsenic ions 13 are implanted into the entire surface, and a heat treatment is performed to form the second n-type diffusion layer 10, which is a source region 11 and a drain region 12. An EEPROM is formed by the above method. Incidentally, the above-described erasing operation of the memory transistor is usually performed as follows. That is, the control gate electrode 5 and the semiconductor substrate 1 are set to the ground potential, the drain region 12 is set to the floating potential, and the source region 11 only induces the Fowler-Nordheim (FN) tunneling of electrons via the first gate insulating film 2. By applying a high voltage to the source region 11 to extract electrons accumulated from the floating gate electrode 3.

[0003]

SUMMARY OF THE INVENTION In the conventional manufacturing method,
By making the junction of the source region 11 gentle,
The first n-type diffusion layer 8 is formed by vertically implanting phosphorus ions 9 into the semiconductor substrate 1 in order to increase the junction withstand voltage of the first n-type diffusion layer 8. For this purpose, a heat treatment at a high temperature of, for example, 1000 ° C. was required. Therefore, there has been a serious problem in reliability, such as an increase in insulation leakage current of the first gate insulating film 2.

[0004]

According to the present invention, there is provided a method of manufacturing a MOS nonvolatile semiconductor memory device, comprising the steps of: forming a first gate insulating film, a floating gate electrode, a second gate insulating film on a P-type semiconductor substrate;
Sequentially stacking a control gate electrode, forming a gate electrode composed, 30 degrees selectively phosphorus ions only one side of the region adjacent to the gate electrode on the semiconductor substrate with respect to the normal line of the semiconductor substrate At an angle of 60 degrees from
Forming a second 1n-type diffusion layer, then, the gate
Forming a second n-type diffusion layer by implanting arsenic ions over the entire surface of both sides including the one side region adjacent to the electrode ;
And is comprised.

[0005]

Embodiments of the present invention will be described below with reference to the drawings. 1A to 1C are sectional views of a semiconductor device for explaining a first embodiment of the present invention. First, Figure 1
As shown in FIG. 1A, a gate electrode 6 formed by sequentially stacking a first gate insulating film 2, a floating gate electrode 3, a second gate insulating film 4, and a control gate electrode 5 on a semiconductor substrate 1 is formed by a known method. Form. Next, in FIG. 1B, the photoresist 7 is used to mask phosphorus ions 9 obliquely at an angle of 30 to 60 degrees with respect to the normal line of the semiconductor substrate 1 using a pattern opened on one side of the gate electrode 6 as a mask. Inject first
An n-type diffusion layer 8 is formed. 1C, the arsenic ions 13 are implanted into the entire surface except for the photoresist 7, and a heat treatment at 900 ° C. or less is performed to form the second n-type diffusion layer 10.
Are formed to form a source region 11 and a drain region 12.
FIG. 4 shows the dependency of the source breakdown voltage on the implantation angle of the phosphorus ions 9. As a result, those in which the phosphorus ions 9 are implanted at 0 degrees with respect to the normal line of the semiconductor substrate 1 have a large variation and a low withstand voltage. When the implantation angle of the phosphorus ions 9 is changed from 30 degrees to 60 degrees, a sufficient withstand voltage is obtained, and the variation is small. Therefore, the angle of oblique implantation of phosphorus ions 9 is 30
A degree of 60 degrees is appropriate. The first thus formed
In the embodiment, the first n-type diffusion layer 8 sufficiently diffuses beyond the second n-type diffusion layer 10 in the source region 11 under the gate electrode 6 even at a heat treatment of 900 ° C. or less, and the junction at the source region 11 The withstand voltage can be increased, and a sufficient margin can be provided between the voltage applied to the source region 11 during the erasing operation and the junction withstand voltage, and the occurrence of avalanche breakdown in the source region 11 during the erasing is completely suppressed. And the deterioration of the first gate insulating film 2 due to the heat treatment can be suppressed.

FIGS. 2A to 2C are cross-sectional views of a semiconductor device for explaining a second embodiment of the present invention. In the second embodiment, the gate electrode 6 shown in FIG.
Is the same as in the first embodiment up to the formation of. FIG.
As shown in FIG. 2B, the photoresist 7 is used to mask phosphorus ions 9 obliquely at an angle of 30 to 60 degrees with respect to the normal line of the semiconductor substrate 1 by using a pattern opened on one side of the gate electrode 6 as a mask. The first n-type diffusion layer 8 is formed by implanting while rotating the substrate 1. 2C, the arsenic ions 13 are implanted into the entire surface except for the photoresist 7, and a heat treatment at 900 ° C. or less is performed to form the second n-type diffusion layer 10, and the source region 11 and the drain region 12 are formed.
And In the second embodiment thus formed, since the semiconductor substrate 1 is rotated and implanted, it is not necessary to adjust the implantation direction at the time of phosphorus ion implantation, and the first n-type diffusion layer 8 is surely formed by the second n-type diffusion layer. 10, the junction breakdown voltage in the source region 11 can be increased, and a sufficient margin can be provided between the voltage applied to the source region 11 during the erase operation and the junction breakdown voltage. 11 can completely suppress avalanche breakdown from occurring, and can also suppress deterioration of the first gate insulating film 2 due to heat treatment.

[0007]

As described above, according to the present invention, 900 ° C.
Even in the following heat treatment, the source region 11 under the gate electrode 6 is formed.
Thus, the first n-type diffusion layer 8 can be formed so as to sufficiently diffuse beyond the second n-type diffusion layer 10, a sufficient junction breakdown voltage in the source region 11 is obtained, and avalanche breakdown is suppressed during the erase operation. In addition, a nonvolatile semiconductor memory device which can suppress the deterioration of the first gate insulating film due to the heat treatment can be obtained.

[Brief description of the drawings]

FIGS. 1A to 1C are cross-sectional views of a semiconductor device for explaining a first embodiment of the present invention;

FIGS. 2A to 2C are cross-sectional views of a semiconductor device for explaining a second embodiment of the present invention;

FIGS. 3A to 3C are cross-sectional views of an example of a conventional nonvolatile semiconductor memory device;

FIG. 4 shows the dependency of the source breakdown voltage on the phosphorus ion implantation angle.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 first gate insulating film 3 floating gate electrode 4 second gate insulating film 5 control gate electrode 6 gate electrode 7 photoresist 8 first n-type diffusion layer 9 phosphorus ion 10 second n-type diffusion layer 11 source region 12 drain region 13 Arsenic ion

──────────────────────────────────────────────────続 き Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8247 H01L 29/788 H01L 29/792

Claims (1)

(57) [Claims] A first gate insulating film formed on a P-type semiconductor substrate;
Forming a configured gate electrode by sequentially stacking a floating gate electrode, a second gate insulating film, and a control gate electrode; and selectively forming only a region on one side of the semiconductor substrate adjacent to the gate electrode. And implanting phosphorus ions at an angle of 30 to 60 degrees with respect to the normal line of the semiconductor substrate to form a first n-type diffusion layer.
Forming and then including the one side region adjacent to the gate electrode.
Implanting arsenic ions into free sides of areas on the entire surface, MOS, which comprises forming a first 2n-type diffusion layer, the
Of manufacturing a nonvolatile semiconductor memory device.