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JP3139835B2 - Method for manufacturing semiconductor device - Google Patents
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JP3139835B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JP3139835B2
JP3139835B2 JP04166945A JP16694592A JP3139835B2 JP 3139835 B2 JP3139835 B2 JP 3139835B2 JP 04166945 A JP04166945 A JP 04166945A JP 16694592 A JP16694592 A JP 16694592A JP 3139835 B2 JP3139835 B2 JP 3139835B2
Authority
JP
Japan
Prior art keywords
film
oxide film
cvd
polycrystalline
heat treatment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP04166945A
Other languages
Japanese (ja)
Other versions
JPH05335265A (en
Inventor
もくじ 影山
嘉明 松下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
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Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP04166945A priority Critical patent/JP3139835B2/en
Publication of JPH05335265A publication Critical patent/JPH05335265A/en
Application granted granted Critical
Publication of JP3139835B2 publication Critical patent/JP3139835B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Semiconductor Memories (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の製造方法
に関するもので、特にCVD法による成膜後の酸化膜形
成において、信頼性の高い酸化膜を得る製造方法に使用
されるものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for obtaining a highly reliable oxide film in forming an oxide film after film formation by a CVD method. .

【0002】[0002]

【従来の技術】DRAM(ダイナミックRAM)の電荷
蓄積キャパシタのキャパシタ酸化膜や、EPROM(書
き換え可能なPROM)のフローディングゲート上の酸
化膜は、CVD法により成膜された多結晶シリコン(以
下多結晶Si と略記する)などを熱酸化して形成し、そ
の後さらにCVD法により電極となる多結晶Si を成膜
している場合が多い。
2. Description of the Related Art A capacitor oxide film of a charge storage capacitor of a DRAM (dynamic RAM) and an oxide film on a loading gate of an EPROM (rewritable PROM) are formed of polycrystalline silicon (hereinafter referred to as polycrystalline silicon) formed by a CVD method. In many cases, a crystal Si is abbreviated by thermal oxidation, and then a polycrystalline Si serving as an electrode is formed by a CVD method.

【0003】上記酸化膜の信頼性は、熱酸化工程とCV
D工程との清浄度や熱処理条件に依存している。
The reliability of the above oxide film depends on the thermal oxidation process and CV
It depends on the cleanliness from the D step and the heat treatment conditions.

【0004】熱酸化工程の清浄化、その熱処理条件の最
適化は、CVD工程に比べて容易である。
[0004] Cleaning of the thermal oxidation step and optimization of the heat treatment conditions are easier than in the CVD step.

【0005】CVD工程は、反応性の高いガスを使用す
るために、配管や炉材に用いられているFe 、Ni 及び
Cu 等の金属汚染物質が、前記成膜用のガスと反応して
Siウエーハを汚染し、膜中の例えば結晶粒界に偏析す
る可能性が高い。CVD膜の成膜温度を下げることで、
金属汚染量を低下させることも可能であるが、膜質の劣
化が懸念される。
In the CVD process, since a highly reactive gas is used, metal contaminants such as Fe, Ni, and Cu used in pipes and furnace materials react with the film-forming gas to form Si. There is a high possibility that the wafer will be contaminated and segregated at, for example, crystal grain boundaries in the film. By lowering the deposition temperature of the CVD film,
Although it is possible to reduce the amount of metal contamination, there is a concern about deterioration of the film quality.

【0006】また、CVD膜中に取り込まれた金属のう
ち、特にFe は酸化膜に偏析しやすいため、前記酸化膜
が、例えばゲート酸化膜などのように、前記CVD膜に
比べて十分に薄い場合、前記CVD膜中のFe が前記酸
化膜中に濃縮される形となり、酸化膜の信頼性を著しく
低下させる。
Further, among the metals taken into the CVD film, in particular, Fe tends to segregate in the oxide film, so that the oxide film is sufficiently thinner than the CVD film, such as a gate oxide film. In this case, Fe in the CVD film is concentrated in the oxide film, and the reliability of the oxide film is significantly reduced.

【0007】[0007]

【発明が解決しようとする課題】これまで述べたよう
に、CVD法により成膜された例えば多結晶Si 膜に
は、成膜時に炉材等に用いられているFe 、Ni 、Cu
等の金属汚染物が取り込まれる。その後、このような多
結晶Si 膜上に酸化膜を形成すると、Fe などは酸化膜
に偏析しやすく、酸化膜の絶縁耐圧を劣化し、信頼性を
著しく低下させるという問題がある。
As described above, for example, the polycrystalline Si film formed by the CVD method includes Fe, Ni, Cu used for a furnace material at the time of film formation.
And other metal contaminants. Thereafter, when an oxide film is formed on such a polycrystalline Si film, there is a problem that Fe or the like is easily segregated in the oxide film, the dielectric strength of the oxide film is deteriorated, and the reliability is significantly reduced.

【0008】他方、LSI素子用基板として通常用いら
れているSi 単結晶基板には、過飽和な酸素が混入して
いる。これら酸素は、熱処理することによりBMD(酸
素析出物などの微小欠陥)を内部に発生し、そこでゲッ
タリングがおこなわれる。従ってBMDは、素子形成領
域内には存在せず、この領域外に多数分布することが望
ましい。素子製造工程中の熱処理でBMD分布や密度は
変化するが、適正なBMD分布や密度を維持することは
重要な課題である。
On the other hand, supersaturated oxygen is mixed in a Si single crystal substrate usually used as a substrate for LSI elements. These oxygens generate BMD (micro defects such as oxygen precipitates) inside by heat treatment, and gettering is performed there. Therefore, it is desirable that the BMD does not exist in the element formation region but is distributed in large numbers outside this region. Although the BMD distribution and density change due to the heat treatment during the device manufacturing process, maintaining proper BMD distribution and density is an important issue.

【0009】本発明の第1の目的は、CVD膜の成膜後
に、該膜中に取り込まれた金属不純物を除去し、より信
頼性の高い酸化膜を形成する半導体装置の製造方法を提
供することであり、本発明の他の目的は、選択的に酸化
膜が形成されている半導体基板内のBMD分布を、前記
酸化膜を損傷することなく、容易に適正な分布にするこ
とができる半導体装置の製造方法を提供することであ
る。
A first object of the present invention is to provide a method of manufacturing a semiconductor device in which after forming a CVD film, a metal impurity taken in the film is removed to form a more reliable oxide film. Another object of the present invention is to provide a semiconductor device in which a BMD distribution in a semiconductor substrate on which an oxide film is selectively formed can be easily adjusted to an appropriate distribution without damaging the oxide film. It is to provide a method of manufacturing the device.

【0010】[0010]

【課題を解決するための手段とその作用】本発明の半導
体装置の製造方法は、CVD膜を成膜した後に水素イオ
ンを前記CVD膜に注入し、次に温度 800℃以上の還元
性雰囲気中で前記CVD膜を熱処理する工程と、前記C
VD膜に又は前記CVD膜上に酸化膜を形成する工程と
を具備することを特徴とするものである。
A means for solving the action] semiconductor of the present invention
The manufacturing method of the body device is such that the hydrogen ion
Into the CVD film, and then reduce the temperature to 800 ° C or higher.
Heat-treating said CVD film in a neutral atmosphere;
Forming an oxide film on the VD film or on the CVD film;
It is characterized by having .

【0011】本発明に関連する第1および第2の参考例
の半導体装置の製造方法は、CVD膜を成膜した後に還
元性雰囲気中で前記CVD膜を熱処理する工程と、前記
CVD膜に又は前記CVD膜上に酸化膜を形成する工程
とを具備することを特徴とするものである。
First and second reference examples related to the present invention
The method of manufacturing a semiconductor device according to
Heat-treating said CVD film in an intrinsic atmosphere;
Forming an oxide film on the CVD film or on the CVD film
And characterized in that:

【0012】上記の還元性雰囲気としては、少なくとも
水素を含む還元性ガスであることが望ましい。また還元
性雰囲気中の熱処理は、本発明においては800 ℃以上で
あればよいが、参考例においては1100℃以上の温度で行
うことが特に望ましい。またCVD膜に形成される酸化
膜としては、熱酸化膜を用いることが望ましい。
The above reducing atmosphere is preferably a reducing gas containing at least hydrogen. In the present invention, the heat treatment in a reducing atmosphere is performed at 800 ° C. or more.
However, in the reference example, it is particularly desirable to carry out at a temperature of 1100 ° C. or higher. It is desirable to use a thermal oxide film as the oxide film formed on the CVD film.

【0013】例えば、CVD膜が多結晶Si の場合、C
VD膜に取り込まれたFe 等の金属不純物は、結晶粒界
に偏析しやすい。本発明のようにCVD膜を成膜した後
に水素イオンを前記CVD膜に注入しないでも、高温の
還元性雰囲気で熱処理すると、これら金属不純物は外方
拡散および結晶表面の還元反応により、CVD膜中より
外方へ引き抜かれ、高清浄のCVD膜が得られ、これに
より信頼性の高い酸化膜を形成できる。この効果は、11
00℃以上の高温度において著しく、本発明の特別の手段
を講じない場合においては、特に重要である。さらにC
VD成膜直後の多結晶Si は、粒界の影響で表面に細か
い凹凸がみられるが、1100℃以上の高温で熱処理するこ
とにより、前記凹凸が平坦化し、この多結晶Si 膜を熱
酸化して形成された酸化膜の耐圧改善の原因の 1つと思
われる。
For example, when the CVD film is polycrystalline Si, C
Metal impurities such as Fe taken into the VD film tend to segregate at crystal grain boundaries. After forming a CVD film as in the present invention
Even if hydrogen ions are not implanted into the CVD film, when heat treatment is performed in a high-temperature reducing atmosphere, these metal impurities are pulled out from the CVD film by the outward diffusion and the reduction reaction of the crystal surface, and the high-purity CVD is performed. A film is obtained, so that a highly reliable oxide film can be formed. The effect is 11
This is particularly important at high temperatures of 00 ° C. or higher, and is particularly important when the special measures of the present invention are not taken. Further C
The polycrystalline Si immediately after VD film formation has fine irregularities on the surface due to the influence of the grain boundaries. However, by performing a heat treatment at a high temperature of 1100 ° C. or more, the irregularities are flattened, and the polycrystalline Si film is thermally oxidized. This is considered to be one of the causes of the improvement of the breakdown voltage of the oxide film formed by the above.

【0014】本発明の製造方法をSi 一酸化膜−Si か
らなるキャパシタ形成に適用した結果では、あらかじめ
水素イオンを注入することにより、熱処理温度が 800℃
であっても、リーク電流の減少が見られた。これは、C
VD膜より金属不純物が抜け出てゆく前記効果のほか、
Si −酸化膜界面の不整合から生ずるダングリングボン
ドが水素原子によりターミネイトされることが原因と思
われる。
As a result of applying the manufacturing method of the present invention to the formation of a capacitor composed of a Si monoxide film-Si, the heat treatment temperature is set to 800 ° C. by implanting hydrogen ions in advance.
Even in this case, a decrease in leakage current was observed. This is C
In addition to the above effect that metal impurities escape from the VD film,
It is considered that dangling bonds resulting from the mismatch of the Si-oxide film interface are terminated by hydrogen atoms.

【0015】なお、本発明に関連する第3の参考例とし
て示す半導体装置の製造方法は、選択的に酸化膜が形成
された半導体基板上に、還元性雰囲気で反応しないCV
D膜を成膜した後、還元性雰囲気中で前記CVD膜を熱
処理する工程を含むことを特徴とするものである。
Incidentally, a third reference example related to the present invention will be described.
The method of manufacturing a semiconductor device shown in FIG.
After the D film is formed, a step of heat-treating the CVD film in a reducing atmosphere is included.

【0016】この第3の参考例の製造方法は、基板上の
酸化膜が還元されることなく、CVD膜及び基板表面層
中の酸素の高速外方拡散が行われ、CVD膜の純化およ
び基板中のBMD分布の適正化が行われる。
In the manufacturing method according to the third embodiment , oxygen is diffused at high speed in the CVD film and the substrate surface layer without reducing the oxide film on the substrate, thereby purifying the CVD film and reducing the substrate. The BMD distribution in the interior is optimized.

【0017】[0017]

【実施例】本発明のようにCVD膜を成膜した後に水素
イオンを前記CVD膜に注入しないで、高温の還元性雰
囲気で熱処理する製造方法を、スタックトキャパシタセ
ル(stacked capacitor cell)構造のDRAMのキャパ
シタ作製プロセスに適用した第1の参考例について説明
する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hydrogen after forming a CVD film as in the present invention
Without implanting ions into the CVD film, a high-temperature reducing atmosphere
A first reference example in which a manufacturing method in which heat treatment is performed in an atmosphere is applied to a capacitor manufacturing process of a DRAM having a stacked capacitor cell structure will be described.

【0018】図1は、前記DRAMの構造の要部を示す
断面図である。これは、図示していないが、素子分離さ
れたP型シリコン基板1上に、ゲート電極(ワード線)
2、ゲ−ト酸化膜3、N+ ドレイン領域4及びN+ ソー
ス領域5等から成るMOSFETを公知の方法により形
成する。次にその上を層間絶縁膜(Si O2 )6で覆
い、これにコンタクト孔を開け、CVD法により、ソー
ス領域5に接続し下層キャパシタ電極7となる多結晶S
i 膜を全面に成膜する。次に100 %H2 の雰囲気中、12
00℃,70sec の熱処理をする。次に乾燥酸素雰囲気中で
加熱し、下層キャパシタ電極7を含む多結晶Si 膜の表
面に酸化膜8を形成し、さらに多結晶Siを堆積し、バ
ターニングして図1に示すように上層キャパシタ電極
9、キャパシタ酸化膜8及び下層キャパシタ電極7から
なる蓄積キャパシタを形成する。最後に全面を酸化膜1
0で覆い、ドレイン領域4に達するコンタクト孔を開
け、Alビット線11を形成して完成する。
FIG. 1 is a sectional view showing a main part of the structure of the DRAM. Although not shown, a gate electrode (word line) is formed on the P-type silicon substrate 1 from which the element is separated.
2. A MOSFET comprising a gate oxide film 3, an N + drain region 4 and an N + source region 5 is formed by a known method. Next, the upper surface thereof is covered with an interlayer insulating film (SiO 2 ) 6, a contact hole is formed in the interlayer insulating film 6, and a polycrystalline S which is connected to the source region 5 and becomes the lower capacitor electrode 7 by the CVD method.
i Film is formed on the entire surface. Next, in an atmosphere of 100% H 2 ,
Heat treatment at 00 ° C for 70 seconds. Next, the substrate was heated in a dry oxygen atmosphere to form an oxide film 8 on the surface of the polycrystalline Si film including the lower capacitor electrode 7, and further deposited and patterned polycrystalline Si as shown in FIG. A storage capacitor including the electrode 9, the capacitor oxide film 8, and the lower capacitor electrode 7 is formed. Finally, the entire surface is an oxide film 1
0, a contact hole reaching the drain region 4 is formed, and an Al bit line 11 is formed to complete the process.

【0019】前記第1の参考例の方法を適用したDRA
Mと、従来の方法によるDRAMのポーズ時間(pause
time)特性の歩留の比較を図2(図2において第1の参
考例の方法は本発明の方法として示される)に示す。横
軸は従来法と第1の参考例の方法のロット区分を、縦軸
はそれぞれのロットのポーズ歩留を示す。同図より、
記第1の参考例の方法を適用したDRAMでは、リーク
電流などの少ない良質のキャパシタ酸化膜が得られ、蓄
積電荷保持特性の向上が見られる。
DRA to which the method of the first embodiment is applied
M and the pause time (pause) of the DRAM according to the conventional method.
Figure 2 shows a comparison of the yield of the characteristics .
Illustrative methods are shown as methods of the invention) . The horizontal axis represents the lot division of the conventional method and the method of the first reference example, and the vertical axis represents the pause yield of each lot. From the figure, before
In the DRAM to which the method of the first reference example is applied, a high-quality capacitor oxide film with little leakage current or the like is obtained, and the stored charge retention characteristics are improved.

【0020】トレンチ形容量メモリセル構造のDRAM
についても、前記第2の参考例の方法を適用することに
より同様の効果が得られた。
A DRAM having a trench-type capacitance memory cell structure
For also obtained the same effect by applying the method of the second embodiment.

【0021】次に本発明のようにCVD膜を成膜した後
に水素イオンを前記CVD膜に注入しないで、高温の還
元性雰囲気で熱処理する製造方法を、EPROMのフロ
ーティングゲートの作製に適用した場合の第2の参考例
について説明する。
Next , after a CVD film is formed as in the present invention.
Without implanting hydrogen ions into the CVD film
A description will be given of a second reference example in which a manufacturing method in which heat treatment is performed in an original atmosphere is applied to manufacture of a floating gate of an EPROM.

【0022】図3は該EPROMの構造の要部断面図、
図4はその製造工程途中の断面図である。まずP型シリ
コン基板31のフィールド酸化膜30に囲まれた島状の
素子領域表面に、薄い第1の熱酸化膜23を形成する。
次にその上にフローティングゲートとなる厚さ100 nmの
第1の多結晶Si 膜27を低圧CVD法より形成する。
次に 100%H2 雰囲気中、1200℃,90秒で熱処理を行
う。次にこの多結晶Si膜27にリンをドープした後、
熱酸化を行い厚さ50 nm の第2の熱酸化膜26を形成す
る。次に全面にコントロールゲートとなる第2の多結晶
Si 膜22を堆積する(図4参照)。
FIG. 3 is a sectional view of a main part of the structure of the EPROM.
FIG. 4 is a cross-sectional view during the manufacturing process. First, a thin first thermal oxide film 23 is formed on the surface of an island-shaped element region surrounded by a field oxide film 30 on a P-type silicon substrate 31.
Next, a first polycrystalline Si film 27 having a thickness of 100 nm serving as a floating gate is formed thereon by a low-pressure CVD method.
Next, heat treatment is performed in a 100% H 2 atmosphere at 1200 ° C. for 90 seconds. Next, after doping this polycrystalline Si film 27 with phosphorus,
Thermal oxidation is performed to form a second thermal oxide film 26 having a thickness of 50 nm. Next, a second polycrystalline Si film 22 serving as a control gate is deposited on the entire surface (see FIG. 4).

【0023】次に写真蝕刻法により、第2の多結晶Si
膜22、第2の熱酸化膜26、第1の多結晶Si 膜27
及び第1の熱酸化膜23を順次エッチングして、図3に
示すようにコントロールゲート32、第2ゲート酸化膜
36、フローティングゲート37及び第1ゲート酸化膜
33を形成する。なお第1多結晶Si 膜27を熱酸化し
た第2熱酸化膜26に代えて、第1多結晶Si 膜上に酸
化膜を堆積してもよい。次にこれら積層膜をマスクとし
てN型不純物をイオン注入し、熱処理を行ってN +ドレ
イン領域34、及びN+ ソース領域35を形成すると共
に、積層膜外面に後酸化膜38を形成する。次に全面に
パッシベーション膜(例えばPSG膜)39を堆積した
後、選択的にエッチングしてコンタクトホールを開孔
し、更に全面にAl −Si 膜を堆積した後、パターニン
グしてドレイン電極40及びソース電極41を形成し、
図3に示すEPROMが得られる。
Next, a second polycrystalline Si is formed by photolithography.
Film 22, second thermal oxide film 26, first polycrystalline Si film 27
Then, the first thermal oxide film 23 is sequentially etched to form a control gate 32, a second gate oxide film 36, a floating gate 37, and a first gate oxide film 33 as shown in FIG. Note that an oxide film may be deposited on the first polycrystalline Si film instead of the second thermal oxide film 26 obtained by thermally oxidizing the first polycrystalline Si film 27. Next, N-type impurities are ion-implanted using these laminated films as a mask, and heat treatment is performed to form N + drain regions 34 and N + source regions 35, and a post-oxide film 38 is formed on the outer surface of the laminated films. Next, a passivation film (for example, a PSG film) 39 is deposited on the entire surface, a contact hole is opened by selective etching, and an Al—Si film is further deposited on the entire surface, and then patterned to form a drain electrode 40 and a source electrode. Forming an electrode 41,
The EPROM shown in FIG. 3 is obtained.

【0024】前記EPROMは、N+ ドレイン領域34
とコントロールゲート32とに正の高電圧を加えてフロ
ーティングゲート37に電子を注入し書込みを行うデバ
イスであり、この注入電子は長期間にわたってフローテ
ィングゲート37に蓄積される必要がある。この蓄積電
荷の漏洩は多くの場合第2ゲート酸化膜36の品質によ
り決定される。
The EPROM has an N + drain region 34.
This is a device in which a positive high voltage is applied to the floating gate 37 and the control gate 32 to inject electrons into the floating gate 37 for writing. The injected electrons need to be accumulated in the floating gate 37 for a long period of time. The leakage of the stored charges is often determined by the quality of the second gate oxide film 36.

【0025】図5は、前記第2の参考例の方法を適用し
たEPROMと、従来方法によるEPROMとの製品歩
留を比較したものである(図5において第2の参考例の
方法は本発明の方法として示される)。両方法の歩留の
差は、主として第2ゲート酸化膜36の品質の差による
ものと考えられる。
FIG. 5 shows a comparison of the product yield between an EPROM to which the method of the second embodiment is applied and an EPROM according to the conventional method .
The method is shown as the method of the present invention ). It is considered that the difference in yield between the two methods is mainly due to the difference in quality of the second gate oxide film 36.

【0026】前述のように、多結晶Si 中の金属不純物
は、特に過剰な分は結晶粒界に析出しやすく、このよう
な金属原子は粒界拡散による外方拡散が生ずるため、短
時間の熱処理で効果がある。このような場合、熱処理と
して1100℃以上, 3分以下とすることが望ましい。
As described above, the metal impurities in the polycrystalline Si, particularly in an excessive amount, tend to precipitate at the crystal grain boundaries, and such metal atoms cause outward diffusion due to the grain boundary diffusion. Heat treatment is effective. In such a case, it is desirable that the heat treatment be performed at a temperature of 1100 ° C. or more and 3 minutes or less.

【0027】また、例えば低温で成膜した多結晶Si の
CVD膜に対しても、高温、短時間の本熱処理による
「焼しめ」による電気特性の改善が得られることは言う
までもない。
It is needless to say that, for example, even for a polycrystalline Si CVD film formed at a low temperature, the electrical characteristics can be improved by "baking" by the high-temperature, short-time main heat treatment.

【0028】次に多結晶Si 膜を熱酸化して形成した酸
化膜の耐圧は、前記参考例の方法を適用することによ
り、図6に示すように改善された(図6において参考例
の方法は本発明の方法として示される)。同図(a )は
参考例の方法によるもの、同図(b )は従来の方法によ
るもので、横軸は耐圧限界における電解強度(MV/c
m)を示し、縦軸は該耐圧限界を示す試料頻度を示す。
同図により、参考例の方法を適用すれば、耐圧が大幅に
改善されることがわかる。これはCVD法により成膜さ
れた直後の多結晶Si は、粒界の影響で表面に細かい凹
凸が見られるが、1100℃以上の高温雰囲気中で熱処理す
ることにより、上記凹凸が平坦化したことが寄与してい
る。
[0028] Next withstand voltage of the oxide film polycrystalline Si film was formed by thermal oxidation, by applying the method of Reference Example, Reference Example (FIG. 6 which is improved as shown in FIG. 6
Is shown as the method of the present invention ). Figure (a)
In the method of the reference example , the same figure (b) is based on the conventional method, and the horizontal axis is the electrolytic strength (MV / c
m), and the vertical axis indicates the sample frequency indicating the withstand voltage limit.
It can be seen from the figure that the application of the method of the reference example significantly improves the breakdown voltage. This is because although polycrystalline Si immediately after being formed by the CVD method has fine irregularities on the surface due to the influence of grain boundaries, the above irregularities are flattened by heat treatment in a high temperature atmosphere of 1100 ° C. or more. Has contributed.

【0029】次に前記した第3の参考例について説明す
る。図7に示すように、シリコン基板71に、LOCO
S法により、素子分離のための島状酸化膜72を形成す
る。その後、CVD法により多結晶Si 膜73を全面に
成膜し、次に 100%H2 雰囲気にて、1200℃,10時間の
熱処理を施した。図7は、この熱処理後の基板内部のB
MD(酸素析出物などの微小欠陥)74の分布の概念を
示す断面図である。素子分離された部分は、島状酸化膜
72の近傍までBMDが発生しており、金属不純物のゲ
ッタリング効果があるが、素子活性領域75では、H2
雰囲気中の熱処理により、酸素濃度の低下が著しく、B
MDは発生しておらず、デバイスの動作に影響を与えな
い。即ち、請求項3に係る本発明の方法によれば、容易
にこのような望ましいBMDの分布を得ることができ
る。この場合、この処理は拡散層深さに影響を与えるた
め、本熱処理前のドライブイン熱処理の時間を抑えてお
く必要があった。
Next , the third embodiment will be described. As shown in FIG. 7, a LOCO is
An island-shaped oxide film 72 for element isolation is formed by the S method. Thereafter, a polycrystalline Si film 73 was formed on the entire surface by the CVD method, and then a heat treatment was performed at 1200 ° C. for 10 hours in a 100% H 2 atmosphere. FIG. 7 shows B inside the substrate after this heat treatment.
FIG. 3 is a cross-sectional view showing the concept of the distribution of MD (micro defects such as oxygen precipitates) 74. Isolation portion is BMD is generated to the vicinity of the island-shaped oxide film 72, there is a gettering effect of metal impurities, in the element active region 75, H 2
Due to the heat treatment in the atmosphere, the oxygen concentration was significantly reduced.
MD does not occur and does not affect the operation of the device. That is, according to the method of the present invention according to claim 3, such a desirable distribution of BMD can be easily obtained. In this case, since this treatment affects the depth of the diffusion layer, it is necessary to suppress the drive-in heat treatment time before the main heat treatment.

【0030】またこの方法は、選択的に酸化膜が形成さ
れている基板中の金属不純物の引き抜き及び基板中の酸
素の高速外方拡散を得る場合、上記基板に還元性雰囲気
で反応しない、例えば多結晶Si 膜等を形成すること
で、前記基板上の酸化膜が還元されることはなく、酸素
の高速外方拡散が可能となる方法である。
Further, this method does not react with the substrate in a reducing atmosphere when selectively extracting metal impurities in a substrate on which an oxide film is formed and obtaining high-speed outward diffusion of oxygen in the substrate. By forming a polycrystalline Si film or the like, the oxide film on the substrate is not reduced, and high-speed outward diffusion of oxygen becomes possible.

【0031】前記第1参考例のDRAMのキャパシタを
作製する工程において、下層キャパシタ電極用の多結晶
Si 成膜後、本発明のように該Si 膜に水素イオン注入
を行い、その後 850℃の還元性雰囲気にて熱処理したキ
ャパシタで漏洩電流の減少がみられたが、これはSi −
酸化膜界面の不整合から生ずるSi のダングリングボン
ド(不対結合手)が、水素原子により満されることが原
因とみられる。
In the step of fabricating the DRAM capacitor of the first reference example, after forming a polycrystalline Si film for the lower layer capacitor electrode, hydrogen ions are implanted into the Si film as in the present invention , and then a reduction at 850 ° C. A decrease in leakage current was observed for capacitors heat-treated in a neutral atmosphere.
It is considered that the dangling bond of Si resulting from the mismatch at the oxide film interface is filled with hydrogen atoms.

【0032】[0032]

【発明の効果】これまで詳述したように、本発明によれ
ば、CVD膜を成膜し、水素イオン注入後 800℃以上の
温度の還元性雰囲気中で熱処理することにより、CVD
膜中に取り込まれた金属不純物を除去し、その後の酸化
膜形成工程でより信頼性の高い酸化膜が得られた。
As described so far, according to the present invention, according to the present invention, by the CVD film is formed, a heat treatment in a reducing atmosphere at 800 ° C. or higher temperature after the hydrogen ion implantation, CVD
The metal impurities taken into the film were removed, and a more reliable oxide film was obtained in the subsequent oxide film forming step.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に関連する第1の参考例を説明するため
のDRAMの構造の要部断面図である。
FIG. 1 is a sectional view of a principal part of a DRAM structure for explaining a first reference example related to the present invention ;

【図2】第1の参考例の方法及び従来の方法で、それぞ
れ作製したDRAMのポーズタイム(pause time)の歩
留比較図である。
FIG. 2 is a yield comparison diagram of pause times of DRAMs manufactured by the method of the first reference example and the conventional method, respectively.

【図3】本発明に関連する第2の参考例を説明するため
のEPROMの構造の要部断面図である。
FIG. 3 is a sectional view of a main part of the structure of an EPROM for explaining a second reference example related to the present invention ;

【図4】図3に示すEPROMの製造工程を示す断面図
である。
FIG. 4 is a sectional view showing a manufacturing process of the EPROM shown in FIG. 3;

【図5】第2の参考例の方法及び従来の方法でそれぞれ
作製したEPROMの製品歩留比較図である。
FIG. 5 is a product yield comparison diagram of EPROMs respectively manufactured by the method of the second reference example and a conventional method.

【図6】参考例の方法及び従来法のそれぞれにより作製
した酸化膜の耐圧の比較図である。
FIG. 6 is a comparison diagram of the breakdown voltage of an oxide film formed by each of the method of the reference example and the conventional method.

【図7】本発明に関連する第3の参考例を説明するため
の図で、LOCOS法により素子分離酸化膜を形成した
基板に、第3の参考例を適用した場合のBMDの分布を
示す基板断面図である。
FIG. 7 is a diagram for explaining a third reference example related to the present invention, and shows a distribution of BMD when the third reference example is applied to a substrate on which an element isolation oxide film is formed by a LOCOS method; It is a board | substrate sectional drawing.

【符号の説明】[Explanation of symbols]

1,31 P型シリコン基板 2 ゲート電極 3 ゲート酸化膜 4,34 N+ ドレイン領域 5,35 N+ ソース領域 7 下層キャパシタ電極 8 キャパシタ酸化膜 9 上層キャパシタ電極 32(22) コントロールゲート(第2多結晶Si
膜) 33(23) 第1ゲート酸化膜(第1熱酸化膜) 36(26) 第2ゲート酸化膜(第2熱酸化膜) 37(27) フローティングゲート(第1多結晶Si
膜) 40 ドレイン電極 41 ソース電極 72 素子分離用島状酸化膜 73 多結晶Si 膜 74 BMD 75 素子活性領域
1, 31 P-type silicon substrate 2 Gate electrode 3 Gate oxide film 4, 34 N + Drain region 5, 35 N + Source region 7 Lower capacitor electrode 8 Capacitor oxide film 9 Upper capacitor electrode 32 (22) Control gate (second gate) Crystal Si
33 (23) First gate oxide film (first thermal oxide film) 36 (26) Second gate oxide film (second thermal oxide film) 37 (27) Floating gate (first polycrystalline Si)
Film) 40 drain electrode 41 source electrode 72 island oxide film for element isolation 73 polycrystalline Si film 74 BMD 75 element active region

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 CVD膜を成膜した後に水素イオンを前
記CVD膜に注入し、次に温度 800℃以上の還元性雰囲
気中で前記CVD膜を熱処理する工程と、前記CVD膜
に又は前記CVD膜上に酸化膜を形成する工程とを具備
することを特徴とする半導体装置の製造方法。
1. A method according to claim 1 , wherein hydrogen ions are formed after the CVD film is formed.
Implanting into the CVD film, and then heat-treating the CVD film in a reducing atmosphere at a temperature of 800 ° C. or higher; and forming an oxide film on or on the CVD film. A method for manufacturing a semiconductor device.
JP04166945A 1992-06-02 1992-06-02 Method for manufacturing semiconductor device Expired - Fee Related JP3139835B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP04166945A JP3139835B2 (en) 1992-06-02 1992-06-02 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP04166945A JP3139835B2 (en) 1992-06-02 1992-06-02 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH05335265A JPH05335265A (en) 1993-12-17
JP3139835B2 true JP3139835B2 (en) 2001-03-05

Family

ID=15840549

Family Applications (1)

Application Number Title Priority Date Filing Date
JP04166945A Expired - Fee Related JP3139835B2 (en) 1992-06-02 1992-06-02 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP3139835B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6131701B2 (en) * 2013-05-08 2017-05-24 株式会社豊田自動織機 Manufacturing method of semiconductor substrate

Also Published As

Publication number Publication date
JPH05335265A (en) 1993-12-17

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