JP3142033B2 - D / A conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process apparatus including a transmitter provided with a digital processing device, for example, which converts digital data obtained by digitally processing measured values into 4 to 2 digital data.
It is suitable for use in a measurement system or the like which converts an analog current value of 0 mA into an analog current value and transmits it to a host controller or the like.
/ A (digital / analog) conversion circuit.

[0002]

2. Description of the Related Art Hitherto, as this type of D / A conversion circuit, those called a ladder type, a weight type and the like are generally well known. However, in the above-described process equipment, it is required that the power consumption (current) is extremely small. From such a viewpoint, pulse width modulation (also referred to as PWM) is required.
Is used.

A conventional D / A based on the principle shown in FIG.
2 shows an example of a conversion circuit. In the figure, 1 is a processing device such as a microcomputer, 2 is a counter, 3 is a latch circuit, 4 is a comparator, and 5 is a low-pass filter (LPF).

In such a configuration, the digital amount (set value) from the microcomputer 1 is latched by the latch circuit 3, while the counter 2 sequentially counts the clock signal. The two values are compared by the comparator 4, and a high-level (H) signal is output when the output of the counter 2 is larger than the output of the latch circuit 3, and a low-level (L) signal is output when the output is smaller. This output is L
It is smoothed in PF5 and output as an analog quantity.

Now, for example, the clock frequency is set to 3.
Assuming 6864 MHz, the period of the PWM waveform is as shown in FIG.
As shown in (a), it is about 17.8 mS. On the other hand, if the digital set value from the microcomputer 1 is 43691, the output of the comparator 4 in this case is as shown in FIG.
The waveform is as follows. FIG. 9 shows this for a plurality of cycles.
(B), and (c) shows a waveform obtained by smoothing the waveform with the LPF 5. Here, in the waveform of FIG. 9A, the relationship between the high level and the low level of the signal is opposite to that of the operation in FIG. 8, because the inverted LPF is used.

[0006]

However, the conventional circuit has a problem that the ripple of the output waveform is large as shown in the analog output waveform of FIG. To this end, for the LPF, there are conceivable methods of (1) lowering its cutoff frequency, (2) increasing its order, etc., but (1) causes a response delay, and (2) requires a complicated circuit. In addition to this, there is a problem that current consumption increases and further a phase delay occurs.

On the other hand, in order to shorten the PWM cycle, there are conceivable methods of (3) speeding up the clock, (4) reducing the number of bits of the counter and the latch circuit, and (3).
In this case, current consumption increases, and in (4), a problem such as a decrease in resolution occurs. Therefore, an object of the present invention is to reduce ripple without increasing current consumption and without lowering resolution.

[0008]

In order to solve such a problem, according to the present invention, a digital input set value of (m + n) bits and a clock signal are counted (n +
a D / A conversion circuit which obtains a pulse width modulation (PWM) signal by comparing it with an output of a m) bit counter and smoothes the signal to obtain an analog signal; Bit, output of the counter is upper n bits, lower m bits
And the lower n bits of the input set value and the counter
Input the upper n bits of the
The remainder value when dividing by the resolution is the upper m of the input set value.
A logic circuit that generates a signal that is periodically reflected on bits
And the input set value based on the signal from this logic circuit.
Position periodically provided a correction to a correction circuit in accordance with m bits to the remainder value, it is characterized by obtaining a PWM signal by comparing the lower m bits from the this correction circuit output counter.

[0009]

The digital input set value is set to the upper m bits and lower n bits.
By dividing the PWM signal into bits and periodically correcting the pulse width of the PWM signal determined by the upper m bits according to the lower n bits, the frequency of the PWM signal is increased without lowering the resolution, and as a result, the ripple is reduced.

[0010]

1 is a block diagram showing an embodiment of the present invention. In FIG. 8, a + n selection logic circuit (also simply referred to as a logic circuit) 6A, a +1 adder 7A, a +2 adder 7B, and a +3 adder are shown. 7C and 4 inputs and 1 output (4 →
It is configured by adding the selector 8A of 1) and the like. Also,
Here, the upper 2 bits (C1
5, C14) to the logic circuit 6A and the lower 14 (C13)
To C0) bits to the comparator 4, respectively, and the upper 14 bits (L15 to L2) of the 16-bit latch circuit 3 are directly supplied or the +1 adders 7A, +
Selector 8A via 2 adder 7B and +3 adder 7C
And the lower two bits (L1, L0) to the logic circuit 6A.

The logic circuit 6A outputs "00", "01", "10" as shown in FIG. 2 according to the values of the bits C15 and C14 and L1 and L0 of the counter 2 and the latch circuit 3.
And the signal of "11" is output and given to the selector 8A. The selector 8A outputs “0” from the logic circuit 6A.
When it is "0", the input "A", that is, the upper 14 bits (L15 to L2) from the latch circuit 3 are selected, and when it is "01", the input "B", that is, the output from the +1 adder 7A,
When "10", the input "C", that is, the output from the +2 adder 7B is selected, and when "11", the input "D", that is, the output from the +3 adder 7C is selected.

Therefore, the upper 14 bits (L15 to L2) from the latch circuit 3 are supplied as they are from the selector 8A, or this value is added to this value by the adders 7A, 7B and 7C.
The value of 1, +2 or +3 is output, and this is compared with the lower 14 bits from the counter 2. It should be noted that which of the adders 7A, 7B and 7C is used
It is determined by the digital input value set in the latch circuit 3. For example, whether the remainder when the input value is divided by 4 is 1 or not,
Either of the adders 7A, 7B, 7C is used depending on whether it is 2 or 3. Further, although 16 bits are divided into 14 bits and 2 bits, it is needless to say that division may be performed by other numbers.

FIG. 3 shows the above operation. FIG. 3A shows the PWM output waveform, and FIGS. 3B and 3C show the upper two bits of the counter. As is clear from comparison with FIG.
The PWM cycle is 1/4 (65536/4 = 1) in the case of FIG.
6384). The input set value is 43691 as in the case of FIG. 9, which is not divisible by 4 and the fraction is 3, so the +3 adder 7C in FIG.
"3" is corrected periodically. For example, in this case, by adding "3" for each fourth cycle in units of four cycles, the fraction "3" is periodically corrected so as not to lower the resolution.

FIG. 4 is a graph for explaining an example of characteristics of the low-pass filter shown in FIG. 1, in which the order is "3". That is, the frequency of the clock signal is 3.6864 MHz as in the case of FIG.
6864 MHz / 2 ¹⁶ ≒ 56.25 Hz. On the other hand, the PWM frequency in the case as shown in FIG.
4, the gain of the low-pass filter is reduced by about 36 dB, as is almost clear from FIG. 4, whereby the ripple is reduced to approximately 1/64, and it can be seen that the ripple can be greatly reduced.

FIG. 5 is a block diagram showing a modification of FIG. This is +1 instead of + n selection logic 6A in FIG.
A selection logic 6 is provided, and a +1 adder 7 shown in FIG.
A, +1 instead of +2 adder 7B and +3 adder 7C
The feature is that only one adder 7 is provided, and the other points are the same as those in FIG. The selector also has 4 inputs and 1
Because the output has two inputs and one output, FIG.
The reference numeral 8 is given as a little different from the one shown in FIG.

FIG. 6 shows the input / output relationship of the +1 selection logic 6 in this case. That is, if the input set value is 43691 as in the case of FIG. 1, a fraction obtained by dividing the input set value by 4 is “3”. By adding "1" in each of the second period, the third period, and the fourth period, the fraction "3" is periodically corrected so as not to lower the resolution.

FIG. 7 shows the above operation, and the frequency of the clock signal, the PWM cycle, and the input set value are the same as those in FIG. The difference is that in FIG. 3, +3 is added for every fourth cycle in which four cycles are defined as one unit.
1 ", so that the
In this case, the correction is simpler than that shown in FIG.

[0018]

According to the present invention, the input data is divided into upper several bits and lower several bits, and the PWM pulse width determined by the upper several bits is periodically corrected in accordance with the lower bits, whereby (the upper several bits) Since (+ lower few bits) resolution is ensured, there is an advantage that the ripple can be reduced without increasing the operating clock frequency or modifying the LPF.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram for explaining an input / output relationship of the + n selection logic circuit shown in FIG. 1;

FIG. 3 is a waveform chart for explaining the operation of FIG. 1;

FIG. 4 is a graph showing a characteristic example of a low-pass filter.

FIG. 5 is a block diagram showing a modification of FIG. 1;

6 is an explanatory diagram for explaining an input / output relationship of the +1 selection logic circuit shown in FIG. 5;

FIG. 7 is a waveform chart for explaining the operation of FIG. 5;

FIG. 8 is a block diagram showing a conventional example.

FIG. 9 is a waveform chart showing an output waveform of FIG. 8;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... microcomputer (microcomputer), 2 ... counter, 3 ... latch circuit, 4 ... comparator, 5 ... low-pass filter (LPF), 6, 6A ... selection logic circuit,
7, 7A, 7B, 7C ... adder, 8, 8A ... selector.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 1/00-1/88

Claims (1)

(57) [Claims] 1. A pulse width modulation (PWM) signal is obtained by comparing a digital input set value of (m + n) bits with an output of a (n + m) bit counter for counting clock signals, and smoothing the obtained signal. A D / A conversion circuit for obtaining a signal, wherein the digital input set value is upper m bits and lower n bits, and the output of the counter is upper n bits and lower m bits.
And the lower n bits of the input set value and the counter
Input the upper n bits of the
The remainder value when dividing by the resolution is the upper m of the input set value.
A logic circuit that generates a signal that is periodically reflected on bits
And the input set value based on the signal from this logic circuit.
Position m bits periodically provided and a correction to the correction circuit in response to the remainder value, D / A, characterized in that to obtain a PWM signal by comparing the lower m bits from the this correction circuit output counter Conversion circuit.