JP3143957B2 - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JP3143957B2 JP3143957B2 JP03166398A JP16639891A JP3143957B2 JP 3143957 B2 JP3143957 B2 JP 3143957B2 JP 03166398 A JP03166398 A JP 03166398A JP 16639891 A JP16639891 A JP 16639891A JP 3143957 B2 JP3143957 B2 JP 3143957B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- integrated circuit
- semiconductor integrated
- circuit device
- dummy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 6
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- 238000000034 method Methods 0.000 claims description 2
- 239000003870 refractory metal Substances 0.000 claims description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 6
- 229910021342 tungsten silicide Inorganic materials 0.000 description 6
- 238000013508 migration Methods 0.000 description 5
- 230000005012 migration Effects 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【産業上の利用分野】本発明は半導体集積回路装置に関
し、特に金属配線構造に関する。The present invention relates to a semiconductor integrated circuit device, and more particularly to a metal wiring structure.
【０００２】[0002]
【従来の技術】半導体集積回路装置の高集積化，多機能
化に伴い、微細化が増々進んでいる。特に、半導体基板
上の各トランジスタを結線する金属配線は、半導体集積
回路装置内の約半分の領域を占めるため、配線幅及び配
線間隔の微細化、さらに多層配線化が進んでいる。2. Description of the Related Art As semiconductor integrated circuit devices have become more highly integrated and multifunctional, miniaturization is increasing. In particular, the metal wiring connecting each transistor on the semiconductor substrate occupies about half the area in the semiconductor integrated circuit device, so that the wiring width and the wiring interval have been reduced, and the multilayer wiring has been developed.
【０００３】従来、金属配線は、アルミを主成分とする
金属層を用いてきたが、最近では微細化に伴うエレクト
ロマイグレーション，ストレスマイグレーション等の耐
マイグレーション対策のため、アルミに銅を添加した
り、アルミ層の上にタングステンシリサイド等のシリサ
イド層を重ねた積層構造を持つ配線が使用されている。Conventionally, metal layers have been made of a metal layer containing aluminum as a main component. Recently, however, copper has been added to aluminum in order to prevent migration such as electromigration and stress migration due to miniaturization. A wiring having a laminated structure in which a silicide layer such as tungsten silicide is stacked on an aluminum layer is used.
【０００４】[0004]
【発明が解決しようとする課題】図２（ａ）は微細化及
び耐マイグレーション対策を施した従来の配線の平面
図、（ｂ）は、図２（ａ）のＡ−Ａ′線断面図である。
図２（ａ），（ｂ）に示すように半導体基板１上に厚い
絶縁膜２が形成され、その上にアルミを主成分とする金
属層３とタングステンシリサイド層４との積層構造配線
が形成されている。FIG. 2 (a) is a plan view of a conventional wiring which has been subjected to miniaturization and anti-migration measures, and FIG. 2 (b) is a sectional view taken along line AA 'of FIG. 2 (a). is there.
As shown in FIGS. 2 (a) and 2 (b), a thick insulating film 2 is formed on a semiconductor substrate 1, and a laminated wiring of a metal layer 3 mainly composed of aluminum and a tungsten silicide layer 4 is formed thereon. Have been.
【０００５】上記積層構造配線は、最小配線幅１．５μ
ｍ程度の微細化が可能であり、かつ耐マイグレーション
に強い構造であるが、アロイ工程，パシベーション膜の
形成による３００℃から４５０℃の温度の影響でアルミ
層３から横方向へのヒロック、いわゆるラテラルヒロッ
ク５が発生し、配線間が短絡してしまうという問題があ
る。The above-mentioned laminated wiring has a minimum wiring width of 1.5 μm.
m, and has a structure that is resistant to migration. Hillocks 5 are generated, and there is a problem that wirings are short-circuited.
【０００６】この現象は、通常アルミ層３がタングステ
ンシリサイド層４に抑えられているため、ヒロック５が
上方向に成長できずに横方向に成長する現象であり、特
に金属層が広い面積の場合に発生しやすく、最小幅配線
では発生しにくい。つまり、図２（ａ）に示すように最
小幅配線６同士が最小間隔で隣接している場合は発生せ
ず、比較的幅の広い配線７が最小間隔で最小幅配線６と
隣接する箇所にラテラルヒロック５が発生し、短絡する
危険がある。This phenomenon is a phenomenon in which the hillock 5 cannot grow upward but grows laterally because the aluminum layer 3 is usually suppressed by the tungsten silicide layer 4, especially when the metal layer has a large area. And is unlikely to occur with minimum width wiring. That is, as shown in FIG. 2A, the case where the minimum width wirings 6 are adjacent to each other at the minimum interval does not occur, and the relatively wide wiring 7 is located at a position adjacent to the minimum width wiring 6 at the minimum interval. There is a risk that lateral hillocks 5 will be generated and short-circuited.
【０００７】本発明の目的は前記課題を解決した半導体
集積回路装置を提供することにある。An object of the present invention is to provide a semiconductor integrated circuit device which solves the above-mentioned problems.
【０００８】[0008]
【課題を解決するための手段】前記目的を達成するた
め、本発明に係る半導体集積回路装置は、半導体基板上
に形成されたアルミを主成分とする金属層と高融点金属
のシリサイドとの積層構造をもつ複数の配線において、
幅の広い配線と幅の狭い配線とが隣接する場合、その間
に幅の狭いダミー配線を設け、前記幅の広い配線から生
じるラテラルヒロックを前記ダミー配線に接触させるよ
うにしたものである。In order to achieve the above object, a semiconductor integrated circuit device according to the present invention comprises a laminate of a metal layer mainly composed of aluminum and a refractory metal silicide formed on a semiconductor substrate. In multiple wirings with a structure,
If a wide line and a narrow line are adjacent to each other,
Narrow dummy wiring is provided in the
A lateral hillock to the dummy wiring.
It is something that has been done .
【０００９】また前記幅の広い配線が幅３μｍ以上であ
り、前記幅の広い配線と前記ダミー配線及び前記ダミー
配線と前記幅の狭い配線との間隔が１．５μｍ以下であ
る。The above-mentioned wide wiring has a width of 3 μm or more.
The wide wiring, the dummy wiring and the dummy wiring.
The distance between the wiring and the narrow wiring is 1.5 μm or less.
You .
【００１０】[0010]
【作用】本発明の半導体集積回路装置では、比較的幅の
広い第１の配線が最小間隔で別の第２の配線に隣接する
場合に前記第１の配線と第２の配線との間に、最小間隔
をもってフローティング状態のダミー配線を設け、第１
の配線から生じるラテラルヒロックをダミー配線に接触
させることにより、第１の配線と第２の配線とがラテラ
ルヒロックを介して短絡することを防止したものであ
る。In the semiconductor integrated circuit device of the present invention, when a relatively wide first wiring is adjacent to another second wiring at a minimum interval, the first wiring is located between the first wiring and the second wiring. , A dummy wiring in a floating state is provided with a minimum interval,
The first wiring and the second wiring are prevented from being short-circuited via the lateral hillock by contacting the lateral hillock generated from the wiring with the dummy wiring.
【００１１】[0011]
【実施例】次に本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【００１２】図１（ａ）は、本発明の一実施例を示す平
面図、（ｂ）は、図１（ａ）のＡ−Ａ′線断面図であ
る。FIG. 1A is a plan view showing an embodiment of the present invention, and FIG. 1B is a sectional view taken along the line AA 'in FIG. 1A.
【００１３】図１（ａ），（ｂ）において、半導体基板
１上に厚い絶縁膜２を形成し、その上にたとえばスパッ
タ法にて膜厚１．０μｍ程度の１％シリコン含有のアル
ミ層３を形成し、続いて膜厚０．１μｍ程度のタングス
テンシリサイド層４を形成し、周知のホトリソグラフィ
技術及び異方性のリアクティブイオンエッチングにより
所望の金属配線を形成する。1A and 1B, a thick insulating film 2 is formed on a semiconductor substrate 1, and a 1% silicon-containing aluminum layer 3 having a thickness of about 1.0 μm is formed thereon by, for example, a sputtering method. Then, a tungsten silicide layer 4 having a thickness of about 0.1 μm is formed, and a desired metal wiring is formed by a known photolithography technique and anisotropic reactive ion etching.
【００１４】本発明では、上記金属配線パターンにダミ
ー配線８を設けることを特徴としている。つまり、ラテ
ラルヒロック５の発生しやすい比較的幅の広い配線７と
別の配線６とが隣接する場合に、上記幅の広い配線７と
別の配線６との間にダミー配線８を設けることで、ラテ
ラルヒロック５による配線間短絡を防止している。本発
明における幅の広い配線７とは幅３μｍ以上であり、最
小間隔とし１．５μｍ以下としたものである。The present invention is characterized in that a dummy wiring 8 is provided on the metal wiring pattern. In other words, when the relatively wide wiring 7 where the lateral hillock 5 is likely to be generated is adjacent to another wiring 6, the dummy wiring 8 is provided between the wide wiring 7 and another wiring 6. In addition, a short circuit between wirings due to the lateral hillock 5 is prevented. The wide wiring 7 in the present invention has a width of 3 μm or more and a minimum interval of 1.5 μm or less.
【００１５】[0015]
【発明の効果】以上説明したように本発明は、ラテラル
ヒロックの発生しやすい比較的幅の広い配線に沿ってダ
ミー配線を設けることで、配線同士がラテラルヒロック
によって短絡するという問題を解決し、微細化に適した
耐マイグレーション対策を施したアルミ層とタングステ
ンシリサイド層との積層構造をもつ金属配線を提供でき
る。As described above, the present invention solves the problem that the wiring is short-circuited by the lateral hillock by providing the dummy wiring along the relatively wide wiring in which the lateral hillock easily occurs. It is possible to provide a metal wiring having a laminated structure of an aluminum layer and a tungsten silicide layer which has been subjected to migration resistance suitable for miniaturization.
【図１】（ａ）は、本発明の一実施例を示す平面図、
（ｂ）は、図１（ａ）のＡ−Ａ′線断面図である。FIG. 1A is a plan view showing an embodiment of the present invention,
FIG. 2B is a cross-sectional view taken along line AA ′ of FIG.
【図２】（ａ）は、従来例を示す平面図、（ｂ）は、図
２（ａ）のＡ−Ａ′線断面図である。FIG. 2A is a plan view showing a conventional example, and FIG. 2B is a cross-sectional view taken along line AA ′ of FIG. 2A.
１ 半導体基板 ２ 絶縁膜 ３ アルミ層 ４ タングステンシリサイド層 ５ ラテラルヒロック ６ 最小幅配線 ７ 幅の広い配線 ８ ダミー配線 Reference Signs List 1 semiconductor substrate 2 insulating film 3 aluminum layer 4 tungsten silicide layer 5 lateral hillock 6 minimum width wiring 7 wide wiring 8 dummy wiring
Claims (2)
分とする金属層と高融点金属のシリサイドとの積層構造
をもつ複数の配線において、幅の広い配線と幅の狭い配線とが隣接する場合、その間
に幅の狭いダミー配線を設け、前記幅の広い配線から生
じるラテラルヒロックを前記ダミー配線に接触させるよ
うにしたものである ことを特徴とする半導体集積回路装
置。1. A plurality of wirings having a laminated structure of a metal layer mainly composed of aluminum and a refractory metal silicide formed on a semiconductor substrate, wherein a wide wiring and a narrow wiring are adjacent to each other. If
Narrow dummy wiring is provided in the
A lateral hillock to the dummy wiring.
The semiconductor integrated circuit device, characterized in that those were Unishi.
り、前記幅の広い配線と前記ダミー配線及び前記ダミー
配線と前記幅の狭い配線との間隔が１．５μｍ以下であ
ることを特徴とする請求項１に記載の半導体集積回路装
置。2. The method according to claim 1, wherein the wide wiring has a width of 3 μm or more.
The wide wiring, the dummy wiring and the dummy wiring.
The distance between the wiring and the narrow wiring is 1.5 μm or less.
The semiconductor integrated circuit device according to claim 1, characterized in that that.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03166398A JP3143957B2 (en) | 1991-06-11 | 1991-06-11 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03166398A JP3143957B2 (en) | 1991-06-11 | 1991-06-11 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04364042A JPH04364042A (en) | 1992-12-16 |
| JP3143957B2 true JP3143957B2 (en) | 2001-03-07 |
Family
ID=15830681
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP03166398A Expired - Fee Related JP3143957B2 (en) | 1991-06-11 | 1991-06-11 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3143957B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006339406A (en) * | 2005-06-02 | 2006-12-14 | Renesas Technology Corp | Semiconductor device |
-
1991
- 1991-06-11 JP JP03166398A patent/JP3143957B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04364042A (en) | 1992-12-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |