JP3144552B2 - Manufacturing method of nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the same.

[0002]

2. Description of the Related Art Flash EEPROMs are widely used as electrically erasable and erasable nonvolatile semiconductor memory devices. FIG. 1 shows a conventional flash type E
1 shows a cross section of an EPROM. As shown in FIG. 1, this device has a stacked gate structure formed on a silicon substrate 101 and a complicated impurity diffusion structure formed in the silicon substrate 101. This gate structure
Tunnel insulating film 10 formed on silicon substrate 101
2, a floating gate electrode 103 formed on the tunnel insulating film 102, a capacitive insulating film 104 formed on the floating gate electrode 103, and a control gate electrode 105 formed on the capacitive insulating film 104. I have. Insulating sidewalls 109a and 109b are provided on the side surfaces of these stacked gate structures. The impurity diffusion structure includes a first n ⁺ -type high-concentration impurity diffusion layer 110 on the drain side.
And a second n ⁺ -type high-concentration impurity diffusion layer 111. A p-type impurity diffusion layer 112 is located outside these impurity diffusion layers 110 and 111. On the other hand, on the source side, an n ⁺ -type high concentration impurity diffusion layer 113 and an n ⁻ -type low concentration impurity diffusion layer 114 are formed.

When writing data, the silicon substrate 101
The intensity peak of the electric field in the channel length direction formed near the interface between the first n ⁺ -type high concentration impurity diffusion layer 110 and the p-type impurity diffusion layer 112 ing. Hot electrons are formed at and near the electric field intensity peak position, injected into the floating gate electrode 103, and accumulated therein.

At the time of erasing data, electrons in the floating gate electrode 103 are extracted to the n ⁺ -type high-concentration impurity diffusion layer 113 on the source side by tunneling in the tunnel insulating film 102.

[0005]

The above-mentioned conventional nonvolatile semiconductor memory device has the following problems.

First, the data write speed in a conventional flash EEPROM is two orders of magnitude slower than the data write speed in a DRAM. For this reason, the voltage applied to the drain and control gate electrodes during data writing must be increased, which complicates the circuit configuration and the manufacturing process.

It is considered that one of the causes of the low writing speed is that the efficiency of channel hot electrons being injected into the floating gate is low.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to improve the efficiency of channel hot electron injection, and to improve the writing speed or the writing voltage. An object of the present invention is to provide a semiconductor memory device and a method of manufacturing the same.

[0009]

A nonvolatile semiconductor memory device according to the present invention comprises a semiconductor region of a first conductivity type, an insulating film formed on the semiconductor region, and a gate electrode formed on the insulating film. And a second formed in the semiconductor region.
A source region of a conductivity type; a drain region of a second conductivity type formed in the semiconductor region; and a channel region formed in the semiconductor region and located between the source region and the drain region. Wherein the gate electrode overlaps a portion of the drain region, and the portion of the drain region overlapped by the gate electrode has an impurity concentration in a channel length direction. Along with a substantially constant uniform area.

[0010] In a preferred embodiment, a size of the uniform region of the drain region measured along the channel length direction is 50 nm or more.

The channel length may be 0.4 μm or less, and the size of the portion of the drain region measured along the channel length direction may be 80 nm or more.

Preferably, the size of the portion of the drain region measured along the channel length direction is larger than the thickness of the portion of the drain region.

[0013] It is preferable that an impurity concentration of the uniform region included in the portion of the drain region is lower than an impurity concentration of a region of the drain region where the gate electrode does not overlap.

The drain region is electrically connected to a first impurity diffusion layer formed on a surface of the semiconductor region and the first impurity diffusion layer, and has a lower impurity concentration than the first impurity diffusion layer. A second impurity diffusion layer having a high impurity concentration, wherein the part of the drain region is formed from the first impurity diffusion layer, and the second impurity diffusion layer is It is preferable that the semiconductor device be in contact with a wiring for supplying a drain voltage to the region and have a function of transmitting the drain voltage to the first impurity diffusion layer.

The drain region includes a third impurity diffusion layer, the third impurity diffusion layer is formed on a surface of the semiconductor region, and includes a first impurity diffusion layer and a second impurity diffusion layer. May be electrically interconnected to have an impurity concentration higher than the impurity concentration of the first impurity diffusion layer and lower than the impurity concentration of the second impurity diffusion layer.

It is preferable that at least a part of the third impurity diffusion layer in the drain region is overlapped by the gate electrode.

In a preferred embodiment, the channel region includes a first conductivity type impurity diffusion layer formed at a position in contact with the portion of the drain region.
The conductivity type impurity diffusion layer has an impurity concentration higher than the impurity concentration of the other portion of the first conductivity type semiconductor region.

The drain region includes a second conductivity type low concentration impurity diffusion layer provided between the second impurity diffusion layer and the semiconductor region, and the low concentration impurity diffusion layer is May have an impurity concentration lower than the impurity concentration of the impurity diffusion layer.

The channel region includes a first conductivity type impurity diffusion layer formed at a position in contact with the portion of the drain region, and the first conductivity type impurity diffusion layer is formed of the first conductivity type. May have a higher impurity concentration than the impurity concentration of the semiconductor region.

According to another aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising: a semiconductor region of a first conductivity type; an insulating film formed on the semiconductor region; a gate electrode formed on the insulating film; A second conductivity type source region formed in the region, a second conductivity type drain region formed in the semiconductor substrate, and a second conductivity type drain region formed in the semiconductor substrate, between the source region and the drain region. Wherein the gate electrode overlaps a portion of the drain region, and the portion of the drain region overlaps the gate electrode. The size measured along the channel length direction is larger than the lateral diffusion length of the second conductivity type impurity in the drain region.

It is preferable that a size of the portion of the drain region overlapping the gate electrode measured along a channel length direction is larger than a thickness of the portion of the drain region.

[0022] The part of the drain region may include an impurity implanted by an oblique ion implantation method.

The channel length may be 0.4 μm or less, and the size of the part of the drain region measured along the channel length direction may be 80 nm or more.

It is preferable that the impurity concentration of the portion of the drain region is lower than the impurity concentration of a region of the drain region where the gate electrode does not overlap.

The drain region is electrically connected to a first impurity diffusion layer formed on a surface of the semiconductor region and the first impurity diffusion layer. A second impurity diffusion layer having a high impurity concentration, wherein the part of the drain region is formed from the first impurity diffusion layer, and the second impurity diffusion layer is It is preferable that the semiconductor device be in contact with a wiring for supplying a drain voltage to the region and have a function of transmitting the drain voltage to the first impurity diffusion layer.

The drain region includes a third impurity diffusion layer, and the third impurity diffusion layer is formed on a surface of the semiconductor region, and includes a first impurity diffusion layer and a second impurity diffusion layer. May be electrically interconnected to have an impurity concentration higher than the impurity concentration of the first impurity diffusion layer and lower than the impurity concentration of the second impurity diffusion layer.

Preferably, at least a part of the third impurity diffusion layer in the drain region is overlapped by the gate electrode.

In a preferred embodiment, the channel region includes a first conductivity type impurity diffusion layer formed at a position in contact with the portion of the drain region.
The conductivity type impurity diffusion layer has an impurity concentration higher than the impurity concentration of the semiconductor region of the first conductivity type.

The drain region includes a second conductivity type low-concentration impurity diffusion layer provided between the second impurity diffusion layer and the semiconductor region. May have an impurity concentration lower than the impurity concentration of the impurity diffusion layer.

In a preferred embodiment, the channel region includes a first conductivity type impurity diffusion layer formed at a position in contact with the portion of the drain region, and the first conductivity type impurity diffusion layer includes: The first conductive type semiconductor region has an impurity concentration higher than that of the semiconductor region.

The nonvolatile semiconductor memory device according to the present invention
A first conductive type semiconductor region, an insulating film formed on the semiconductor region, a gate electrode formed on the insulating film, and a second conductive type source region formed in the semiconductor region; A nonvolatile semiconductor memory device comprising: a second conductivity type drain region formed in the semiconductor region; and a channel region formed in the semiconductor region and located between the source region and the drain region. The intensity peak position of the channel length direction electric field formed on the surface of the semiconductor region at the time of data writing is shifted toward the center of the channel region from the edge of the gate electrode, and the shift The amount is greater than the lateral diffusion length of the second conductivity type impurity in the drain region.

According to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, a semiconductor region of a first conductivity type; an insulating film formed on the semiconductor region; a gate electrode formed on the insulating film; A second conductivity type source region formed in the semiconductor region, a second conductivity type drain region formed in the semiconductor region, and a second conductivity type drain region formed in the semiconductor region;
A method of manufacturing a nonvolatile semiconductor memory device including a channel region located between the source region and the drain region, wherein the semiconductor region is formed before forming the source region and the drain region. A step of covering a region to be a channel region with a mask, and a step of forming a second conductivity type impurity diffusion layer functioning as at least a part of the drain region in a region of the semiconductor region not covered by the mask; Removing the mask and forming the gate electrode so as to cover both the channel region and a part of the second conductivity type impurity diffusion layer functioning as a part of the drain region. The step of forming the gate may include removing the portion of the second conductivity type impurity diffusion layer that is overlapped by the gate electrode. It is performed to include the impurity concentration constant uniform region laterally along the channel length direction.

According to another method of manufacturing a nonvolatile semiconductor memory device according to the present invention, there is provided a semiconductor device of a first conductivity type, an insulating film formed on the semiconductor region, and a gate electrode formed on the insulating film. A source region of the second conductivity type formed in the semiconductor region, a drain region of the second conductivity type formed in the semiconductor region, and the source region and the drain region formed in the semiconductor region. And a channel region located between the non-volatile semiconductor memory device and the source region and the drain region, before forming the source region and the drain region, at least a region of the semiconductor region to be the channel region and A step of covering the region to be the source region with a mask, and forming at least a part of the drain region in a region of the semiconductor region not covered by the mask. Forming a functioning second conductivity type impurity diffusion layer; removing the mask; and forming the gate electrode so as to cover a part of the second conductivity type impurity diffusion layer functioning as a part of the drain region. Forming a gate, wherein the portion of the second conductivity type impurity diffusion layer overlapped by the gate electrode has a constant impurity concentration in a lateral direction along a channel length direction. Is performed so as to include the uniform region of

In a preferred embodiment, the size of the uniform region of the second conductivity type impurity diffusion layer measured along the channel length direction is 50 nm.
The processing is executed as described above.

The step of forming the gate is performed such that a size of the portion of the second conductivity type impurity diffusion layer overlapped by the gate electrode, measured along the channel length direction, is 80 nm or more. Is also good.

In the gate forming step, the size of the portion of the second conductivity type impurity diffusion layer overlapped by the gate electrode measured along the channel length direction may be equal to the size of the second conductivity type impurity diffusion layer. Preferably, it is performed to be larger than the thickness of the part.

After the formation of the gate electrode, a high-level doping step of completing the formation of the source region and the drain region by implanting a second conductivity type impurity into the semiconductor region using at least the gate electrode as a mask is further included. Is preferred.

After the formation of the gate electrode and before the high-level doping step, a second conductivity type impurity is implanted into the semiconductor region using the gate electrode as a mask, thereby forming an impurity in the second conductivity type impurity diffusion layer. Forming another second conductivity type impurity diffusion layer having an impurity concentration higher than the impurity concentration in a self-aligned manner with respect to the gate electrode; and forming the second second conductivity type impurity diffusion layer after forming the second second conductivity type impurity diffusion layer. Forming a side wall spacer on a side surface of the gate electrode and the second gate electrode before the level doping step.

After forming the mask and before removing the mask, the method further includes implanting a first conductivity type impurity into a region of the semiconductor region that is not covered by the mask. Preferably, the channel region has a first conductivity type impurity diffusion layer at a position in contact with the second conductivity type impurity diffusion layer.

Still another non-volatile semiconductor memory according to the present invention comprises a semiconductor region of a first conductivity type; an insulating film formed on the semiconductor region; a gate electrode formed on the insulating film; A second conductivity type source region formed in the region, a second conductivity type drain region formed in the semiconductor region, and a second conductivity type drain region formed in the semiconductor region between the source region and the drain region. A drain region, wherein the drain region has a first impurity diffusion layer having an impurity concentration substantially constant along a channel length direction; and a first impurity diffusion layer having a substantially constant impurity concentration along a channel length direction. A second impurity diffusion layer having an impurity concentration higher than the impurity concentration of the second impurity diffusion layer. It overlaps with a part of.

In writing data, it is preferable that an inversion layer is formed on at least the surface of the first impurity diffusion layer.

Still another non-volatile semiconductor memory device according to the present invention is a semiconductor device comprising: a first conductivity type semiconductor region; an insulating film formed on the semiconductor region; a gate electrode formed on the insulating film; A source region of the second conductivity type formed in the semiconductor region, a drain region of the second conductivity type formed in the semiconductor region, and a source region and the drain region formed in the semiconductor region. A non-volatile semiconductor storage device comprising a channel region located between
The drain region has a first impurity diffusion layer having an impurity concentration at least such that an inversion layer is formed on the surface at the time of data writing, and a first impurity diffusion layer having an impurity concentration higher than that of the first impurity diffusion layer. And the gate electrode overlaps the whole of the first impurity diffusion layer and a part of the second impurity diffusion layer in the drain region.

Still another non-volatile semiconductor memory device according to the present invention comprises a semiconductor region of the first conductivity type, an insulating film formed on the semiconductor region, a gate electrode formed on the insulating film, A source region of the second conductivity type formed in the semiconductor region, a drain region of the second conductivity type formed in the semiconductor region, and a source region and the drain region formed in the semiconductor region. A non-volatile semiconductor storage device comprising a channel region located between
The drain region includes a high-concentration impurity diffusion layer that exhibits a substantially constant drain potential regardless of the potential of the gate electrode, and a low-concentration impurity diffusion layer whose surface potential distribution changes according to the potential of the gate electrode. And the gate electrode overlaps the entire low concentration impurity diffusion layer of the drain region and a part of the high concentration impurity diffusion layer.

[0044]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a nonvolatile semiconductor memory device according to the present invention, the position of a pn junction formed between a drain region and a channel region on the surface of a semiconductor substrate moves from a gate edge toward the inside of a channel region. The shift is larger than the “transverse diffusion length”. According to the conventional manufacturing method, since the drain region is formed after the gate is formed, the gate overlap portion of the drain region is formed by diffusion of the implanted impurity in a subsequent process in a lateral direction. In that case, the size of the overlap portion is about the lateral diffusion length.

The intensity distribution of the horizontal electric field formed in the channel region at the time of data writing has a peak near the pn junction. In the present invention, the position of the peak is shifted from the gate edge to a place deeply penetrating into the inside while the peak of the electric field intensity is kept high. As a result, a large amount of hot electrons generated near the peak position of the electric field intensity can be efficiently injected into the floating gate. From the viewpoint of data writing, it is preferable that the impurity concentration of the drain region below the floating gate has a distribution such that the impurity concentration decreases sharply from the drain region to the channel region.

(First Embodiment) A first embodiment of a nonvolatile semiconductor memory device according to the present invention will be described below with reference to FIG. The storage device according to the present embodiment is an n-channel MOS flash EEPROM.

The nonvolatile semiconductor memory device of the present embodiment
As shown in FIG. 2, it is formed in the p-type semiconductor region of the single-crystal silicon substrate 1 including the p-type semiconductor region (p-type impurity concentration: for example, 5 × 10 ¹⁵ to 5 × 10 ¹⁶ cm ⁻³ ). The single-crystal silicon substrate 1 has a p-channel MO (not shown).
An n-type well in which an S transistor is formed may be included. Although only a single memory cell is shown in the figure for simplification, in reality, many memory cells are integrated on the same substrate. Peripheral circuits and the like (not shown) for writing data to these memory cells or reading data from the memory cells are provided on the substrate.

Each memory cell includes a tunnel insulating film (first insulating film) 2 formed on a silicon substrate 1, a floating gate electrode (first gate electrode) 3 formed on the tunnel insulating film 2, A capacitive insulating film (second insulating film) 4 formed on the floating gate electrode 3, and a control gate electrode (second gate electrode) 5 formed on the capacitive insulating film 4. The tunnel insulating film 2 is preferably made of a silicon substrate 1
It is formed by thermally oxidizing the surface of. The thickness of the tunnel insulating film 2 is typically about 8 to about 10 nm. The floating gate electrode 3 is formed from, for example, a polycrystalline silicon film. The thickness of the floating gate electrode 3 is typically about 100 to about 200 nm. The capacitance insulating film 4 can be formed from, for example, an ONO film. The thickness of the capacitance insulating film 4 is about 15 to about 22 nm. Control gate electrode 5
Is formed, for example, from a polycrystalline silicon film, and has a thickness of about 150 to about 300 nm. These electrodes may be formed from a conductive film other than the polycrystalline silicon film.

This memory cell includes an n-type source region 11a and a drain region 11 formed in silicon substrate 1.
b and the source region 11a formed in the silicon substrate 1.
And a channel region located between the drain region 11b. The impurity concentration of the source region 11a and the drain region 11b in the present embodiment ranges from 5 × 10 ¹⁹ to 5 × 10 ²⁰ cm ⁻³ near the surface of the silicon substrate 1.
It is. The impurity concentration of the channel region is
5 × 10 ¹⁶ to 5 × 10 ¹⁷ cm ^-3 in the vicinity of the surface.

A feature of the device of this embodiment is that the floating gate electrode 3 overlaps a part of the drain region 11b (hereinafter referred to as "overlap portion"). In addition, the "uniform region" in which the impurity concentration is constant in the lateral direction along the channel length direction is included. The impurity concentration on the substrate surface in the uniform region is 5 × 10 ¹⁹ to 5 × 10 ²⁰ cm ⁻³ . The size (L) measured along the channel length direction of the uniform region
_UNI ) is in the range of 50 nm to 100 nm in the present embodiment. The size (L _OVR ) measured along the channel length direction of the overlap portion is:
It is about 70 nm larger than L _UNI . The overlap length (L _OVR ) is the channel length (L _ch : 400) of the present embodiment.
nm).

In a conventional nonvolatile semiconductor memory device
Also, the floating gate electrode 103 is connected to a part of the drain region.
-Although it overlaps, the overlap part is
After the formation of the floating gate electrode 103,
Impurities implanted in a self-aligned manner
101 formed by heat diffusion in the lateral direction inside
Things. Therefore, the impurities in the overlap area
The concentration is measured from immediately below the edge of the floating gate electrode 103.
It decreases monotonically toward the inside of the channel region. say
In other words, the “uniform area” of the present embodiment is
In the semiconductor memory device, actual
It does not exist qualitatively. In the conventional case,
Overlap measured along the channel length direction
Top length (L _ovr) Is at most about 15% of the channel length
There is only below.

The nonvolatile semiconductor memory device according to the present embodiment
Below the floating gate electrode 3, it has an impurity profile distinguished from the prior art, whereby the following remarkable effects are achieved.

In the present non-volatile semiconductor memory device, since a part of the drain region 11b extends laterally deep below the floating gate electrode 3, the electric field in the channel length direction formed on the surface of the silicon substrate 1 at the time of data writing. (The maximum electric field intensity point) shifts from the edge of the floating gate electrode 3 toward the center of the channel region.

FIG. 3 shows an overlay of the drain region 11b.
The cross-sectional structure of the top part, the impurity concentration distribution in that part, and
3 schematically shows the electric field intensity distribution. Floating gate electrode
3 from the drain side edge toward the center of the channel region
Tte length L_UNIArea, the surface of the drain region
Pure substance concentration N_dIs substantially constant in the lateral direction. This area
"Uniform area". Uniform area of overlap
In the region except for the region, as shown in FIG.
Surface impurity concentration N of region 11b_dIs the center of the channel region
It decreases monotonically toward the part. Drain region 11b
Junction semiconductor formed between the semiconductor and the p-type semiconductor region
Depth measured from the surface (joining depth) X_JIs the drain territory
This corresponds to the thickness of the region 11b. In the present embodiment,
Joining depth X _JOverlap length L_OVRIs big. Figure
3 shows a tunnel between the silicon substrate 1 and the data writing.
The strength of the electric field in the channel length direction formed at the interface with the insulating film 2
The spatial distribution of the degree E is shown. The peak of this field strength
Is formed at the interface between the silicon substrate 1 and the tunnel insulating film 2.
Where the p-type semiconductor region and the n-type semiconductor region are in contact
According to the present embodiment located in the portion, the uniform area floats.
Since it exists below the idle gate electrode 3, the impurity concentration
The drain region 11b is connected to the floating gate while suppressing the
Under the contact electrode 3 can be extended deeply in the lateral direction. This
The extended portion of the drain region is referred to as “N-ex
It may be called "strain". This N-Exten
If the impurity concentration of the drain region is sufficiently high,
The drain potential is kept high even at the tip of
Of the electric field in the channel length direction at the tip of the conduction region 11b
Increase the degree peak. Therefore, given the voltage condition
Generation rate of hot electrons increases
You. This in turn reduces the voltage applied to the drain region.
The hot electron generation
Can result in

FIG. 4A schematically shows an intensity distribution curve 41 of the electric field in the channel length direction formed near the surface of the silicon substrate 1 in this embodiment. FIG. 4 (b)
1 schematically shows an intensity distribution curve 43 of an electric field in a channel length direction formed on the surface of a silicon substrate 101 in the conventional nonvolatile semiconductor memory device of FIG. FIG. 4 (a)
As can be seen from (b) and (b), according to the present embodiment,
The position P of the intensity peak of the electric field in the channel length direction formed on the surface of the silicon substrate 1 can be made closer to the center of the channel region from the gate edge O, and the height of the peak can be kept large. As a result, the floating gate electrode 3
Will widely cover the hot electron generation region, and the generated hot electrons can be efficiently captured by the floating gate electrode 3. When the position P ′ of the electric field intensity peak is located near the gate edge O as in the related art, only a part of the generated hot electrons is injected into the floating gate electrode 103, and most of the generated hot electrons flow into the drain region 110. It is thought that there is. On the other hand, in the present embodiment, the position where hot electrons are generated is intentionally shifted from the vicinity of the edge of the floating gate electrode 3 toward the center of the channel region.
Most of the generated hot electrons are transferred to the floating gate electrode 3
, The injection efficiency is significantly improved.

Note that the overlap portion is a "uniform region".
In other words, when the impurity concentration in the overlap portion monotonously decreases along the channel length direction, the potential at the end of the drain region 11b decreases. ), A low electric field peak as shown by the broken line 42 is obtained.

According to the device of this embodiment, the write operation is performed in a state where a voltage of 5 V is applied to the drain region 11b, a voltage of 7 to 9 V is applied to the control gate electrode 5, and a voltage of 0 V is applied to the source region 11a and the silicon substrate 1. You. In this case, the electrons emitted from the source region 11a acquire energy from the channel length direction electric field in the channel region while moving in the channel region toward the drain region 11b,
Hot electrons are generated in the high electric field region at the end of the drain region 11b, and are injected into the floating gate electrode 3 beyond the barrier between the silicon substrate 1 and the tunnel insulating film 2. As described above, according to the device of the present embodiment, the impurity concentration in the portion where the drain region 11b overlaps the floating gate electrode 3 is relatively high, and the overlap length is long. For this reason, the energy of the electrons becomes sufficiently high at a position shifted from directly below the edge of the floating gate electrode 3 toward the center of the channel region, so that high-energy electrons are efficiently injected into the floating gate electrode 3. You.

According to the present non-volatile semiconductor memory device, in the erasing operation, a voltage of -6 to -8 V is applied to the control gate electrode 5, a voltage of 5 to 6 V is applied to the drain region 11b, and a voltage of 0 V is applied to the source region 11a and the silicon substrate 1. Run in state.
In this case, the electrons in the floating gate electrode 3 are drained by the tunnel current flowing through the tunnel insulating film 2 to the drain region 11b.
Pull out. Since the electron tunneling phenomenon occurs in the portion of the tunnel insulating film 2 where the strongest electric field is formed, in the above-described voltage application state, the extraction of electrons occurs at the drain-side edge portion of the floating gate electrode 3. Since the position of the electron injection at the time of the writing operation and the position of the tunneling of the electrons at the time of the erasing operation are different, the deterioration of the tunnel insulating film 2 is small and the reliability is excellent. Note that the erasing operation can also be performed by extracting electrons accumulated in the floating gate electrode 3 to the source region 11a.

Hereinafter, a method for manufacturing the device of the present embodiment will be described with reference to FIGS. 5 (a) to 5 (d).

First, as shown in FIG. 5A, a mask 51 for covering a portion to be a channel region on the surface of the silicon substrate 1 is formed. The mask 51 may be, for example, a resist pattern formed in a lithography process. Before forming the mask 51, it is preferable to protect the surface of the silicon substrate 1 with a thin oxide film 50. The size of the mask 51 measured along the channel length direction is, for example, 0.3 to 0.4 μm.

Next, a mask on the surface of the silicon substrate 1
Arsenic as an n-type impurity for the region not covered by 51
(As) Ions are implanted. Acceleration energy of ion implantation
Is, for example, 20 to 40 keV, and the dose is, for example, 5
× 10¹⁴From 5 × 10^Fifteencm ^-2It is. Thus, FIG.
As shown in (b), the source region 11a and the drain
A region 11b is formed on the substrate 1.

After removing the mask 51 and the protective oxide film 50, a tunnel insulating film 2 is formed on the surface of the semiconductor substrate 1 by a thermal oxidation method, as shown in FIG. Thereafter, a first polycrystalline silicon film 3 ′ serving as the floating gate electrode 3 is deposited on the tunnel insulating film 2 by a chemical vapor deposition method. After forming the capacitive insulating film 4 on the first polycrystalline silicon film 3 ', a second polycrystalline silicon film 5' to be the control gate electrode 5 is deposited on the capacitive insulating film 4 by a chemical vapor deposition method. I do.

Next, as shown in FIG. 5D, a resist mask 52 for defining a gate electrode pattern is formed on the second polycrystalline silicon film 5 'by using a known lithography technique. Using a known dry etching technique, the second polycrystalline silicon film, the capacitor insulating film 4 and the first polycrystalline silicon film 3 'are sequentially patterned. Thus, the device of FIG. 2 is formed.

The resist mask 52 includes a part of the source region 11a, the channel region, and the drain region 11a.
It is formed so as to cover a part of b. Drain region 11b
The portion covered by the resist mask 52 defines the size of the overlap portion (overlap length L _OVR ) of the drain region 11b.

The annealing for activating the impurities is performed by the above n
It is performed at an arbitrary stage after the implantation of the type impurity ions. By this annealing, the n-type impurities contained in the source region 11a and the drain region 11b diffuse in all directions. The diffusion length varies depending on the conditions of the annealing and other high-temperature processes, but is smaller than 50 nm when manufacturing the device of the present embodiment. This value is smaller than the size of the overlap portion measured along the channel length direction, that is, the overlap length (L _ovr ). Further, since the overlap portion of the present embodiment is formed not by lateral diffusion but by the impurity implanted from the surface of the silicon substrate 1, the impurity concentration in the overlap portion along the channel length direction is increased. A certain “uniform area” is included in the horizontal direction. In addition,
It goes without saying that the impurity concentration in the “uniform region” changes along the depth direction from the surface of the silicon substrate 1.
In addition to the uniform region, the overlap portion includes, at the end, a portion where the impurity concentration changes along the channel length direction due to the lateral diffusion of the impurity.

According to the manufacturing method of this embodiment, the source region 11a and the drain region 11b are formed before the formation of the floating gate electrode 3. As a result, an overlapping portion including a “uniform region” in which the impurity concentration is substantially constant in the lateral direction along the channel length direction is formed in the floating gate electrode 3.
Below. When the source region 11a and the drain region 11b are formed after the formation of the floating gate electrode 3 as in the related art, the overlap portion is formed by the lateral diffusion of the implanted impurities using the gate electrode as a mask. The impurity concentration of the portion monotonously decreases along the channel length direction. Further, in the case of the conventional manufacturing method, the size measured along the channel length direction of the overlap portion (L _{OV R)} is only the diffusion length of about impurity drain region 11b. In addition, also by the method of this embodiment,
Since the impurity diffuses in the horizontal direction, the uniform region functions as a source of impurity for the non-uniform region. Strictly speaking, it is considered that the impurity concentration slightly decreases toward the channel region even in the uniform region.

The device shown in FIG. 2 is actually covered with an interlayer insulating film (not shown), and is electrically connected to a peripheral circuit (not shown) by wiring formed in and / or on the interlayer insulating film. Connected. These interlayer insulating films,
Known wiring and peripheral circuit structures can be used.

According to such a nonvolatile semiconductor memory device, the writing speed is increased (for example, to 10 nanoseconds or less).
Instead, lower the write voltage (for example, 4.0 V
Below). In addition, since the distribution of the impurity concentration has a structure substantially symmetrical with respect to a plane perpendicularly crossing the center of the channel region, writing and reading can be performed by controlling the voltage applied to either the source or the drain. Erase and read operations can be performed. This significantly improves the degree of freedom in circuit design.

(Second Embodiment) Hereinafter, a second embodiment of the nonvolatile semiconductor memory device according to the present invention will be described with reference to FIG. The storage device according to the present embodiment is an n-channel MOS flash EEPROM.

As shown in FIG. 6, the nonvolatile semiconductor memory device of the present embodiment is formed in a p-type semiconductor region of a single crystal silicon substrate 1 including a p-type semiconductor region. FIG.
Describes only a single memory cell, but in reality many memory cells are integrated on the same substrate.

The device of this embodiment has almost the same configuration as the device of FIG. 2 except for the configuration of the impurity diffusion layer formed in the semiconductor region. Therefore, the description of the structure common to both devices will be simplified. The differences will be described in detail.

The device shown in FIG. 6 includes a tunnel insulating film 2 formed on a single crystal silicon substrate 1 including a p-type semiconductor region,
A floating gate electrode 3 formed on the tunnel insulating film 2;
The capacitor includes a capacitance insulating film formed on the floating gate electrode and a control gate electrode formed on the capacitance insulating film. On the side surfaces of these gate electrodes 3 and 5, insulating sidewalls 9a and 9b are formed.

This device includes an n ⁺ -type high-concentration source region 11 a and an n ⁺ -type high-concentration drain region 11 b formed in the silicon substrate 1, and an n ⁻ -type low-concentration source region formed in the silicon substrate 1. A region 6a and an n ⁻ -type low-concentration drain region 6b are provided. A channel region exists between the n ⁻ -type low-concentration source region 6a and the n ⁻ -type low-concentration drain region 6b.

The features of this embodiment are as follows: (1) The floating gate electrode 3 overlaps a part of the low-concentration drain region 6b, and the impurity concentration in the overlapping part is in the channel length direction. (2) the impurity concentration of the uniform region is not included in the region (11b) of the drain region which is not overlapped by the floating gate electrode 3; To be lower than. In other words, the drain region in the storage device of the present embodiment includes a relatively low-concentration impurity diffusion layer (6b) and a relatively high-concentration impurity diffusion layer (11b).

In this embodiment, the size (L _OVR ) of the overlap portion measured along the channel length direction is 1
The size (L _UNI ) measured along the channel length direction of the uniform region is about 100 nm. The overlap length L _OVR is larger than the thickness of the overlap portion (= the junction depth of that portion X _j = about 50 nm). Further, the impurity concentration on the surface of the silicon substrate 1 in the overlap portion is 1 × 10 ¹⁸ cm ^-3 to 1 ×
In contrast to 10 ¹⁹ cm ⁻³ , the impurity concentration in the drain region not covered by the floating gate electrode 3 is:
It is higher than this and is 1 × 10 ²⁰ cm ⁻³ or more.

According to the present embodiment, the impurity concentration differs between the overlapped portion of the drain region and the other portion, and an optimum value can be given to each portion independently. It is desired that the impurity concentration of the high-concentration drain region 11b that is in electrical contact with the wiring be as high as possible from the viewpoint of reducing contact resistance. During the erase operation, holes may be injected into the tunnel insulating film 2 and the tunnel insulating film 2 may be easily deteriorated. In order to avoid this inconvenience, in the present embodiment, the impurity concentration of the overlap portion is set to be lower so as to be within the above range.

The device of this embodiment also operates in the same manner as the device of the first embodiment, and exhibits the same effects as those of the device of the first embodiment. In addition to this effect, according to the present embodiment, while keeping the source / drain contact resistance low, the impurity concentration of the overlap portion is optimized in order to prevent the deterioration of the tunnel insulating film 2 during the erase operation. The effect that can be obtained is obtained.

Hereinafter, a method of manufacturing the storage device according to the present embodiment will be described with reference to FIGS.

First, as shown in FIG. 15A, after forming a photoresist pattern 12 on a silicon substrate 1 whose surface is covered with a protective oxide film 50, arsenic ions are implanted into the silicon substrate 1. The width (the size measured along the channel length direction) of the photoresist pattern 12 is 0.3.
To 0.4 μm. In this embodiment, the arsenic ion implantation acceleration energy is 30 to 60 keV, and the dose is 5 × 10 ¹³ to 5 × 10 ¹⁴ cm ⁻² . By this ion implantation, low-concentration impurity diffusion layers 6a 'and 6b' are formed in regions of the semiconductor region not covered with the photoresist pattern 12.

After removing the photoresist pattern 12 and the protective oxide film 50, as shown in FIG. 15B, a laminated gate comprising a tunnel insulating film 2, a floating gate electrode 3, a capacitive insulating film 4, and a control gate electrode 5 is formed. Form the structure. This stacked gate structure includes a step of forming a tunnel insulating film 2 by a thermal oxidation method, and a first step of forming a floating gate electrode 3.
Depositing a polycrystalline silicon film on the tunnel insulating film 2 by chemical vapor deposition, forming a capacitive insulating film 4 on the first polycrystalline silicon film, and forming a second control gate electrode 5 It is formed by a series of manufacturing process steps including a step of depositing a polycrystalline silicon film on the capacitive insulating film 4 by a chemical vapor deposition method, and a step of patterning these multilayer films using known lithography and etching techniques. You. In the present embodiment, the width of the stacked gate structure (the size measured along the channel length direction) is 0.5.
To 0.6 μm.

In the lithography step for patterning the stacked gate structure, the degree of overlap between the floating gate electrode 3 and the low-concentration impurity diffusion layers 6a 'and 6b' is symmetrical with respect to a plane perpendicular to the center of the channel region. The alignment between the stacked gate structure and the low-concentration impurity diffusion layers 6a 'and 6b' is performed. The size of the overlapping portion (overlap length) between the floating gate electrode 3 and the low-concentration impurity diffusion layer 6b 'is:
In the case of the present embodiment, the thickness is 0.05 to 0.15 μm.
A displacement of about 0.1 μm or less may occur in the above alignment, but this does not significantly affect device performance.

The degree of overlap between the floating gate electrode 3 and the low concentration impurity diffusion layers 6a 'and 6b' is as follows.
It is not necessary to be symmetric about a plane perpendicular to the center of the channel region. This applies to other embodiments described later.

Next, as shown in FIG. 15C, an insulating sidewall spacer (thickness: about 100 to about 15) is formed by using a known thin film deposition technique and an etch back technique.
(0 nm) After forming 9a and 9b on the side wall of the stacked gate structure, arsenic ions are implanted into the silicon substrate 1. The arsenic ion implantation acceleration energy is 30 to 60 keV, and the dose is 5 × 10 ¹⁴ to 5 × 10 ¹⁵ cm ⁻² . By this ion implantation, high-concentration impurity diffusion layers 11a and 11b are formed in a region other than the region where the stacked gate structure is provided on the surface of the silicon substrate 1. In the low concentration impurity diffusion layers 6a 'and 6b', arsenic ions are not additionally implanted into the regions covered with the stacked gate structure and the sidewall spacers, but high-level arsenic ions are implanted into other regions. Doping is performed.
Therefore, some of the low-concentration impurity diffusion layers 6a 'and 6b' function as the low-concentration source region 6a and the low-concentration drain region 6b, while the other portions correspond to the high-concentration impurity diffusion layers 11a and 11b. Change. The high concentration impurity diffusion layers 11a and 11b function as a high concentration source region and a high concentration drain region, respectively.

As described above, low concentration source region 6a and low concentration drain region 6b are formed by impurity ions implanted from the surface of the semiconductor substrate. These impurity ions thermally diffuse during a plurality of high-temperature process steps performed after the implantation. Therefore, the low-concentration drain region 6b in the finally completed nonvolatile semiconductor memory device is
It is thicker than immediately after the implantation, and its ends slightly expand toward the center of the channel region. Similarly, the impurity in the high-concentration drain region 11b also diffuses, so that its end slightly spreads toward the center of the channel region, and enters the lower portion of the sidewall spacer 9b. This also occurs in the source region. However, even if such impurity diffusion occurs, a uniform region where the impurity concentration hardly changes along the channel length direction exists in the overlapping portion of the low-concentration drain region 6b covered by the floating gate electrode 3. .

After the formation of the source / drain regions is completed, well-known manufacturing steps such as formation of an interlayer insulating film and formation of a multilayer wiring are performed to manufacture a final nonvolatile semiconductor memory device.

(Third Embodiment) Hereinafter, a third embodiment of the nonvolatile semiconductor memory device according to the present invention will be described with reference to FIG. The storage device of the present embodiment is also an n-channel MOS flash EEPROM.

As shown in FIG. 7, the nonvolatile semiconductor memory device of this embodiment is formed in a p-type semiconductor region of a single crystal silicon substrate 1 including a p-type semiconductor region. FIG.
Describes only a single memory cell, but in reality many memory cells are integrated on the same substrate.

The device of this embodiment has almost the same configuration as the device of FIG. 6 except for the configuration of the impurity diffusion layer formed in the semiconductor region. Therefore, the description of the structure common to both devices will be omitted. The differences will be described in detail.

The features of this embodiment are as follows: (1) The floating gate electrode 3 overlaps with a part of the drain region, and the impurity concentration in the overlapping part is horizontal along the channel length direction. (2) The drain region includes a first impurity diffusion layer 6b having a relatively low impurity concentration and a second impurity diffusion layer 11b having a relatively high impurity concentration. Including,
And (3) the "whole" of the first impurity diffusion layer 6b and the second
Part of the impurity diffusion layer 11 b is overlapped by the floating gate electrode 3.

Incidentally, the structure of the source region includes a first impurity diffusion layer 6a having a relatively low impurity concentration and a second impurity diffusion layer 11a having a relatively high impurity concentration, similarly to the structure of the drain region. In addition, the entire first impurity diffusion layer 6 a and a part of the second impurity diffusion layer 11 a are overlapped by the floating gate electrode 3.

In writing data, the floating gate electrode 3
Rise (for example, to 3.3 to 5 volts), the first impurity diffusion layer 6 having a relatively low impurity concentration.
An inversion layer is formed on at least the surface of b. This inversion layer extends from the edge of the second impurity diffusion layer 11b to the channel region and is located immediately below the floating gate electrode 3. Due to the presence of such an inversion layer, the second impurity diffusion layer 11b
Of the first impurity diffusion layer 6b is transmitted to the channel region side edge of the first impurity diffusion layer 6b with almost no drop.

FIG. 8A shows the surface potential (potential) of the drain region and its vicinity during data writing. As can be seen from FIG. 8A, at the time of data writing, the potential on the surface of the first impurity diffusion layer 6b has a value substantially equal to the potential of the second impurity diffusion layer 11b (drain potential: 5 volts, for example). , At the boundary between the first impurity diffusion layer 6b and the channel region. Due to such a steep change in potential, a strong electric field peak is formed as shown in FIG.

In the present embodiment, the first impurity diffusion layer 6b
Is entirely covered with the floating gate electrode 3. Therefore, the inversion layer formed in the first impurity diffusion layer 6b by applying a positive potential to the floating gate electrode 3 extends from the edge of the second impurity diffusion layer 11b to the channel region without interruption. As a result, the second impurity diffusion layer 11
The high potential (drain potential) of the first impurity diffusion layer 6
While maintaining a high value even in b, the light is transmitted to a portion adjacent to the channel region.

By lowering the potential of the floating gate electrode 3, the strong inversion layer changes to a weak inversion layer, and when the (weak) inversion layer disappears, as shown in FIG. The surface potential (potential) of the impurity diffusion layer 6b decreases as approaching the channel region. As a result, the electric field at the boundary between the first impurity diffusion layer 6b and the channel region is reduced.

As can be clearly understood from a comparison between FIGS. 8A and 8B, the first impurity diffusion layer 6b uses the potential of the second impurity diffusion layer 11b in accordance with the potential of the floating gate electrode 3 as the source. Transmit to the area side or relax.

The impurity concentration of the first impurity diffusion layer 6b is
At the time of data writing, the impurity concentration (for example, 5 ×) is such that an inversion layer is formed on the surface of the first impurity diffusion layer 6b.
It is preferably 10 ¹⁷ to 1 × 10 ¹⁹ cm ⁻³ ). Such a first impurity diffusion layer 6b is formed on the floating gate electrode 3
When an appropriate potential is applied to the second impurity diffusion layer 1 having a high impurity concentration, the inversion layer is formed.
1b can exhibit the same function electrically.

In this embodiment, the drain region has a high impurity concentration portion (the second impurity diffusion layer 11) showing a substantially constant drain potential irrespective of the potential of the floating gate electrode 3.
b) and a low impurity concentration portion (first impurity diffusion layer 6b) in which the surface potential changes from a level equal to the drain potential to a level lower than the drain potential according to the potential of the floating gate electrode 3, and , First impurity diffusion layer 6
b and a part of the second impurity diffusion layer 11 b are overlapped by the floating gate electrode 3. With such a configuration, it is possible to form a strong electric field at a position shifted from the edge of the floating gate electrode 3 toward the center of the channel region during data writing.

At the time of data erasure, zero or negative potential is applied to floating gate electrode 3 while supplying a high potential (drain potential) to second impurity diffusion layer 11b. At this time, since the first impurity diffusion layer 6b relaxes the drain potential, band-to-band tunneling due to band bending is suppressed, and the problem that the gate oxide film 2 traps holes can be avoided.

Next, a method of manufacturing the device shown in FIG. 7 will be described with reference to FIGS. 9A and 9B.

First, as shown in FIG. 9A, after forming a photoresist pattern 12 on a silicon substrate 1 whose surface is covered with a protective oxide film 50, arsenic ions are implanted into the silicon substrate 1. The width (size measured along the channel length direction) of the photoresist pattern 12 is set to 0.3 to 0.4 μm. In this embodiment, the arsenic ion implantation acceleration energy is 30 to 60 keV, and the dose is 5 × 10 ¹³ to 5 × 10 ¹⁴ cm ⁻² . By this ion implantation, the low concentration impurity diffusion layer 6 is formed in a region of the surface of the semiconductor region which is not covered with the photoresist pattern 12.
a ′ and 6b ′ are formed.

After removing the photoresist pattern 12 and the protective oxide film 50, as shown in FIG. 9B, a laminated gate composed of the tunnel insulating film 2, the floating gate electrode 3, the capacitor insulating film 4, and the control gate electrode 5 is formed. Form the structure.
This stacked gate structure includes a step of forming a tunnel insulating film 2 by a thermal oxidation method, a step of depositing a first polycrystalline silicon film serving as a floating gate electrode 3 on the tunnel insulating film 2 by a chemical vapor deposition method, Forming a capacitive insulating film 4 on the first polycrystalline silicon film, depositing a second polycrystalline silicon film to be the control gate electrode 5 on the capacitive insulating film 4 by chemical vapor deposition, and These multilayer films are formed by a series of manufacturing process steps including a step of patterning using a known lithography and etching technique. In the present embodiment, the width (the size measured along the channel length direction) of the stacked gate structure is set to 0.5 to 0.6 μm.

In the lithography step for patterning the stacked gate structure, the alignment of the stacked gate structure with the low-concentration impurity diffusion layers 6a 'and 6b' is performed by aligning the floating gate electrode 3 with one of the low-concentration impurity diffusion layers 6b '. It is executed so as to overlap with the division. Floating gate electrode 3
In this embodiment, the size (overlap length) of the overlapping portion between the low concentration impurity diffusion layer 6b 'and the low concentration impurity diffusion layer 6b' is about 100 to 150 nm.

Next, arsenic ions are implanted using the patterned laminated gate structure as a mask. The arsenic ion implantation acceleration energy is 30 to 60 keV, and the dose is 5 × 10 ¹⁴ to 5 × 10 ¹⁵ cm ⁻² . By this ion implantation, the high-concentration impurity diffusion layer 11a is formed in a region of the semiconductor surface other than the region where the stacked gate structure is provided.
And 11b are formed. High concentration impurity diffusion layer 11a
9 and 11b are diffused in the horizontal direction through a subsequent heat treatment process even if they are not overlapped by the floating gate electrode 3 immediately after the ion implantation.
As shown in FIG. 2B, a part of the high-concentration impurity diffusion layers 11 a and 11 b is overlapped by the floating gate electrode 3. Finally, the high-concentration impurity diffusion layers 11a and 11b function as a high-concentration source region and a high-concentration drain region, respectively.

As described above, low concentration source region 6a and low concentration drain region 6b are formed by impurity ions implanted from the surface of the semiconductor substrate. These impurity ions thermally diffuse during a plurality of high-temperature process steps performed after the implantation. Therefore, the low-concentration drain region 6b in the finally completed nonvolatile semiconductor memory device is
It is thicker than immediately after the implantation, and its ends slightly expand toward the center of the channel region. However, even if such impurity diffusion occurs, a uniform region where the impurity concentration hardly changes along the channel length direction exists in the overlapping portion of the low-concentration drain region 6b covered by the floating gate electrode 3. .

(Fourth Embodiment) Hereinafter, a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention will be described with reference to FIG. The storage device of the present embodiment is also an n-channel MOS flash EEPROM.

As shown in FIG. 10, the nonvolatile semiconductor memory device of the present embodiment is formed in a p-type semiconductor region of a single crystal silicon substrate 1 including a p-type semiconductor region. FIG. 10 shows only a single memory cell,
In reality, many memory cells are integrated on the same substrate.

The device of this embodiment has almost the same configuration as that of the device of FIG. 6 except for the configuration of the impurity diffusion layer formed in the semiconductor region. Therefore, the description of the structure common to both devices will be omitted. The differences will be described in detail.

The features of the present embodiment are as follows: (1) The floating gate electrode 3 overlaps a part of the drain region, and the impurity concentration in the overlapping part is horizontal along the channel length direction. (2) a first impurity diffusion layer 6b having a relatively low impurity concentration in the drain region and a second impurity diffusion layer 11b having a relatively high impurity concentration in the drain region. And a third impurity diffusion layer 8b provided between the first and second impurity diffusion layers. Note that, similarly to the configuration of the drain region, the configuration of the source region includes a first impurity diffusion layer 6a having a relatively low impurity concentration, a second impurity diffusion layer 11a having a relatively high impurity concentration, and first and second impurity diffusion layers. And a third impurity diffusion layer 8a provided between the two impurity diffusion layers.

Most of the overlapping portion of the drain region is formed of the first impurity diffusion layer 6b having an impurity concentration of 1 × 10 ¹⁸ to 1 × 10 ¹⁹ cm ⁻³ , and is formed immediately below the sidewall spacer 9b. Has an impurity concentration of 2 × 10 ^18
3 × 10 ¹⁹ cm ⁻³ of the third impurity diffusion layer 8b is located. As can be seen from FIG. 10, third impurity diffusion layers 8a and 8b are partially covered by floating gate electrode 3. The other portion of the drain region has a second impurity diffusion layer 1 having an impurity concentration of 1 × 10 ²⁰ cm ⁻³ or more.
1b.

In this embodiment, the size (L _OVR ) of the overlap portion measured along the channel length direction is 1
The size (L _UNI ) measured along the channel length direction of the uniform region is about 100 nm. The overlap length L _OVR is larger than the thickness of the overlap portion (= the junction depth of that portion X _j = about 50 nm).

The storage device of this embodiment operates in the same manner as the device of the second embodiment, and exhibits the same effects as those of the device of the second embodiment. In addition to this effect, according to the present embodiment, the n-type impurity concentration in the region where electrons are extracted is higher than in the device of FIG.

Hereinafter, a method of manufacturing the storage device according to the present embodiment will be described with reference to FIGS. 16 (a) to 16 (c).

First, as shown in FIG. 16A, after forming a photoresist pattern 12 on a silicon substrate 1 whose surface is covered with a protective oxide film 50, arsenic ions are implanted into the silicon substrate 1. The width (the size measured along the channel length direction) of the photoresist pattern 12 is 0.3.
To 0.4 μm. Also in this embodiment, the arsenic ion implantation acceleration energy is 30 to 60 keV, and the dose is 1 × 10 ¹³ to 1 × 10 ¹⁴ cm ⁻² . By this ion implantation, low-concentration impurity diffusion layers 6a 'and 6b' are formed in a region of the surface of the silicon substrate 1 which is not covered with the photoresist pattern 12.

After removing the photoresist pattern 12 and the protective oxide film 50, as shown in FIG. 16B, a laminated gate comprising the tunnel insulating film 2, the floating gate electrode 3, the capacitor insulating film 4, and the control gate electrode 5 is formed. Form the structure. This stacked gate structure includes a step of forming a tunnel insulating film 2 by a thermal oxidation method, and a first step of forming a floating gate electrode 3.
Depositing a polycrystalline silicon film on the tunnel insulating film 2 by chemical vapor deposition, forming a capacitive insulating film 4 on the first polycrystalline silicon film, and forming a second control gate electrode 5 It is formed by a series of manufacturing process steps including a step of depositing a polycrystalline silicon film on the capacitive insulating film 4 by a chemical vapor deposition method, and a step of patterning these multilayer films using known lithography and etching techniques. You. In the present embodiment, the width of the stacked gate structure (the size measured along the channel length direction) is 0.5.
To 0.6 μm.

In the lithography process for patterning the stacked gate structure, the degree of overlap between the floating gate electrode 3 and the low-concentration impurity diffusion layers 6a 'and 6b' is symmetrical with respect to a plane perpendicular to the center of the channel region. The alignment between the stacked gate structure and the low-concentration impurity diffusion layers 6a 'and 6b' is performed. The size of the overlapping portion (overlap length) between the floating gate electrode 3 and the low-concentration impurity diffusion layer 6b 'is:
In the case of the present embodiment, it is about 100 to 150 nm.

Next, as shown in FIG. 16B, arsenic ions are implanted using the patterned stacked gate structure as a mask. Arsenic ion implantation acceleration energy is 30
To 60 keV, and the dose is 5 × 10 ¹³ to 5 × 10 ¹⁴
cm ^-2 . By this ion implantation, impurity diffusion layers 8a 'and 8b' are formed in regions other than the region where the stacked gate structure is provided on the semiconductor surface. In the low-concentration impurity diffusion layers 6a 'and 6b', arsenic ions are not additionally implanted into regions covered with the stacked gate structure, but arsenic ion doping at an intermediate level is performed on the other regions. . Therefore, a part of the low-concentration impurity diffusion layers 6a 'and 6b' functions as the low-concentration source region 6a and the low-concentration drain region 6b.

Next, as shown in FIG. 16 (c), insulating sidewall spacers 9 are formed on the side walls of the laminated gate structure.
After forming a and 9b, arsenic ions are implanted. The arsenic ion implantation acceleration energy is 30 to 60 keV,
The dose is 5 × 10 ¹⁴ to 5 × 10 ¹⁵ cm ⁻² . By this ion implantation, the high-concentration impurity diffusion layers 11
a and 11b are formed. Arsenic ions are not additionally implanted in the regions of the impurity diffusion layers 8a 'and 8b' that are covered with the stacked gate structure or the sidewall spacers, but high-level arsenic ion doping is performed in other regions. Done. Therefore, some of the impurity diffusion layers 8a 'and 8b' function as the medium-concentration source region 8a and the medium-concentration drain region 8b, while the other portions have the high-concentration impurity diffusion layers 11a and 11b.
Changes to High concentration impurity diffusion layers 11a and 11b
Function as high-concentration source regions and high-concentration drain regions, respectively.

The low-concentration source region 6a and the low-concentration drain region 6b are formed by the impurity ions implanted from the surface of the semiconductor substrate as described above. These impurity ions thermally diffuse during a plurality of high-temperature process steps performed after the implantation. Therefore, the low-concentration drain region 6b in the finally completed nonvolatile semiconductor memory device is
It is thicker than immediately after the implantation, and its ends slightly expand toward the center of the channel region. Similarly, the impurity in the medium concentration drain region 8b also diffuses, so that its edge slightly spreads toward the center of the channel region, and enters the lower portion of the floating gate electrode 3. This also occurs in the source region. However, even if such impurity diffusion occurs, a uniform region where the impurity concentration hardly changes along the channel length direction exists in the overlapping portion of the low-concentration drain region 6b covered by the floating gate electrode 3. . As a result, the high concentration drain region 11
b while maintaining a relatively high potential level supplied through the wiring to the channel region and the lightly doped drain region 6.
It can be transmitted to the joint with b. As a result, a strong horizontal electric field peak can be formed at a position near the center of the semiconductor surface area covered by the floating gate electrode 3.

After the formation of the source / drain regions is completed, well-known manufacturing steps such as formation of an interlayer insulating film and formation of a multilayer wiring are performed to manufacture a final nonvolatile semiconductor memory device.

(Fifth Embodiment) Hereinafter, a nonvolatile semiconductor memory device according to a fifth embodiment of the present invention will be described with reference to FIG. The storage device of the present embodiment is also an n-channel MOS flash EEPROM.

As shown in FIG. 11, the nonvolatile semiconductor memory device of this embodiment is formed in a p-type semiconductor region of a single crystal silicon substrate 1 including a p-type semiconductor region. FIG. 11 shows only a single memory cell,
In reality, many memory cells are integrated on the same substrate.

The device of the present embodiment has almost the same configuration as the device of FIG. 10 except for the configuration of the impurity diffusion layer formed in the semiconductor region. Therefore, description of the structure common to both devices will be omitted. The differences will be described in detail.

The features of this embodiment are as follows: (1) The floating gate electrode 3 overlaps with a part of the drain region, and the impurity concentration in the overlapped portion extends along the channel length direction. (2) a first impurity diffusion layer having a relatively low impurity concentration in the drain region, a second impurity diffusion layer having a relatively high impurity concentration, A third impurity diffusion layer provided between the first and second impurity diffusion layers; and (3) a channel region formed relatively at a position in contact with an overlap portion of the drain region. That is, it includes a high concentration p-type impurity diffusion layer 7b.
The impurity concentration of the p-type impurity diffusion layer 7b of this embodiment is 2 ×
It is 10 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ .

The storage device of this embodiment operates in the same manner as the device of the fourth embodiment, and exhibits the same effects as those of the device of the fourth embodiment. In addition to this effect, according to the present embodiment, the presence of the p-type semiconductor region 7b increases the electric field intensity formed at the drain end as compared with the case of the above-described embodiment. The injection efficiency can be further improved.

To manufacture the device of the present embodiment, in the manufacturing method of the fourth embodiment, after masking the surface of the silicon substrate 1 with the photoresist pattern 12 shown in FIG. Boron (B) for 1
It is only necessary to add a step of implanting p-type impurity ions such as these to form the p-type impurity diffusion layers 7a and 7b. This p-type impurity ion implantation step may be performed before or after the n-type impurity ion implantation step for the low concentration impurity diffusion layers 6a and 6b. The conditions for implanting p-type impurity ions are, for example, that the acceleration energy is 20 to 4
0 keV, implantation dose 5 × 10 ¹² to 5 × 10 ¹³ c
cm ^-2 .

(Sixth Embodiment) Hereinafter, a nonvolatile semiconductor memory device according to a fifth embodiment of the present invention will be described with reference to FIG. The storage device of the present embodiment is also an n-channel MOS flash EEPROM.

As shown in FIG. 12, the nonvolatile semiconductor memory device of the present embodiment is formed in a p-type semiconductor region of a single crystal silicon substrate 1 including a p-type semiconductor region. Although only a single memory cell is shown in FIG. 9, many memory cells are actually integrated on the same substrate.

The device of this embodiment has almost the same configuration as the device of FIG. 11 except for the configuration of the impurity diffusion layer formed in the semiconductor region. Therefore, the description of the structure common to both devices will be omitted. The differences will be described in detail.

The features of this embodiment are as follows: (1) The floating gate electrode 3 overlaps with a part of the drain region, and the impurity concentration in this overlapping part is laterally along the channel length direction. (2) The drain region has a first impurity diffusion layer 6b having a relatively low impurity concentration and a second impurity diffusion layer 11b having a relatively high impurity concentration. , First and second
Third impurity diffusion layer 8b provided between impurity diffusion layers
(3) that the channel region includes a relatively high-concentration p-type impurity diffusion layer 7b formed at a position in contact with the overlap portion of the drain region; and (4) The present invention includes an n ⁻ -type low-concentration impurity diffusion layer 12b provided between the second impurity diffusion layer 11b and the p-type semiconductor region.

This n ⁻ -type low-concentration impurity diffusion layer 12b is
It has an impurity concentration lower than the impurity concentration of third impurity diffusion layer 8b. Note that the p-type impurity diffusion layer 7b of the present embodiment
Is 2 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ in the substrate surface region, and the impurity concentration of the n ⁻ -type low concentration impurity diffusion layer 12b is 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ^{1. 9}
cm ^-3 .

The storage device of this embodiment operates in the same manner as the device of the fifth embodiment, and exhibits the same effects as those of the device of the fifth embodiment. In addition to this effect, according to the present embodiment, the presence of the n ⁻ -type low-concentration impurity diffusion layer 12b improves the drain withstand voltage and reduces the parasitic capacitance of the junction. Further, since the withstand voltage of the drain junction is large, a leakage current at the time of data erasure is reduced, and power consumption is reduced. The reduction of the leak current suppresses the injection of hot electrons and hot holes into the tunnel insulating film 2, and further improves the reliability.

Hereinafter, a method of manufacturing the storage device according to the present embodiment will be described with reference to FIGS.

First, as shown in FIG. 17A, after a photoresist pattern 12 is formed on a silicon substrate 1 whose surface is covered with a protective oxide film 50, arsenic ions and boron are implanted into the silicon substrate 1. I do. The width (size measured along the channel length direction) of the photoresist pattern 12 is set to 0.3 to 0.4 μm. In this embodiment, the arsenic ion implantation acceleration energy is 30 to 60 k.
eV, dose amount is 1 × 10 ¹³ to 1 × 10 ¹⁴ cm ^−2, and boron ion implantation acceleration energy is 20 to 40.
The keV and the dose are 5 × 10 ¹² to 5 × 10 ¹³ cm ⁻² . By this ion implantation, low-concentration impurity diffusion layers 6a 'and 6b' and p-type impurity diffusion layers 7a 'and 7b' are formed in a region of the surface of the silicon substrate 1 which is not covered with the photoresist pattern 12. The ion implantation conditions are such that the n-type impurity concentration on the surface of the silicon substrate 1 is higher than the p-type impurity concentration, and the junction depth of the low-concentration impurity diffusion layers 6a ′ and 6b ′ measured from the substrate surface is In this case, the junction depth of the p-type impurity diffusion layers 7a 'and 7b' measured from the substrate surface is made shallower.

After removing the photoresist pattern 12 and the protective oxide film 50, as shown in FIG. 17B, a laminated gate composed of the tunnel insulating film 2, the floating gate electrode 3, the capacitor insulating film 4, and the control gate electrode 5 is formed. Form the structure. This stacked gate structure includes a step of forming a tunnel insulating film 2 by a thermal oxidation method, and a first step of forming a floating gate electrode 3.
Depositing a polycrystalline silicon film on the tunnel insulating film 2 by chemical vapor deposition, forming a capacitive insulating film 4 on the first polycrystalline silicon film, and forming a second control gate electrode 5 It is formed by a series of manufacturing process steps including a step of depositing a polycrystalline silicon film on the capacitive insulating film 4 by a chemical vapor deposition method, and a step of patterning these multilayer films using known lithography and etching techniques. You. In the present embodiment, the width of the stacked gate structure (the size measured along the channel length direction) is 0.5.
To 0.6 μm.

In the lithography process for patterning the stacked gate structure, the degree of overlap between the floating gate electrode 3 and the low-concentration impurity diffusion layers 6a 'and 6b' is symmetrical with respect to a plane perpendicular to the center of the channel region. The alignment between the stacked gate structure and the low-concentration impurity diffusion layers 6a 'and 6b' is performed. The size of the overlapping portion (overlap length) between the floating gate electrode 3 and the low-concentration impurity diffusion layer 6b 'is:
In the case of the present embodiment, the thickness is 0.05 to 0.15 μm.

Next, as shown in FIG. 17B, arsenic ions are implanted using the patterned laminated gate structure as a mask. Arsenic ion implantation acceleration energy is 30
To 60 keV, and the dose is 5 × 10 ¹³ to 5 × 10 ¹⁴
cm ^-2 . By this ion implantation, n-type impurity diffusion layers 8a 'and 8b' are formed in regions other than the region where the stacked gate structure is provided on the semiconductor surface. In the low-concentration impurity diffusion layers 6a 'and 6b', arsenic ions are not additionally implanted into regions covered with the stacked gate structure, but arsenic ion doping at an intermediate level is performed on the other regions. . Therefore, a part of the low-concentration impurity diffusion layers 6a 'and 6b' functions as the low-concentration source region 6a and the low-concentration drain region 6b. Further, p-type impurity diffusion layers 7a 'and 7
The portion of b ′ covered by the floating gate electrode 3 remains as the p-type impurity diffusion layers 7a and 7b.

Next, as shown in FIG. 17 (c), insulating sidewall spacers 9 are formed on the side walls of the laminated gate structure.
After forming a and 9b, arsenic ions and phosphorus (P) ions are implanted. The arsenic ion implantation acceleration energy is 30 to 60 keV, and the dose is 5 × 10 ¹⁴ to 5 × 10 ¹⁵ cm ⁻² . The implantation acceleration energy of phosphorus ions is 40 to 60 keV, and the dose is 5 × 10 ¹² to 5 × 10 ¹³ cm ⁻² . By arsenic ion implantation, high-concentration impurity diffusion layers 11a and 11b are formed in regions of the semiconductor surface other than the region where the stacked gate structure and the sidewall spacers 9a and 9b are provided. Among the impurity diffusion layers 8a 'and 8b', arsenic ions are not additionally implanted in the regions covered with the stacked gate structure or the sidewall spacers 9a and 9b, but high-level arsenic ions are implanted in other regions. Ion doping is performed. Therefore, some of the impurity diffusion layers 8a 'and 8b' function as the medium-concentration source region 8a and the medium-concentration drain region 8b, but the other portions change to the high-concentration impurity diffusion layers 11a and 11b. . The high concentration impurity diffusion layers 11a and 11b function as a high concentration source region and a high concentration drain region, respectively. Further, the n ⁻ -type low-concentration impurity diffusion layer 12 is formed by the phosphorus implanted by the ion implantation.
a and 12b are formed. Since the impurity diffusion coefficient of phosphorus is larger than that of arsenic, the n ^- type low-concentration impurity diffusion layer 12
a and 12b also extend below the sidewalls 9a and 9b.

(Seventh Embodiment) Hereinafter, a nonvolatile semiconductor memory device according to a seventh embodiment of the present invention will be described with reference to FIG. The storage device of the present embodiment is also an n-channel MOS flash EEPROM.

As shown in FIG. 13, the nonvolatile semiconductor memory device of the present embodiment is formed in a p-type semiconductor region of a single crystal silicon substrate including a p-type semiconductor region. FIG.
3, only a single memory cell is described, but in reality, many memory cells are integrated on the same substrate.

The device of this embodiment has almost the same configuration as the device of FIG. 12 except for the asymmetric configuration of the impurity diffusion layer formed in the semiconductor region. Therefore, the description of the structure common to both devices will be omitted. The differences will be described in detail.

The difference between the device of this embodiment and the device of FIG. 12 is that while the structure of the drain region of the device has the same structure as that of the device of FIG. It has a structure in which the diffusion layer 7a is removed.

In the device of this embodiment, the write operation can be performed on the drain side, and the erase operation can be performed on the source side. For this reason, the intensity of the electric field to be formed can be further increased, whereby the injection efficiency can be further improved.

In the erasing operation, control gate electrode 5
A voltage of -6 to -8 V, a voltage of 5 to 6 V to the source region 11a, and a voltage of 0 V to the drain region 11b and the substrate are applied, and electrons are extracted from the floating gate electrode 3 to the source region by a tunnel current flowing through the tunnel insulating film 2. in this case,
Under the above-described voltage application condition, electron tunneling occurs in a portion having the strongest electric field formed in the tunnel insulating film 2.
Since the extraction of electrons is performed in the source region, the location is different from that of writing (injection of electrons), and the tunnel insulating film 2 is less deteriorated and excellent in reliability.

In order to provide the p-type impurity diffusion layer 7b only on the drain side, the source side may be covered with a resist pattern before the impurity ion implantation step for forming the p-type impurity diffusion layer 7b. . Except for this point, the device of FIG. 13 can be manufactured by the same manufacturing method as described with reference to FIGS. 17A to 17C.

(Eighth Embodiment) Hereinafter, an eighth embodiment of the nonvolatile semiconductor memory device according to the present invention will be described with reference to FIG. The storage device of the present embodiment is also an n-channel MOS flash EEPROM.

As shown in FIG. 14, the nonvolatile semiconductor memory device of this embodiment is formed in a p-type semiconductor region of a single crystal silicon substrate including a p-type semiconductor region. FIG.
4, only a single memory cell is described, but in reality, many memory cells are integrated on the same substrate.

The difference between the device of this embodiment and the device of FIG. 13 is that the structure of the drain region of this device has the same structure as that of the device of FIG. The point is that the diffusion layer 6a has a structure further removed.

Also in this embodiment, extraction of electrons for erasing is performed on the source side. For this reason, the voltage applied to the drain region is as low as, for example, about 5 V, and the impurity concentrations of the n ⁻ -type low-concentration impurity diffusion layer 6b and the p-type impurity diffusion layer 7b are respectively reduced by the fifth and sixth embodiments. Even if the impurity concentration is higher than the above, the decrease in the withstand voltage on the drain side hardly causes a problem. For this reason, in the present embodiment, the low concentration impurity diffusion layer 6b and the p-type impurity diffusion layer 7
b, the impurity concentration is 1 × 10 ¹⁹ to 1 × 10
²⁰ cm ^-3 and 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ^-3 are set. Since the impurity concentration of the low concentration impurity diffusion layer 6b is high, the same drain voltage is applied to the high concentration drain region 11b.
, The intensity of the electric field formed in the channel region is increased, and the injection efficiency is improved.

In the erase operation, the control gate electrode 5
A voltage of 6 to -8 V, a voltage of 5 to 6 V to the source region 11a, and a voltage of 0 V to the drain region 11b and the silicon substrate 1 are used to extract electrons from the floating gate electrode 3 to the source region by a tunnel current flowing through the tunnel oxide film 2. Also in this case, since the extraction of electrons is performed on the source side, tunneling occurs in a place different from the writing (injection of electrons), and the tunnel insulating film 2 is less deteriorated and excellent in reliability. In addition, the presence of the n ⁻ -type low-concentration impurity diffusion layer 12a improves the breakdown voltage of the source junction and reduces the leakage current during the erasing operation. Therefore, power consumption can be reduced. Since the reduction of the leak current suppresses the injection of hot electrons and hot holes into the tunnel insulating film 2, the reliability is improved.

Hereinafter, a method of manufacturing the storage device according to the present embodiment will be described with reference to FIGS.

First, as shown in FIG.
Photolithography is performed on the silicon substrate 1 covered with the protective oxide film 50.
After forming the dist pattern 12, the silicon substrate 1
Inject arsenic ions and boron. Photoresist resist
Turn 12 width (size measured along the channel length direction)
) Is a portion of the active region that becomes a channel region, and
It is formed so as to cover a portion to be a source region. Arsenic
On implantation acceleration energy is 30 to 60 keV,
Size is 1 × 10¹³From 1 × 10¹⁴cm^-2And Boron Yi
On implantation acceleration energy is 20 to 40 keV,
Size is 1 × 10 ¹³From 1 × 10¹⁴cm^-2And This
The photoresist on the surface of the silicon substrate 1 is
Low-concentration impurities in the region not covered with the strike pattern 12
Diffusion layer 6b 'and p-type impurity diffusion layer 7b' are formed.
You.

After removing the photoresist pattern 12 and the protective oxide film 50, as shown in FIG. 18B, a laminated gate composed of the tunnel insulating film 2, the floating gate electrode 3, the capacitor insulating film 4, and the control gate electrode 5 is formed. Form the structure. This stacked gate structure includes a step of forming a tunnel insulating film 2 by a thermal oxidation method, and a first step of forming a floating gate electrode 3.
Depositing a polycrystalline silicon film on the tunnel insulating film 2 by chemical vapor deposition, forming a capacitive insulating film 4 on the first polycrystalline silicon film, and forming a second control gate electrode 5 It is formed by a series of manufacturing process steps including a step of depositing a polycrystalline silicon film on the capacitive insulating film 4 by a chemical vapor deposition method, and a step of patterning these multilayer films using known lithography and etching techniques. You. In the present embodiment, the width of the stacked gate structure (the size measured along the channel length direction) is 0.5.
To 0.6 μm.

In the lithography process for patterning the stacked gate structure, the degree of overlap between the floating gate electrode 3 and the low-concentration impurity diffusion layer 6b ′ is 5
The alignment between the stacked gate structure and the low-concentration impurity diffusion layer 6b 'is performed so that the thickness becomes about 0 to 150 nm.

Next, as shown in FIG. 18C, arsenic ions are implanted using the patterned gate structure as a mask. Arsenic ion implantation acceleration energy is 30
To 60 keV and a dose of 1 × 10 ¹⁴ to 5 × 10 ¹⁴
cm ^-2 . By this ion implantation, impurity diffusion layers 8a 'and 8b' are formed in regions other than the region where the stacked gate structure is provided on the semiconductor surface. In the low concentration impurity diffusion layer 6b ', arsenic ions are not additionally implanted into a region covered with the stacked gate structure, but arsenic ion doping at an intermediate level is performed on other regions. For this reason, the low concentration impurity diffusion layer 6b '
A portion functions as the low-concentration drain region 6b. Further, the portion of the p-type impurity diffusion layer 7b 'covered by the floating gate electrode 3 remains as the p-type impurity diffusion layer 7b.

Next, as shown in FIG. 18C, an insulating sidewall spacer 9 is formed on the side wall of the stacked gate structure.
After forming a and 9b, arsenic ions and phosphorus (P) ions are implanted. The arsenic ion implantation acceleration energy is 30 to 60 keV, and the dose is 5 × 10 ¹⁴ to 5 × 10 ¹⁵ cm ⁻² . The implantation acceleration energy of phosphorus ions is 40 to 60 keV, and the dose is 1 × 10 ¹² to 1 × 10 ¹⁴ cm ⁻² . By implanting arsenic ions, high-concentration impurity diffusion layers 11a and 11b are formed in a region of the semiconductor surface other than the region where the stacked gate structure and the sidewall spacers 9a and 9b are provided.
Is formed. Of the impurity diffusion layers 8a 'and 8b', the stacked gate structure or the side wall spacer 9a
And 9b are not additionally implanted with arsenic ions, while the other regions are subjected to a high level of arsenic ion doping. Therefore, part of the impurity diffusion layers 8a 'and 8b'
And functions as a medium-concentration drain region 8b, but the other portions have high-concentration impurity diffusion layers 11a and 11a.
changes to b. High concentration impurity diffusion layers 11a and 11b
Function as high-concentration source regions and high-concentration drain regions, respectively. Further, the n ⁻ -type low-concentration impurity diffusion layers 12 a and 12
b is formed.

As described above, in the third to eighth embodiments, the entire low-concentration impurity diffusion layer 6b is formed at a position covered by the floating gate electrode 3, and
A high-concentration impurity diffusion layer for transmitting a drain potential to the low-concentration impurity diffusion layer 6b is formed at a position connected to the drain-side end of the low-concentration impurity diffusion layer 6b. Therefore, when a high potential is applied to the floating gate electrode 3 at the time of data writing, an inversion layer is formed immediately below the floating gate electrode 3 according to the potential of the floating gate electrode 3, and as a result, as shown in FIG. Such a surface potential distribution is formed.

FIGS. 19A and 19B are diagrams schematically showing where electron tunneling occurs during data writing and data erasing in the nonvolatile semiconductor memory device of the present invention. The potentials applied to the floating gate electrode 3 and the like during data writing and erasing are, for example, as shown in Table 1 below (unit: volt). In writing data, a potential of -2 to -3 volts may be applied to the substrate.

[0158]

[Table 1] At the time of data writing, electrons are injected into the floating gate electrode 3 from the channel-side end of the first impurity diffusion layer 6b mainly through the path indicated by the arrow A. On the other hand, at the time of data erasing, in the structure of FIG. 19A, electrons of the floating gate electrode 3 mainly pass through the path of the arrow B and pass through the second impurity diffusion layer 11.
It is pulled out by b. In the structure of FIG. 19B, at the time of data erasing, electrons of the floating gate electrode 3 are mainly extracted to the third impurity diffusion layer 8b through the path indicated by the arrow B.

As described above, according to the nonvolatile semiconductor memory device of the present invention, the position of the electron injection during the writing operation is different from the position of the tunneling of the electrons during the erasing operation. Excellent in reliability. Further, since data writing and erasing can be performed on the drain side, a circuit configuration for connecting a bit line to the source side can be realized, and read disturb is eliminated. Note that the erasing operation can also be executed by extracting the electrons accumulated in the floating gate electrode 3 to the source region 8a or 11a.

In each of the above embodiments, the control gate electrode 5 is stacked above the floating gate electrode 3 via the capacitance insulating film (second insulating film) 4. However, the nonvolatile semiconductor memory device of the present invention It is not limited to the one having such a stacked gate structure. Even in a nonvolatile semiconductor memory device having a structure in which at least a part of the control gate electrode 5 faces the channel region via an insulating film, the phenomenon described with reference to FIGS. 8A and 8B occurs. The same effect as that of the nonvolatile semiconductor memory device having the type gate structure can be obtained.

[0161]

According to the present invention, the floating gate electrode overlaps with a part of the drain region, and the overlapping portion includes a region where the impurity concentration is constant in the horizontal direction along the channel length direction. The intensity peak position of the horizontal lateral electric field formed in the semiconductor region at the time of writing is shifted inward from the drain-side edge of the floating gate electrode, whereby hot electrons can be efficiently injected into the floating gate electrode. as a result,
The injection efficiency of channel hot electrons is improved, and the writing speed is improved or the writing voltage is reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view of a conventional MOS flash EEPROM.

FIG. 2 is a sectional view of the first embodiment of the nonvolatile semiconductor memory device according to the present invention;

FIG. 3 is a diagram schematically showing a cross-sectional configuration, an impurity concentration, and a horizontal electric field intensity distribution in a drain region of the device according to the first embodiment.

FIG. 4A is a diagram schematically showing a horizontal electric field intensity distribution in a drain region of the device according to the first embodiment;
(B) is a diagram schematically showing a horizontal electric field intensity distribution in a drain region of a conventional device.

FIGS. 5A to 5D are process cross-sectional views for explaining a method of manufacturing the device of FIG. 2;

FIG. 6 is a sectional view of a second embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 7 is a sectional view of a third embodiment of the nonvolatile semiconductor memory device according to the present invention.

8A is a diagram showing the surface potential (potential) of the drain region and its vicinity when data is written, and FIG. 8B is a diagram showing the drain region and its vicinity when the potential of the floating gate electrode is lowered; FIG. 4 is a diagram showing a surface potential (potential) of FIG.

FIGS. 9A and 9B are process cross-sectional views for explaining a method of manufacturing the device of FIG. 7;

FIG. 10 shows a third example of the nonvolatile semiconductor memory device according to the present invention.
It is sectional drawing of embodiment.

FIG. 11 shows a fourth example of the nonvolatile semiconductor memory device according to the present invention.
It is sectional drawing of embodiment.

FIG. 12 shows a fifth embodiment of the nonvolatile semiconductor memory device according to the present invention;
It is sectional drawing of embodiment.

FIG. 13 shows a sixth embodiment of the nonvolatile semiconductor memory device according to the present invention.
It is sectional drawing of embodiment.

FIG. 14 shows a seventh embodiment of the nonvolatile semiconductor memory device according to the present invention.
It is sectional drawing of embodiment.

FIGS. 15A to 15C are process cross-sectional views for explaining a method of manufacturing the device of FIG. 6;

16A to 16C are process cross-sectional views for explaining a method of manufacturing the device of FIG. 7;

17A to 17C are process cross-sectional views illustrating a method of manufacturing the device in FIG. 9;

FIGS. 18A to 18C are process cross-sectional views illustrating a method of manufacturing the device of FIG. 11.

FIGS. 19A and 19B are diagrams schematically showing where electron tunneling occurs during data writing and data erasing in the nonvolatile semiconductor memory device of the present invention. FIGS.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Single crystal semiconductor substrate 2 Tunnel insulating film 3 Floating control gate (FG) 4 Capacitive insulating film 5 Control gate electrode (CG)

──────────────────────────────────────────────────の Continued on the front page (72) Inventor Junichi Kato 1006 Kazuma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Inventor Masaki Ogura 12590, New York, USA, Wappingers Falls, Old Hopewell Road 140, Halo LSI Design and Device Technology Inc. (56) References JP-A-63-99573 (JP, A) JP-A-2-295169 (JP, A) JP-A-6-252414 (JP, A) JP-A-10-74850 (JP, A) JP-A-9-129755 (JP, A) JP-A-2 -128476 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/82 47 H01L 27/115 H01L 29/788 H01L 29/792

Claims (1)

(57) [Claims] A first conductive type semiconductor region; an insulating film formed on the semiconductor region; a gate electrode formed on the insulating film; and a second conductive type formed in the semiconductor region. A non-volatile memory, comprising: a source region of a second conductivity type; a drain region of a second conductivity type formed in the semiconductor region; and a channel region formed in the semiconductor region and located between the source region and the drain region. A step of covering a region to be the channel region in the semiconductor region with a mask before forming the source region and the drain region; Forming a second conductivity type impurity diffusion layer functioning as at least a part of the drain region in an uncovered region; removing the mask; A gate formation step so as to cover both the portion and the channel region of the second conductivity type impurity diffusion layer serving as a part of the in-region forming the gate electrode, after forming the gate electrode, the gate electrode With a mask
Implanting a second conductivity type impurity into the semiconductor region by
Therefore, the impurity concentration of the second conductivity type impurity diffusion layer is
Another impurity diffusion layer of the second conductivity type having a high impurity concentration
Forming the gate electrode in a self-aligned manner, and forming the second impurity diffusion layer of the second conductivity type;
Side walls on the side surfaces of the gate electrode and the second gate electrode.
Forming a spacer, and after forming the gate electrode, at least the gate electrode
Into the semiconductor region with the second conductivity type impurity as a mask.
The source region and the drain
High level doping process to complete the formation of the region
The gate forming step is performed such that the portion of the second conductivity type impurity diffusion layer overlapped by the gate electrode includes a uniform region having a constant impurity concentration in a lateral direction along a channel length direction. Manufacturing method of a nonvolatile semiconductor memory device.