JP3146254B2 - Logic circuit simulation result display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform display device for a simulation result of a logic circuit in ASIC design or the like.

[0002]

2. Description of the Related Art Generally, full custom ICs and semi-casters
Beam IC, and summarizes the ASSP (application-specific standard products) ASIC (Application Specific Integrated
Circuit). Further, a PLD (Programmable Logic Device) may be included. Normally, when developing an ASIC or the like using a logic simulator, using a library provided by each ASIC maker, a simulation is performed in a state in which the delay of the logic circuit is minimum, standard, and maximum, and three types of delay are performed. It is necessary to confirm the operation with the value. Also, at the time of designing, how much delay each signal has, how much delay between the change position in the simulation when the minimum delay is set and the change position in the simulation when the maximum delay is set, It is also usually performed to confirm such information. However, a device or method for automatically checking or visually displaying them has not yet been developed. Therefore, prior to the present application, the present applicant has proposed a method capable of automatically checking waveform consistency (Japanese Patent Application No. 2-3008).
No. 81 specification and drawing "Error detection control method of logic circuit verification device").

[0003]

As described above, in the conventional simulator, each ASIC manufacturer provides three types of minimum delay, standard delay, and maximum delay for each series. By changing those delays, all three simulations can be performed.
However, in these simulators, the difference between the changes caused by the delay difference cannot be viewed as a waveform.
In addition, some manufacturers show a difference in change by a special simulator, but the device is realized by processing performed by the simulator itself. Therefore, it was not possible to use any simulator, and it was one function of some simulators. Also, which ones are N the殆, even if an attempt to output a difference of more changes to the simulator, there is a problem that output would all become peace (undefined). FIG. 3 shows a conventional simulation.
FIG. 3 is a diagram of a delay circuit for performing a translation. this
By passing a signal through a delay circuit,
The minimum delay, the standard delay, and the maximum delay.
Execute the three types of b. A first object of the present invention is to solve these conventional problems and to display a difference in delay easily from a simulation result performed using a normal simulator, and to eliminate manual calculation and complicated work. It is an object of the present invention to provide a logic circuit simulation result display device capable of performing the above. A second object of the present invention is to provide a logic circuit simulation result that does not need to target all signals, reduces processing on a computer, enables high-speed processing, and reduces processing wait time. A display device is provided. A third object of the present invention is to provide a logic circuit which can eliminate the troublesome work of searching for an error part whose phase due to each delay is not normal on a waveform and immediately determine where the error part is. A simulation result display device is provided. A fourth object of the present invention is to provide a logic circuit simulation result display device which can treat a short pulse having a phase shift that causes a waveform error separately from the waveform error and can be completely identified by the human eye. To provide. A fifth object of the present invention is to provide a logic circuit simulation result display device capable of automatically searching for an error portion, eliminating a manual search operation, and easily checking the error portion. is there. A sixth object of the present invention is to provide a logic circuit simulation capable of easily displaying each delay waveform of an error portion by displaying detailed information of the error portion, thereby eliminating a cumbersome manual data collection operation. A result display device is provided. A seventh object of the present invention is to provide a logic circuit capable of automatically summing up what kind of delay is caused by the state of change at each change point, thereby eliminating complicated manual measurement and counting work. A simulation result display device is provided. An eighth object of the present invention is to make it possible to set a mask after checking an error portion, display it in a different color, and manage errors such as how far the check has been made, thereby reducing complicated management work. An object of the present invention is to provide a logic circuit simulation result display device which can be eliminated.

[0004]

Means for Solving the Problems] To achieve the above object, the logic circuit simulation result display device of the present invention, in order to simulate the logic circuit used in the design of such (b) ASIC, and inputs on a computer Logic circuit input means, test pattern input means for creating an input pattern required for simulating a logic circuit, logic simulation means for executing a simulation using the logic circuit and the test pattern, minimum, standard, and maximum A logic simulation result holding means for each delay for holding the simulation results of the three delays, a waveform consistency check means for checking whether the phases of the waveforms in the three delays match, and a waveform display Means. Further, (b) as waveform display means, there are provided superimposition display means for superimposing and displaying waveforms with three kinds of delays, and superimposition display signal designation means for designating a necessary signal among all signals. The waveform is superimposed and displayed on some of the signals specified by the superimposed display signal specifying means. Also, (c) the waveform display means may cause an error in the waveform consistency check,
It is characterized in that it is provided with a color display means for displaying various errors and the like for displaying each error in a background color or a signal line color for a portion where a short pulse error occurs. (D) If a waveform error is detected as a result of the check by the waveform consistency check means, a short pulse detection means for detecting a short pulse error in which the phase is shifted because the stability width is shorter than the waveform error. And a color display means for displaying various errors in a color different from the waveform error so that the short pulse can be handled separately from the waveform error. (E) As a waveform display means, a waveform error search and display means for moving to and displaying a waveform screen of the previous and next error occurrence positions by searching for a waveform error in time order from a waveform group on a simulation result superimposed error display. It is characterized by having. (F) As the waveform display means, there is provided a delay detailed waveform display means for displaying an error portion of the waveform by indicating an error portion of the waveform to display detailed waveform information for each delay of the waveform. Furthermore, (g)
Equipped with a delay width measuring means for summing up the minimum, average and maximum delay widths such as rise and fall of each change point in each signal held in the logic simulation result holding means for each delay. It is characterized by doing. Further, (h) when the superimposed waveform is displayed by the waveform display means, when it is confirmed that there is no problem with the error at each position, the error partial mask setting means for masking the error; A color display means for changing various colors when set is provided.

[0005]

According to the present invention, the delay difference is displayed in an easy-to-see manner based on the result of a simulation performed using a normal simulator instead of a special simulator for simultaneously simulating the minimum (MNI) and the maximum (MAX). Then, the phase of the waveform is checked based on the simulation result of the minimum delay, the standard delay, and the maximum delay, and the delay of the change point position in each delay is displayed on the waveform in the normal phase portion by the check.
Also, by designating the signals to be superimposed on the waveform, it is not necessary to target all the signals, the processing on the computer can be reduced, and the processing can be sped up, so that the response can be improved. . Also, for the error part where the phase due to each delay is not normal,
By changing the background color, the color of the signal line, and the like, it is possible to immediately determine where the error portion is. Further, on the functionality of detecting short pulses, to detect a short pulse phase shifts becomes a waveform error by treating separately from the waveform error, as a short pulse does not enter into the waveform error , Reducing the overall error and displaying it in a different color to make it easier to identify by human eyes. In addition, an error portion can be searched, so that an error search operation is eliminated, and the error portion can be easily checked. In addition, by having a function of displaying detailed information of an error portion, it is possible to easily see the waveform of each delay at the error portion, and to eliminate a complicated data collection operation by hand. In addition, a totaling operation is eliminated by automatically totalizing what kind of delay difference is produced depending on the state of change of each change point for each signal. After checking the error part,
By setting a mask and displaying the image in different colors, errors are managed so that the check is performed to the extent that the check has been performed or the check is not performed repeatedly.

[0006]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 2 is an overall configuration diagram of the logic simulation result display device of the present invention. In FIG. 2, 101 is a data processing unit, 102 is a mouse, 103 is a keyboard,
104 is a memory and 105 is a screen display unit. In the present invention, by storing various function modules in the data processing unit 101, manual calculations and complicated operations are eliminated, and the waiting time for processing is reduced. Also, by changing the color of the error portion, even if the waveform display is compressed and displayed with a large time scale, it is possible to easily identify which portion of the entire waveform has an error. I do. Furthermore, complicated identification work, data collection work, measurement / aggregation work, and management work can be eliminated.

FIG. 1 is a functional block diagram of the data processing unit in FIG. As shown in FIG. 1, a data processing unit 101 of the present invention comprises a logic circuit input means 201, a test pattern input means 202, a logic simulation / hold / consistency check means 200, and a short pulse error detection means. 206, a width measuring means 207 for the change in delay difference, a waveform display means 208, and a detailed delay waveform display means 213 for each error portion. The logic circuit input means 201 is a means (program module) for inputting on a computer to simulate a circuit to be designed such as an ASIC, and operates in conjunction with the mouse 102. The test pattern input means 202 is for creating an input pattern required for simulating the circuit (program module), and the logic simulation means 203 is provided for the input logic circuit. And an actual simulation using the test pattern. In the logic simulation means 203, each ASIC manufacturer provides a library for each ASIC series as an ASIC design tool, and by using the library, a simulation in which the delay of the element is considered. -Is available for Generally, three types of delays, a minimum delay, a standard delay, and a maximum delay, are prepared from various conditions.

The logic simulation result holding means 204 for each delay holds the simulation results of the three types of delays, respectively. The waveform consistency checking means 205 stores the waveforms of the three types of delays. This is to check the consistency of the waveforms between the delays, such as whether or not the phases of the waveforms coincide with each other. The short pulse error detecting means 206 separates the short pulse errors out of the waveform errors whose phase is shifted due to a short stable width so that they can be handled separately from the waveform errors. The change width measuring means 207 calculates the width of the change delay of the change point of the waveform having a normal phase between the simulation results in which the delay has changed, and sums them up. As a result, the timing margin at each signal change can be seen. The waveform display means 208 has, in addition to the waveform display function of one type of delay conventionally performed, a superimposition display means 209, a color display means 210 such as various errors, and the like.
Overlay display signal designating means 211 and waveform error
A search display unit 212 is provided. Among them, the superimposition display means 209 superimposes and displays the three types of delay waveforms based on the data on which the consistency check has been performed. The error of the check or the short pulse error can be identified by the background color or the color of the signal line. The superimposed display signal designating means 211 designates that superimposed display of a waveform is performed on a part of the signals.
The waveform error search display means 212 is for immediately searching for errors that have occurred on a long pattern and displaying them on the screen. Further, each delay detailed waveform display means 213 of the error portion is provided, and a detailed waveform of each delay is displayed.

FIG . 4 is a schematic operation flowchart of a logic circuit simulation according to the present invention. First, a logic circuit is input to the computer from the logic circuit input means 201 (step 401).
02, a test pattern is created and input (step 402). A simulation is performed by a computer (step 403), and in this embodiment, the minimum delay (M
IN), a standard delay (TYP), and a maximum delay (MAX), and each result is left. The result is displayed as a waveform (step 404).
Timing verification is performed (step 405). The present invention
Waveform display of step 404 in this flow and step 4
05 is a part of the timing verification.

FIG. 5, FIG. 6 and FIG. 7 are operation flowcharts for displaying a simulation result of a logic circuit according to an embodiment of the present invention. FIGS. 5, 6 and 7 show steps 404 and 405 of the flow of FIG. First,
It is checked whether there is a simulation result in each of the three delays of MIN, TYP, and MAX (step 501), and if not, it is determined whether there is a simulation result of TYP (step 501). 502) If not, the process ends. If there is a TYP simulation result, the TYP waveform is displayed (step 503).
Wait for command input (step 517). On the other hand, MI
If the simulation results of N, TYP, and MAX are all complete, it is checked whether or not to superimpose and display the waveforms (step 504). It is checked whether or not there is a signal designation (step 505). When the superimposed display of the waveforms is not performed, the TYP waveform is displayed (step 503), and input of a command is waited for (step 517). If all the signals are to be superimposed and displayed on the waveform, the signal is checked for waveform consistency (step 510). If the target is a designated signal, it is determined whether to designate a new signal or use an existing designation (step 506). If a new designation is to be made, a signal to be superimposed is designated, saved and saved (step 508),
Next, a waveform is displayed with TYP data for a signal for which superposition display is not performed (step 509). When the existing designation is used, the existing superimposition data is read (step 507), and the TYP waveform is displayed for the signal not superimposed (step 50).
9). In either case, a waveform consistency check is performed on the signal to be superimposed (step 510).

If the phases match among the three types of delays for each signal, all data is processed as a normal waveform, and a portion where the phases do not match is used as a waveform error. Among them, short pulses whose phases are shifted due to a short stable width are separated from waveform errors among errors detected as waveform errors (step 511). Next, with respect to the waveform (change point) determined as a normal phase, the width of the change delay at each change point (such as the delay width of the rise due to the delay) is calculated, and the change content is changed for each signal (0 → 1 and 1 → z). Here, the minimum shake, the maximum shake, and the average of the shakes are obtained (step 512). Next, a superimposed waveform is displayed on the signal to be superimposed based on the result of the waveform consistency check (step 513). Next, it is checked whether or not an error portion has a mask specification (step 51).
4) If not, a color is displayed as the color of the error so that the unmasked error can be identified as an error (step 516). If any of the masks is specified, the error of the masked portion is displayed with a color as the mask color so that it can be identified that the mask has been made (step 515).

In FIG. 6 and FIG. 7, it is checked whether or not a command has been input, and the process waits until there is no input (step 517). If there is a command input, the error portion is searched and it is checked whether or not the command is to be displayed (step 518). If so, it is checked whether the search is forward or backward (step 51).
9) If it is forward, it is checked whether there is an error before the current position (step 520). If there is an error, scroll so that the error portion is displayed on the screen.
(Step 521). In the backward search,
It is checked whether or not there is an error after the current phase (step 522). If there is, the same operation is performed so that the error is displayed on the screen (step 52).
1). Next, it is checked whether or not the command input is a display of detailed error information (step 523). If so, a window for displaying detailed error information is created (step 524), and the error is displayed. The waveform of each delay and the like are displayed as detailed information (step 525). If the command is not an error detailed information display command, and if the error detailed information display is completed, the next command input is an error.
It is checked whether or not the mask is specified for the portion (step 526). If so, all the change points and the change contents of the error are registered in the mask information data as a pattern for specifying the mask (step 527). ). Next, the error color display of the error portion is changed to the color display of the mask (step 528). Next, it is checked whether or not the command for terminating the waveform display and the waveform analysis is input (step 529), and if so, the process is terminated. Otherwise, a process for another command is executed (step 530), and the process returns to step 517 to wait for a command input.

FIG. 8 is a pulse waveform diagram displayed on the screen according to the present invention. FIG. 8 is a screen showing simulation results for the minimum delay (MIN), the standard delay (TYP), and the maximum delay (MAX). In each case, only SIGA and SIGB are shown in FIG. When these three types of delay waveforms are subjected to waveform consistency check processing to check the phase between the waveforms and superimpose the waveforms, a display as shown in FIG. 8 is obtained. The portion indicating the delay of each delay is displayed in a color indicating the delay of the change, and is identified by oblique lines in the figure. Further, the portion where the error has occurred is displayed with the color of the error and identified. FIG. 9 shows the error of the present invention.
It is a figure showing an example of detailed information display. In the error part, M
If IN, TYP, and MAX are superimposed, it will not be known. Therefore, the detailed display mode is selected and the corresponding error is selected (see step 523 in FIG. 7). Thereby, the waveforms of MIN, TYP, and MAX are separated and displayed as shown in FIG. Here, the MAX delay has no rise and no fall (that is, there is no signal return). In the waveform check, a normal waveform is processed only when NIN, TYP, and MAX are present in that order, and the change state is the same. In the case of FIG. 9, the change points are MIN, TYP, MAX.
Are not detected in this order, and are naturally detected as errors.

FIG. 10 is a diagram showing a short pulse during a waveform error in the present invention. The short pulse in the waveform error has a waveform as shown in FIG. 9 and the order of the change points is..., But since it is not MAX, the phase is not normal. However, since it is a short pulse, it is treated separately. That is, in the waveform error, a waveform (digit shift) in which the order is shifted by a short pulse
In order to detect a short pulse, a short pulse detection width is set, and a short pulse having a digit shift is detected using the short pulse detection width.
Although it is a short pulse, the order of the change points is MIN,
TYP, MAX, MIN, TYP, M
If it is AX, it is a normal short pulse. FIG.
FIG. 1 is a diagram illustrating a result of a difference tally by a change delay. FIG. 11 shows the results obtained by summing the change delay width at each change point.
Is displayed as shown. That is, for each of the minimum, average, and maximum, the minimum width, the maximum width, and the average of the change delay widths are displayed by the waveform and the number of times. In the above-described embodiment, the error is shown in vermilion, the short pulse is shown in light green, and the delay width of the change is shown in light blue + diagonal lines. It is also possible to use the degree of light instead of the color. In this embodiment,
Although the consistency check and display of the waveform are all performed at once, the present invention is not limited to this method.
A method of checking each displayed on the screen, a method of checking up to several times before and after the screen as one unit, and the like can be considered. In addition, in the present embodiment, the display timing of the signal to be superimposed and the signal to be superimposed are different from each other in the present embodiment. Is also conceivable. Further, the portion where the waveform is separated by the delay is displayed by changing the color for each delay. For example, MIN is dark blue, TYP is red, and MAX is purple.

In the present invention, when an ASIC or the like is developed in a logic simulator, a change delay at a changing point of each signal is grasped from a result of the simulation using the minimum, standard, and maximum delays. Waveform superposition can be displayed. This eliminates the need to purchase a special simulator and eliminates the conventional manual calculations and complicated operations. Since the signals to be displayed can be designated by superimposing the waveforms, the waiting time of the processing can be reduced. If the waveform display is compressed by increasing the time scale and displayed, the waveform will be finer, and it will not be possible to determine whether an error has occurred.Therefore, by changing the color of the error portion, the overall waveform can be displayed. It is possible to easily identify which part has an error, and it is possible to reduce complicated identification work by a human. When analyzing a waveform error, if a large number of short pulses are included, the amount of work will increase, but the short pulses should be displayed in a different color apart from the waveform error. Accordingly, the amount of work can be reduced, and identification by human eyes can be facilitated. Since the error parts can be sequentially searched and displayed, it is not necessary to search for errors scattered in a long test pattern using a screen scroll or the like, and the error parts can be easily viewed and checked. Can be. Since the detailed waveform of the error portion can be viewed, it is possible to easily view the detailed state of the error, and it is possible to eliminate the cumbersome data collection work by hand. By automatically summing up the difference due to the change delay,
It is possible to eliminate complicated measurement and counting work by hand. Since the mask can be set, it is possible to easily discriminate between an error that has been checked and no problem and an unchecked error, and it is possible to eliminate complicated management work by a person.

[0016]

As described above, according to the present invention, there is no need to purchase a special simulator, the waiting time for processing is shortened, manual calculations and complicated work can be eliminated, and the error can be eliminated. The operation for identifying the short pulse is also simplified, and the operation for identifying the short pulse is also facilitated. In addition, there is an effect that any data collection work, measurement work, totalization work and management work can be eliminated.

[0017]

[Brief description of the drawings]

FIG. 1 is an overall functional block diagram of a logic circuit simulation system showing one embodiment of the present invention.

FIG. 2 is a hardware configuration diagram of a logic circuit simulation system according to the present invention.

FIG. 3 is a diagram of a delay circuit according to the present invention.

FIG. 4 is an operation flowchart of the logic simulation system according to the present invention.

FIG. 5 is a part of an operation flowchart of the logic simulation result display device of the present invention.

FIG. 6 is another part of the operation flowchart of the logic simulation result display device as in FIG. 5;

FIG. 7 is another part of the operation flowchart of the logic simulation result display device as in FIG. 5;

FIG. 8 is a diagram showing a simulation result display screen with delay in the present invention.

FIG. 9 is a diagram showing detailed information of an error in the present invention.

FIG. 10 is an explanatory diagram of a short pulse in the present invention.

FIG. 11 is a diagram showing a difference totaling result by a change delay according to the present invention.

[Explanation of symbols]

Reference Signs List 101 Data processing unit 102 Mouse 103 Keyboard 104 Memory 105 Screen display unit 200 Logic simulation main unit 201 Logic circuit input means 202 Test pattern input means 203 Logic simulation means 204 Logic simulation for each delay -Result holding means 205 Waveform consistency checking means 206 Short pulse error detecting means 207 Measurement means of change width due to delay difference 208 Waveform display means 209 Overlay display means 210 Color display means of various errors 211 Overlay display Signal designation means 212 Waveform error search display means 213 Detailed delay waveform display means for each error portion

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-5-143670 (JP, A) JP-A-4-172563 (JP, A) JP-A-3-184177 (JP, A) JP-A-3-184177 138766 (JP, A) JP-A-2-105232 (JP, A) JP-A-63-198042 (JP, A) JP-A-61-219878 (JP, A) (58) Fields investigated (Int. Cl. ^7, DB name) G06F 17/50 668 G06F 17/50 672 JICST file (JOIS)

Claims (8)

(57) [Claims] 1. A logic circuit input means for inputting to a computer for simulating a logic circuit used for designing an ASIC or the like, and a test pattern input for creating an input pattern necessary for simulating the logic circuit. Means, a logic simulation means for executing a simulation using the logic circuit and the test pattern, and a logic simulation result holding means for each delay for holding simulation results for three types of delays, minimum, standard, and maximum, respectively. A logic circuit simulation result display device comprising: a waveform consistency check unit for checking whether the phases of the waveforms in the three types of delays are matched; and a waveform display unit. 2. The logic circuit simulation result display device according to claim 1, wherein said waveform display means comprises:
A superimposition display means for superimposing and displaying the waveforms of the three types of delays and a superimposition display signal designating means for designating a necessary signal of all the signals are designated by the superimposition display signal designating means. A logic circuit simulation result display device, wherein a waveform is superimposed and displayed on some of the selected signals. 3. The logic circuit simulation result display device according to claim 1, wherein:
It is characterized by having color display means such as various errors for displaying each error with a background color or a signal line color for a portion where an error occurs in the waveform consistency check or a short pulse error occurs. Logic circuit simulation result display device. 4. The logic circuit simulation result display device according to claim 1, wherein as a result of the check by the waveform consistency check means, if a waveform error is detected, the stability range is shorter than the waveform error. Short pulse detecting means for detecting a short pulse error that has shifted in phase; and color display means for displaying various errors and the like in a color different from the waveform error so that the short pulse can be handled separately from the waveform error. A logic circuit simulation result display device comprising: 5. The logic circuit simulation result display device according to claim 1, wherein:
A logic circuit simulation characterized by comprising a waveform error search and display means for searching for a waveform error in chronological order from a group of waveforms on a simulation result superimposed error display to move to and display a waveform screen of the previous and next error occurrence positions. Result display device. 6. The logic circuit simulation result display device according to claim 1, wherein:
A logic circuit simulation result display device, comprising: a delay detail waveform display means for displaying an error portion of a waveform by displaying a detailed waveform information for each delay of the waveform by indicating an error portion of the waveform. 7. The logic circuit simulation result display device according to claim 1, wherein a delay width of a rising edge, a falling edge, and the like due to a delay of each change point in each signal held in the delay-based logic simulation result holding means. A logic circuit simulation result display device, comprising a width measuring means for measuring a change in a delay difference for summing up a minimum, an average, and a maximum. 8. The logic circuit simulation result display device according to claim 1, wherein when the overlapped waveform is displayed by the waveform display means, it is confirmed that there is no problem with respect to each position error. A logic circuit simulation result display device, comprising: an error portion mask setting means for setting a mask for the error; and a color display means for changing various colors when the mask is set.