JP3146554B2 - Element isolation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method for electrically isolating a plurality of devices arranged on one semiconductor chip.

[0002]

2. Description of the Related Art FIGS. 10 to 12 show a LOCOS method which has been most commonly used as an element isolation method. In this conventional example, as shown in FIG. 10, a SiO ₂ film 12 obtained by selectively oxidizing the surface of a Si substrate 11 and a channel stopper 13 thereunder are formed in an element isolation region of the Si substrate 11.

[0003]

However, in this conventional example, the SiO ₂ film 12 is etched many times from the formation of the SiO ₂ film 12 to the formation of the transistor and the like. As a result, as shown in FIG. 11, the SiO ₂ film 12 recedes.

When the SiO ₂ film 12 recedes in this way, as shown in FIG. 12, when a diffusion layer 14 is formed in the active region of the Si substrate 11, the diffusion layer 14 and the channel stopper 13 come into contact with each other. . Since the channel stopper 13 has a higher impurity concentration than the Si substrate 11, the hot carrier generation rate is high at the junction between the diffusion layer 14 and the channel stopper 13. Therefore, in the above-described conventional example, a semiconductor device having excellent characteristics cannot be manufactured.

Incidentally, the diffusion layer 14 is the source / drain of the MOS transistor, and when the gate width of the MOS transistor is reduced due to miniaturization, the generation rate of hot carriers at the junction between the diffusion layer 14 and the channel stopper 13 is reduced. The effect of being high is remarkable, and the characteristics of the semiconductor device are further degraded.

Also, the diffusion layer 14 and the channel stopper 13
When the two are in contact with each other, the junction capacitance of the diffusion layer 14 increases, which also makes it impossible to manufacture a semiconductor device having excellent characteristics.

The SiO ₂ film 1 of the Si substrate 11
2 has a large number of crystal defects at the edge portion, that is, a portion below the bird's beak 12a, and this crystal defect causes a junction leak of the diffusion layer 14. Therefore, it is possible to manufacture a semiconductor device having excellent characteristics. Can not.

Further, when the width of the SiO ₂ film 12 is reduced for miniaturization, a parasitic transistor using the SiO ₂ film 12 as a gate oxide film is likely to punch through. In the diffusion layer 14, electric field concentration occurs at the corners, and punch-through occurs at a position deeper than the surface of the Si substrate 11. Therefore, it is difficult to prevent the punch-through with the shallow channel stopper 13.

If the energy of ion implantation of impurities for forming the channel stopper 13 is increased, the depth range of the channel stopper 13 can be widened. However, in this case, impurities may be ion-implanted also in the element active region in the step of FIG.

On the other hand, if the impurity concentration of the Si substrate 11 is increased, punch-through of the parasitic transistor can be prevented, but the above-mentioned influence of the generation of hot carriers becomes remarkable, and the characteristics of the semiconductor device are further deteriorated. I do. Therefore, in the above-described conventional example, the width of the SiO ₂ film 12 cannot be reduced, and a fine semiconductor device cannot be manufactured.

[0011]

According to the present invention, there is provided an element isolation method comprising the steps of: forming an oxidation-resistant film on a portion of a semiconductor substrate to be an element active region;
Forming a channel stopper 13 before Symbol semiconductor substrate 11 by the 6 as a mask, the channel stopper 13
Forming an oxide film 12 on the surface of the oxidation film 16 by oxidizing the surface of the semiconductor substrate 11 as a mask after forming the anti-oxidation film 16 and on the oxide film 1
A step of applying a resist 17 on the surface of the oxide film 12 , and the step of etching the resist 1 until the protrusion 16a on the edge 12a of the oxide film 12 in the oxidation resistant film 16 starts to be etched.
Etching back the oxide film 7 and the oxidation-resistant film 16;
A step of removing the raised portion 16a after the etch back
And the edge portion 12a after removing the raised portion 16a.
Removing the edge of the semiconductor substrate 11
Forming a groove 18 in a portion exposed by removing the edge 12a, and filling the groove 18 with a dielectric material 19.

[0012]

In the device isolation method according to the present invention, the oxidation resistant film 16 is used.
Is formed at the edge 12a of the oxide film 12, that is, at the boundary between the element active region and the element isolation region. A groove 18 is formed at this boundary, and the groove 18 is filled with a dielectric material 19. I have. For this reason, the channel stopper 13 formed in the element isolation region is not in contact with the diffusion layer formed in the element active region, so that the generation rate of hot carriers is low and the junction capacitance of the diffusion layer is small. In addition, since a portion having many crystal defects in the semiconductor substrate 11 is removed by forming the groove 18, the junction leak of the diffusion layer is small.

Since the dielectric 19 in the trench 18 prevents punch-through of a parasitic transistor having the oxide film 12 in the element isolation region as a gate oxide film, the width of the oxide film 12 in the element isolation region can be reduced. it can. Also,
Etch back between resist 17 and oxidation resistant film 16 is oxidation resistant
Stop when the ridge 16a of the film 16 starts to be etched.
It is easy to control this etch-back
You. In addition, since the steps from the step of removing the raised portions 16a of the oxidation-resistant film 16 to the step of filling the grooves 18 with the dielectric 19 can be performed in a self-aligned manner, the number of patterning steps does not increase.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention applied to the manufacture of a MOS transistor will be described below with reference to FIGS.

In this embodiment, as shown in FIG.
The surface of the substrate 11 is oxidized to form a pad SiO ₂ film 15, and the SiN film 1 is formed on the SiO ₂ film 15 by CVD.
6 is deposited.

Next, as shown in FIG. 2, the SiN film 16 is patterned so that the SiN film 16 is left only on a portion of the Si substrate 11 which is to be an element active region. Then, using the SiN film 16 as a mask, an impurity of the same conductivity type as that of the Si substrate 11 is ion-implanted into the Si substrate 11 to form a channel stopper 13 having a higher impurity concentration than the Si substrate 11.

Thereafter, the SiN film 16 is changed to an oxidation-resistant film and
The surface of the i-substrate 11 is selectively oxidized and Si
An O ₂ film 12 is formed. At this time, the SiO ₂ film 12 also enters under the edge of the SiN film 16 and the bird's beak 12
a is formed, and the bird's beak 12 of the SiN film 16 is formed.
The edge on top a becomes the raised portion 16a.

Next, as shown in FIG. 3, a resist 17 is applied to flatten the surface. And, as shown in FIG.
Under the condition that the etching rates of the resist 17 and the SiN film 16 are equal to each other, the resist 17 and the SiN film 16
And etch back. This etch back stops when the dissociated gas generated by etching the SiN film 16 is detected.

Next, as shown in FIG. 5, the SiN film 16 is isotropically etched using the resist 17 as a mask,
The protrusion 16a of the N film 16 is removed. Further, as shown in FIG. 6, the SiO ₂ film 12 is anisotropically etched using the resist 17 and the SiN film 16 as a mask,
SiO ₂ film 1 under ridge 16a of SiN film 16
The second bird's beak 12a is removed.

Next, as shown in FIG.
The iN film 16 is peeled off. Then, the SiO ₂ films 12, 1
5 as a mask, the Si substrate 11 exposed in the process of FIG.
Is anisotropically etched to form a groove 18 in the Si substrate 11. Then, as shown in FIG. 8, an SiO ₂ film 19 is deposited on the entire surface by a plasma CVD method using TEOS as a raw material.

Next, as shown in FIG. 9, the SiO ₂ film 19 is etched back to fill the groove 18 with the SiO ₂ film 19.
Further, the entire surface of the remaining SiO ₂ film 19 and SiO ₂ film 15 is removed by wet etching. At this time, the SiO ₂ film 12 for element isolation is also etched.
Since the iO ₂ film 12 is thick, there is no problem.

Since the portion of the Si substrate 11 exposed by the above-described wet etching is the element active region, the surface of the element active region is oxidized to form an SiO ₂ film (a gate oxide film of a MOS transistor). (Not shown).

Then, a gate electrode (not shown) of the MOS transistor is formed on a gate oxide film or the like,
A diffusion layer (not shown) serving as a drain is formed in the element active region to complete the MOS transistor.

[0024]

According to the element isolation method of the present invention, the generation rate of hot carriers is low, the junction capacity of the diffusion layer is small,
Since the junction leak of the diffusion layer is small, a semiconductor device having excellent characteristics can be manufactured. Further, since the width of the oxide film in the element isolation region can be reduced, a fine semiconductor device can be manufactured. Besides, with resist
Since the control of the etch-back with the oxidation-resistant film is easy and the number of patterning steps is not increased, the semiconductor device as described above can be easily manufactured.

[Brief description of the drawings]

FIG. 1 is a side sectional view showing a first step of an embodiment of the present invention.

FIG. 2 is a side sectional view showing a step following FIG. 1;

FIG. 3 is a side sectional view showing a step following FIG. 2;

FIG. 4 is a side sectional view showing a step following FIG. 3;

FIG. 5 is a side sectional view showing a step following FIG. 4;

FIG. 6 is a side sectional view showing a step following FIG. 5;

FIG. 7 is a side sectional view showing a step following FIG. 6;

FIG. 8 is a side sectional view showing a step following FIG. 7;

FIG. 9 is a side sectional view showing a step following FIG. 8;

FIG. 10 is a side sectional view showing a first step of a conventional example of the present invention.

FIG. 11 is a side sectional view showing a step following FIG. 10;

FIG. 12 is a side sectional view showing a step following FIG. 11;

[Explanation of symbols]

Reference Signs List 11 Si substrate 12 SiO ₂ film 12 a Bird's beak 13 Channel stopper 16 SiN film 16 a Ridge 18 Groove 19 SiO ₂ film

Claims (1)

(57) [Claims] And 1. A process for forming an oxidation-film on a portion to be a device active region of the semiconductor substrate, forming a channel stopper before Symbol semiconductor substrate with the oxidation resistant film as a mask, After forming the channel stopper, the oxidation resistant film is masked.
Forming an oxide film on the surface by oxidizing the surface of the semiconductor substrate in the disk, flat coating a resist on the oxidation film and the oxide film
A step of cloth, the raised portions on the edge portion of the oxide film of the oxidation film
The resist and the oxidation resistant film until etching starts
Etching back , removing the raised portion after the etch back, removing the edge portion after removing the raised portion, and removing the edge portion of the semiconductor substrate of the edge portion Forming a groove in a portion exposed by the removal, and filling the groove with a dielectric.