JP3146715B2 - Data demodulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to differential coded phase modulation (D
More specifically, the present invention relates to a data demodulator for reproducing digital data from a received signal subjected to PSK, and more particularly to an all-digital circuit suitable for wireless communication for an M (M is a positive integer) channel multiplexed time division multiple access (TDMA) digital car telephone system. And a data demodulation device.

[0002]

2. Description of the Related Art In a digital car telephone system in which fading exists, in communication between a radio base station and a mobile station, π / 4 shift QPSK which is one of DPSK signals is used.
(Hereinafter referred to as π / 4 QPSK) signal is recommended (for example, “Digital Car Phone System Standard”, RCR STD-27A, Jan. 1992, published by Radio System Development Center). A data demodulator for a DPSK signal needs to obtain appropriate symbol synchronization and correct a frequency shift (also referred to as a frequency offset) of a received signal to improve an error rate of demodulated data. Also, T
In the data demodulation device for the DMA system, it is necessary to quickly pull in the symbol synchronization and correct the frequency shift of the burst signal, and to perform the symbol synchronization and the frequency shift correction in consideration of noise resistance and the like during continuous reception.

[0003] One of the data demodulators in consideration of the above-mentioned problem is disclosed in the literature (41st IEEEVEHICULAR).
TECHNOLOGY CONFERENCE, pp6
52-pp656, May 1991 and IEICE Technical Report, RCS89-64, March 1990
Monday). This ACT (Adapt-iv
e Carrier Tracking) has been developed for a mobile station that requires miniaturization and low power consumption, and receives the π of the received intermediate frequency band.
The phase of the / 4QPSK signal is compared with the phase of the reference signal to detect the phase of the π / 4QPSK signal, and the detected phase is directly output as a digital value. The data demodulation device demodulates the digitally converted detection phase by a digital circuit capable of realizing an LSI to obtain quaternary code determination data.

[0004] The ACT type data demodulating apparatus is an ACT type data demodulating apparatus.
A circuit, an AFC circuit, and a phase frequency control circuit control the frequency and phase of the reference signal independently of each other, and
The carrier phase rotation of the / 4 QPSK signal is corrected for each symbol. Since this data demodulator controls the frequency shift of the π / 4 QPSK signal with respect to the reference signal independently of the reference phase for phase detection, the data demodulator responds quickly to a burst signal such as a TDMA signal. Does not have the function Also, this data demodulation device
The ACT circuit, the AFC circuit and the phase frequency control circuit require a somewhat complicated phase and frequency control circuit.

[0005]

SUMMARY OF THE INVENTION It is a first object of the present invention to provide a data demodulation apparatus for a differentially encoded phase modulation signal which is easily converted to an LSI and can be easily adjusted without any adjustment.

A second object of the present invention is to provide a data demodulation device suitable for receiving a TDMA signal.

A third object of the present invention is to provide a data demodulator having means for optimally adjusting the symbol synchronization phase of demodulated data.

A fourth object of the present invention is to provide a data demodulator having means for correcting a frequency shift of a received signal.

A fifth object of the present invention is to provide a data demodulating device which realizes the symbol synchronizing means and the frequency shift correcting means with a simple configuration.

A sixth object of the present invention is to provide a data demodulator capable of flexibly changing the set amount of the symbol synchronization phase and the correction amount of the frequency shift according to the state of a received signal.

[0011]

A data demodulating apparatus according to the present invention detects an N-phase clock by delay-detecting a DPSK-modulated TDMA signal by cascade-connected phase detecting means, delay means and phase difference detecting means. A phase difference signal synchronized with the signal is generated. This phase difference signal is reproduced as judgment data by the judgment means.

In one embodiment, the data demodulation device samples the determination data by using an optimum phase among the N sampling phases to obtain demodulated data with symbol synchronization. This data demodulation device is characterized by the method of obtaining the above-mentioned optimum sampling phase. The first sampling phase calculation means adds a determination error signal based on a difference between the phase difference signal and the determination data for a predetermined period for each input of the N-phase clock signal, and the added N determination signals The phase of the clock signal corresponding to the signal indicating the minimum value among the error signals is defined as the sampling phase. The second sampling phase calculation means weights the method of adding the decision error signal according to the reception state of the TDMA signal. One is to obtain a normal sampling phase by weighted averaging the sampling phase obtained by the preceding TDMA burst and the newly obtained sampling phase.

In another embodiment, the data demodulating apparatus subtracts a correction value from the phase difference signal between the phase difference detecting means and the judging means so as to reduce the phase difference due to a frequency shift of a received signal. A subtraction means for eliminating a DC offset of the signal is provided. This data demodulation device is characterized by the method of obtaining the correction value. The first correction value calculation means calculates an average value of a determination error signal based on a difference between the phase difference signal and the determination data within a certain period, and sets the average value as the correction value. The second correction value calculation means is a TDMA
The calculation method of the correction value is weighted according to the signal reception state. One of them takes into account the correction value obtained by the preceding burst when calculating the above-mentioned judgment correction value.

[0014]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a diagram showing the phase difference signals p3 and p3 in the embodiment of FIG.
It is a figure which shows the value of determination data d1 and the square value ea of the determination error. FIG. 3 is a signal timing chart of the embodiment of FIG.

Referring to FIGS. 1, 2 and 3 together,
This data demodulation device is included in a base station device of a digital car telephone system for the TDMA system. This base station device includes a transmitting device (not shown) for transmitting an M-channel TDMA signal, and an 800 MHz band transmitted from a plurality of mobile stations (not shown) on a designated channel of the M-channel TDMA signal. It includes a receiving device (not shown) for receiving the π / 4 QPSK signal, and a control device (not shown) for controlling the transmitting device and the receiving device. A high-frequency unit (not shown) of the receiving device converts the received π / 4 QPSK signal into a received signal r of an intermediate frequency (for example, 455 kHz) band. The data demodulation apparatus receives the π / 4 QPSK modulated reception signal r at the input terminal 100.

The data demodulating device is entirely composed of a digital circuit, and includes a well-known phase detecting means 101 and a delaying means 102.
, Phase difference detecting means 103, determining means 104, and received signal r
And a reference signal generating means 105 for generating a reference signal fr having a frequency substantially equal to K (K is a positive integer) times the center frequency of the reference signal fr. The phase detection means 101 shapes the waveform of the received signal r from the input terminal 100 to a logical level, and compares the zero-crossing point of the shaped signal r with the phase of the signal obtained by dividing the reference signal fr by K. The phase of the received signal r is detected.
The phase detecting means 101 further converts the detected phase into a received signal r using an N (N is a positive integer) phase clock signal clk from the timing generation circuit 106A, that is, c1,.
Is sampled N times per symbol (period Ts), and the sampled detection phase is used as the phase signal p1 of the received signal r. That is, the phase detection means 101 outputs the received signal r
In response to the reference signal fr and the clock signal clk, N phase signals p1 per symbol are output as parallel numerical data. Note that the phase detection accuracy of the received signal r by the phase detection means 101 is 2π / K radians.

The phase signal p1 is supplied to a delay means 102 using a shift register or the like, and the delay means 102 generates a delayed phase signal p2 obtained by delaying the phase signal p1 by one symbol. The phase difference detection means 103 subtracts the delayed phase signal p2 from the phase signal p1 to generate a phase difference signal p3 (p3 =
p1-p2). The phase difference signal p3 is a difference between the phase signal p1 (delayed phase signal p2) one symbol before and the newly received phase signal p1, that is, a signal obtained by delay detection of the π / 4 QPSK modulated reception signal r. . Judgment means 104
Compares the phase difference signal p3 with a predetermined value to generate determination data d1 of a two-column quaternary signal (see FIG. 2). That is, the determination unit 104 determines that the phase difference signal p3 is (−π to −π /
2), (-π / 2 to 0), (0 to π / 2) and (π /
It is determined which of the four ranges (2 to π) it belongs to, and the determination data d1, corresponding to the range, ie, (1, 1), (1,
0), (0,0) or (0,1). here,
N pieces of determination data d1 are generated per symbol of the received signal r.

In the following, description will be given of constituent elements which are features of the present embodiment. Here, the timing generation means 106 receives the frame signal f from the control device of the base station apparatus every time the received TDMA channel (frame) is switched (time t2 and t6), and receives a channel number indication signal synchronized with the frame signal f. ch, clock signal clk, clear signal cl
r and the sampling signal load (see FIG. 3). That is, the timing generation means 106 receives the clock signal clk starting from the TDMA channel switching times t2 and t6, the channel number indication signal ch simultaneously with the reception of the frame signal f, and the reception timing (time t1 and t5) of the specific TDMA channel. ), A sampling signal load is generated, and immediately after the generation of the sampling signal (time t2 and t6), a clear signal clr is generated.

First, the operation of the embodiment shown in FIG. 1 when the received signal r is a continuous signal will be described. In this case, the timing generation means 106 does not generate the channel number indication signal ch, and sets the sampling signal load and the clear signal clr to a predetermined cycle, here, the same frame cycle Tf as when the received signal r is an M-channel TDMA signal. Occurs in

The decision error squaring means 112 generates a square value ea of the decision error in response to the N-phase difference signal p3 and the decision data d1 (see FIG. 2). That is, the judgment data d1 (1,1), (1,0), (0,0) and (0,
Judgment phases -3π / 4, -π / respectively corresponding to 1)
The square value ea of the difference between the 4, π / 4 and 3π / 4 radians and the phase represented by the phase signal p3 is obtained at the output of the means 112 with the correspondence shown in FIG. If the received signal r is a π / 2 shift BPSK signal, the determination unit 104
Determines whether the phase difference signal p3 belongs to one of two ranges (−π to 0) and (0 to π), and generates determination data d1, corresponding to the range, that is, (1) or (0). Therefore, the determination phases corresponding to the determination data d1 of the π / 2 shifted BPSK signal are -π / 2 and π / 2 radians, respectively.

The N square error adding means 113-1,.
Each of 113-N is a clock signal c1,
, And eaN are added to each of the inputs of..., CN to generate sums of the determination errors ea1,..., EaN, and the sums of the determination errors ea1,.
Clear aN respectively. The sum of the judgment errors ea1, ...,
eaN are square error registers 115-1,..., 11
5-N. Square error register 115
,..., 115-N are sampling signals lo
At the timing of ad (time t1), the sum of the determination errors ea1,
, EaN are respectively sampled, and the sum es1,.
07A respectively. The square error adding means 1
, 113-N are determined errors (p1-d1) in each phase of the clock signal clk.
The value may be any value based on. Therefore, the determination error square means 1
Reference numeral 12 may be replaced with a determination error detecting means for generating an absolute value of the determination error (p1-d1).

The signal processing means 107A calculates the sampling phase signal s1 in response to the read sums es1,..., EsN of the judgment errors and the received information inf from the control device by a sampling phase calculation method described later. This sampling phase signal s1 is
Is instruction information for sampling the determination data d1 at the selected phase of the clock signal clk, and is a signal indicating the phase number of the clock signal clk. Signal processing means 1
07A writes the sampling phase signal s1 to the sampling phase register 114-1. Sampling means 11
1 samples the decision data d1 at the timing (phase) indicated by the clock signal clk and the sampling phase signal s1 from the sampling phase register 114-1, and converts the symbol rate demodulation data d2 obtained by optimizing and adjusting the symbol synchronization phase. It occurs at the output terminal 200. Incidentally, in the TDMA channel “1” of FIG.
Since “2” is written in −1, the demodulated data d
2 is the second phase (time t3 and t4) of the clock signal clk.

The operation of the embodiment when the received signal r is a TDMA signal having M channels will be described with reference to FIGS.

A data demodulation device for demodulating a TDMA signal having M channels includes M sampling phase registers 114-1,..., 114-M corresponding to the number M of channels. The signal processing means 107A sums the determination errors es read at each reception end timing of the reception TDMA channel (j channel, where j is an integer from 1 to M).
The sampling phase signal sj is calculated in response to 1,..., EsN and the received information inf, and the sampling phase signal sj is stored in the sampling phase register 114 for the j channel.
Write to -j. That is, the sampling phase register 1
, 114-M write sampling phase signals s1,..., SM of the corresponding TDMA channel, respectively. The sampling means 111 samples the determination data d1 at the sampling timing specified by the sampling phase signal sj and the clock signal clk corresponding to the channel indicated by the channel number instruction signal ch.
Note that, in the TDMA channel “1” in FIG. 3, the symbol synchronization timing (time t3 and time t3) of the demodulated data d2 when “2” is written in the phase register 114-1
4), and in channel “2”, the phase register 1
The symbol synchronization timing (time t7) of the demodulated data d2 when "N" is written in 14-N is shown.

FIG. 4 is a detailed block diagram of the signal processing means 107A in the embodiment of FIG.

Referring to FIG. 4, signal processing means 107A
Of the square error register 115-1,.
Each of the sums es1,..., EsN of the determination errors is read from each of the TDMA channels 115-N at the end of each TDMA channel.
Each of the sums es1,..., EsN of these determination errors is separately stored in N × M determination error storage memories 205 provided in the data RAM 204. The microprocessor (CPU) 201 calculates the sum es1,.
In response to each of esN, an optimum sampling phase signal sj for each TDMA channel is obtained.
Write to the sampling phase register 114-j of the A channel. Note that the CPU 203 is a program ROM 203
It operates according to the program stored in.

One method of calculating the optimum sampling phase signal sj of the decision data d1 is suitable when it is desired to quickly attain symbol synchronization at the start of reception of a burst-like received signal r (burst signal). Each of the square error registers 115-1,..., 115-N is the sum of the determination errors es.
, EsN, the signal processing means 107A calculates the sum es1,.
Is read to obtain the minimum value es i of the sum of the determination errors. The timing of the clock signal clk for the square error register 115-i giving the minimum value es i, that is, the phase of the i-th phase clock signal ci is set as the optimal sampling phase of the determination data d1. This calculation method of the optimal sampling phase signal si can be similarly applied to one or a plurality of TDMA channels.

Another method for calculating the optimum sampling phase si is suitable when the received signal r is a TDMA signal. That is, it is based on the fact that the deviation of the optimal sampling phase signal si between adjacent burst signals of the same channel TDMA signal is very small. Signal processing means 107
A calculates the weighted average of the past sampling phase value si and the newly calculated sampling phase signal si, instead of obtaining an entirely new optimum sampling phase signal si for each sample of the sum of the determination errors es1,. Then, a new sampling phase signal si is obtained. That is, the signal processing unit 107A calculates the weighted average determination error wesi from 1 to N phases according to the equation (1), and provides the clock signal of the square error register 115-i that gives the minimum value of the weighted average determination error wesi. The phase of ci is set as a new sampling phase signal si.

Wesi = ｛(sum of judgment errors esi) × w
+ (Value stored in determination error storage memory 205) × (1-
w)｝ (1) where 0 ≦ weighting coefficient w ≦ 1.

In this sampling phase calculation method, the greater the weighting coefficient w, the earlier the symbol synchronization pull-in. Therefore, the value of the weighting coefficient w is increased immediately after the reception of the reception signal r of a certain channel is started, and the weighting coefficient w is changed to a small value after the pull-in is completed in order to suppress fluctuation due to noise superimposed on the reception signal r. I do. When the reception signal r is not received, the square error memory 205 is cleared and set. When the reception of the reception signal r is started, the sampling phase signal s is determined only by the value of the square error register 115-i.
Determine i. As a result, in this data demodulation apparatus, the symbol synchronization phase of the short preamble burst signal r is quickly acquired. The CPU 201 changes the weighting coefficient w in response to the reception information inf for notifying the reception state of the reception signal r received from the control device and the software program in the program ROM 203. Since it is not preferable that the square error memory 205 is cleared due to the instantaneous interruption of the received signal r, the signal processing means 107A includes:
It is necessary to provide protection means for preventing the square error memory 205 from being cleared when the received signal r is momentarily interrupted, and for preventing a sudden change in the sampling phase signal si.

Known means can be used for collecting the above-mentioned received information inf. That is, the receiving apparatus receives π / 4
The reception electric field strength of the QPSK signal is detected, and when the reception electric field strength exceeds a predetermined level, the reception information inf is supplied to the signal processing means 107 via the control device. When the received signal r includes a synchronization signal, the known synchronization signal detection means transmits the reception information inf when detecting the synchronization signal. Further, when the received signal r is error detection coded, the error detection means of the receiving device
When the error detection code is detected, the reception information inf is transmitted. Further, when the wireless device has a communication procedure, the control device transmits reception information inf when detecting a signal expected in advance. As described above, since there are many means for determining whether or not a signal is being received, the wireless device can supply the reception information inf to the signal processing unit 107A by using a unit suitable for the data demodulation device.

FIG. 5 is a flowchart showing one operation of the signal processing means 107A of FIG.

Referring to FIG. 5, this flowchart shows a second sampling phase calculation method. CPU
Reference numeral 201 denotes a square error register 115-1 at the reception end time of a certain TDMA channel (t1 in the case of the M channel).
, EsN are read out from..., 115-N (step 11). The CPU 201 determines the judgment error storage memory 205 corresponding to these judgment errors es1,..., EsN (M-1,.
N), the weighted average determination errors wes1,..., WesN are respectively calculated according to the equation (1), and these weighted average determination errors we1,. -N) (step 12). Next, the CPU 201 obtains a sampling phase signal si (sM in the case of the M channel) corresponding to the minimum value of the weighted average determination errors wes1,..., WesN (step 13). Finally, the CPU 201 stores the obtained sampling phase signal si in the sampling phase register 114-j (114-M in the case of the M channel) (step 14). This sampling phase calculation flow is repeated for each channel of the TDMA signal.

FIG. 6 is a detailed block diagram of the sampling means 111 in the embodiment of FIG.

Referring to FIG. 6, the selector 253 of the sampling means 111 selects one of the M sampling phase signals s1,..., SM by designating the channel number indication signal ch. Since the channel of the TDMA signal is repeated from 1 to M, the selector 25
3 selects the sampling phase signal sj of the next channel (referred to as the j channel) according to the modulo M every time the channel number instruction signal ch is input. This sampling signal sj becomes a control signal for the selector 252. The selector 252 receives the N clock signals clk.
(C1,..., CN), here ci
Is selected by the phase number i indicated by the sampling phase signal sj. The sampling circuit 251 samples the decision data d1 at the phase of the clock signal ci selected as the optimum sampling phase, and generates symbol rate demodulated data d2.

As described above, since the data demodulation device of the embodiment shown in FIG. 1 is implemented as an all-digital circuit, it is easy to implement an LSI and eliminate adjustment. Further, since the symbol synchronization phase ci is optimized for each channel of the TDMA signal, demodulated data d2 with the lowest error rate can be obtained for each channel. Further, since the data demodulation apparatus flexibly changes the setting method of the sampling phase signal si of the decision data d1 according to the reception content of the reception signal r, it achieves a quick symbol synchronization pull-in at the start of the reception of the burst signal and has the same TDMA For continuous channel reception, data reproduction with few errors can be realized even if the noise of the received signal r is large.

FIG. 7 is a block diagram of another embodiment of the present invention.

Referring to FIG. 7, a data demodulating apparatus according to another embodiment of the present invention shown in a block diagram in FIG. 7 is similar to the embodiment of FIG.
Phase detection means 1 for receiving QPSK-modulated reception signal r
01, a delay means 102, a phase difference detection means 103, a judgment means 104 for generating judgment data d1 at an output terminal 200, a reference oscillator 105 for generating a reference signal fr, and a timing generation means 106. This data demodulation device includes a subtraction means 121 between a phase difference detection means 103 and a determination means 104.
And a signal processing unit 107B substantially similar to the embodiment of FIG. The signal processing unit 107B has the same components as the signal processing unit 107A, but differs in signal processing content as described later.

The center frequency of the received signal r is different from 1 / K of the reference signal fr (the received signal r has "frequency shift").
And the phase difference signal p3 is a signal having a DC offset. When the phase difference signal p3 having the DC offset is directly supplied to the judging means 104, the judging means 104 generates judgment data d1 having many errors caused by the DC offset. Therefore, the subtraction means 121 subtracts the correction value pr of the frequency shift from the phase difference signal p3 to generate a phase correction phase difference signal p4 from which the DC offset caused by the frequency shift has been removed. The corrected phase difference signal p4 is supplied to the judging means 104, and the judging means 104 generates judgment data d1 in which a data error caused by the frequency shift is reduced.

FIG. 8 is a diagram showing the values of the corrected phase difference signal p4, the decision data d1, and the decision error eb in the embodiment of FIG.

Referring also to FIG. 8, the judgment error detecting means 122 generates a judgment error eb in response to the corrected phase difference signal p4 and the judgment data d1. That is, the judgment data d1
(1,1), (1,0), (0,0) and (0,1)
Are -3π / 4, -π /
4, π / 4 and 3π / 4 radians.

FIG. 9 is a signal timing chart of the embodiment of FIG.

Referring also to FIG. 9, the decision error adding means 124 adds the decision error eb every time the symbol rate is N times, that is, every input of the N-phase clock signal clk, to generate the sum eb1 of the decision errors. , The timing before the start of reception of each TDMA channel (channel “1” is at time t2,
The “2” channel clears the sum eb1 of the determination errors in response to the clear signal clr at time t6). The period during which the determination error eb is added is one TDMA frame period (period Tf). When a clock signal clk that is correctly symbol-synchronized with the received signal r is obtained, the determination error adding means 1
24 is a clock signal cl having a period equal to the symbol period.
Even if the determination error eb is added with k (that is, N = 1), sufficient frequency deviation estimation accuracy can be maintained.

The sum eb1 of the judgment errors is stored in the judgment error register 1
26, and the determination error register 126 stores the timing of the sampling signal load (time t1 and t2).
Sample the sum eb1 of the decision errors, and sum the sum eb2 of the sampled decision errors to the signal processing means 10 respectively.
7B.

The signal processing means 107B responds to the read sum es3 of the judgment errors and the received information inf, and corrects the frequency deviation correction value pr for each TDMA channel of the received signal r.
, PrM are calculated as described later, and these correction values pr1,.
5-1..., 125-M. The selector 123 selects the correction register 125-j of the channel j indicated by the channel number instruction signal ch, and changes the correction value prj stored in the correction register 125-j to the correction value pr.
Is supplied to the subtraction means 121. That is, referring to FIG. 9, the selector 123 supplies the correction value pr = prM to the subtraction means 121 at the timing of receiving the “M” channel (until time t2), and receives the timing of receiving the “1” channel (time t2). From t5), the correction value pr = pr1
Is supplied to the subtraction means 121. Since the switching of the correction value pr by the selector 123 can be performed instantaneously, the data demodulating apparatus can immediately correct the frequency deviation even when the received signal r having the different frequency deviation for each TDMA channel is switched. it can. Such quick switching of the correction value pr is performed by the above-described RCS STD-27.
This is particularly effective for a data demodulation device that needs to change the correction value pr within several tens of microseconds, such as a digital car telephone system according to A (bit rate 42 kbps, M = 3).

Next, a first correction value calculation method suitable for quickly setting the correction values pr1,..., PrM when the reception of the burst signal r is started will be described.

Each time the decision error register 126 samples the sum eb2 of the decision errors, the signal processing means 107B reads out the sum eb2 of the decision errors, and at regular intervals, here, every one frame period Tf of the TDMA signal. An average value prj of the determination error eb of this channel (referred to as channel j) is obtained. If one frame period Tf is composed of H symbols, the number of additions of the decision error eb is N × H
And the average value prj is expressed by equation (2). The signal processing means 107B has M decision error storage memories 205 in the data RAM 204 for storing the sum eb2 of decision errors for each channel.

Prj = eb2 / (N × H) (2) p which is the average value of the determination error eb in this j channel
rj represents the DC offset amount of the phase difference signal p4. For example, if this average value prj is obtained in the channel M, the correction value pr of the currently set M channel
M is deviated from the appropriate correction value by the average value prj. Therefore, the signal processing unit 107B adds the average value prj to the correction value prM stored in the correction register 125-M for the M channel as shown in the equation (3), and adds the added value to the new correction value prM. As the correction register 12
Write to 5-M.

PrM ← prM + eb2 / (N × H) (3) If this new correction value prM is a sufficiently corrected value, the corrected phase difference signal p4 in the subsequent TDMA channel M
Has no DC offset, and the effect of frequency shift is removed in the M channel.

Further, a description will be given of a second correction value calculation method suitable for correcting a frequency deviation with respect to a TDMA signal from the same communication partner station (same channel).

The center frequency fluctuation of the received signal r during continuous reception in the same TDMA channel is often considered to be very small between adjacent bursts. In such a case, a completely new frequency deviation correction value p
r instead of calculating the correction value pr with a limited correction amount.
Is considered to be able to reduce the detection amount of the frequency deviation fluctuation when the reception signal r has a lot of noise. Therefore, in this correction value calculation method, the correction value pr is weighted by the weighting coefficient v and calculated as shown in equation (4) (for the M channel).

PrM ← prM + {eb2 / (N × H)} × v = prM + eb2 × v1 (4) where 0 ≦ weighting coefficient v ≦ 1, v1 = v / (N × H).

According to the second correction value calculation method, the larger the value of the weighting coefficient v, the shorter the frequency shift correction period.
Therefore, immediately after the start of the reception of the burst signal r, the weighting coefficient v
Is increased, and after completion of the frequency deviation correction in which the correction value prM becomes smaller than the predetermined value, the weighting coefficient v is changed to a small value in order to suppress fluctuation of the correction value prM due to receiver noise. In particular, when the first burst signal r is received, the frequency deviation can be corrected immediately by setting the weighting coefficient v to 1 (the same as in the first correction value calculation method). Received signal r
Is being received or not may be determined in exactly the same way as the method described in the embodiment of FIG.
The determination is made based on the reception information inf supplied to the 07B. Note that it is not preferable that the judgment error memory 205 is cleared due to the instantaneous interruption of the received signal r.
B needs a protection means for preventing the judgment error memory 205 from being cleared when the received signal r is momentarily interrupted, thereby preventing a sudden change in the correction value pr.

FIG. 10 is a flowchart showing one operation of the signal processing means 107B of FIG.

Referring also to FIG. 10, the flowchart shown in this figure shows a second correction value calculation method. The signal processing means 107B reads the sum eb2 of the judgment errors from the judgment error register 126 at the end time t1 of the M-channel TDMA signal (Step 21). Next, the signal processing unit 107B reads the correction value PrM of the channel M corresponding to the determination error eb2 from the correction register 125-M, and creates the correction value PrM in response to the sum eb2 of the read correction value and the determination error and the reception information inf. Using the weighting coefficient v (or v1) that changes with time, a new correction value prM is calculated according to the equation (4) (step 22). Finally, the signal processing unit 107B stores the new correction value prM in the correction register 125-M (Step 23). The above flow is repeated for each channel reception of the TDMA signal.

As described above, since the data demodulation device of the embodiment shown in FIG. 7 is also formed as an all-digital circuit, it is easy to implement an LSI and no adjustment. Further, since the frequency deviation is corrected instantaneously for each TDMA channel, demodulated data d2 with the lowest error rate can be obtained for each channel. In addition, the time constant of the frequency deviation correction can be flexibly changed according to the reception state of the received signal r, and the frequency deviation can be corrected quickly at the start of the reception of the burst signal r and with excellent noise immunity at the time of continuous reception. Can be.

[0058]

As described above, in the data demodulation device of the present invention, since all circuits including the symbol synchronization circuit or the frequency shift correction circuit are constituted by digital circuits, LS
It is easy to make an I circuit and eliminate adjustment. Further, this data demodulation device can flexibly set the symbol adjustment phase adjustment parameter and the frequency deviation correction parameter according to the reception state of the received signal by a plurality of calculation methods including a temporal change of the weighting coefficient by the signal processing means. Therefore, not only the symbol synchronization and the frequency shift for each TDMA channel can be quickly brought into the steady reception state, but also in the steady reception state, demodulated data can be reproduced with a low error rate even if there is much noise.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a diagram showing values of a phase difference signal p3, determination data d1, and a square value ea of a determination error in the embodiment of FIG.

FIG. 3 is a signal timing chart of the embodiment of FIG. 1;

FIG. 4 is a detailed block diagram of a signal processing unit 107A in the embodiment of FIG.

FIG. 5 is a flowchart showing one operation of the signal processing unit 107A of FIG. 4;

FIG. 6 shows a sampling unit 111 in the embodiment of FIG.
It is a detailed block diagram of.

FIG. 7 is a block diagram of another embodiment of the present invention.

8 is a diagram showing values of a correction phase difference signal p4, determination data d1, and a determination error eb in the embodiment of FIG.

FIG. 9 is a signal timing chart of the embodiment of FIG. 7;

FIG. 10 is a flowchart showing one operation of the signal processing unit 107B of FIG. 7;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 100 Input terminal 101 Phase detection means 102 Delay means 103 Phase difference detection means 104 Judgment means 105 Reference oscillator 106 Timing generation means 107A, 107B Signal processing means 111 Sampling means 112 Judgment error square means 113-1 to 113-N Square error Addition means 114-1 to 114-M Sampling phase register 115-1 to 115-N Square error register 121 Subtraction means 122 Judgment error detection means 123 Selector 124 Judgment error addition means 125-1 to 125-M Correction register 126 Judgment error Register 200 Output terminal 201 Microprocessor (CPU) 202 Input / output means 203 Program ROM 204 Data RAM 205 Judgment error register 251 Sampling circuit 252, 253 Selector

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-85044 (JP, A) JP-A-1-93241 (JP, A) JP-A-63-13416 (JP, A) JP-A-55-1979 25217 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 27/22 H04J 3/00

Claims (36)

(57) [Claims] 1. A phase of a differentially coded phase-modulated received signal is compared with a phase of a reference signal substantially equal to a center frequency of the received signal to detect a phase of the received signal and to change a symbol period of the received signal. Phase detection means for sampling a phase of the received signal detected every time a clock signal divided into N (N is a positive integer) is supplied to obtain a phase signal in a parallel signal format; Delay means for giving a delay of equal length to generate a delayed phase signal; phase difference detection means for subtracting the delayed phase signal from the phase signal to generate a phase difference signal; and the phase difference signal in response to the phase difference signal. A decision unit for producing decision data as a phase decision result of the phase difference signal, wherein the data demodulation device responds to the phase difference signal and the decision data, A determination error calculating means for calculating a determination error based on a difference between a phase of a phase difference signal and a determination phase of the determination data; and a sum of the determination errors by adding the determination error for each supply of the clock signal of a corresponding phase. And receives the clear signal to clear the sum of the determination errors.
Decision error adding means, N decision error registers each storing a sum of the decision errors from the decision error adding means corresponding to each supply of a sampling signal, and a sampling phase register storing a sampling phase signal. Sampling means for sampling the decision data at a phase indicated by the clock signal and the sampling phase signal to generate demodulated data at a symbol rate; and a sum of the decision errors from each of the N decision error registers. A signal including reading means for reading, sampling phase calculating means for calculating the sampling phase signal by a predetermined calculation method in response to each of the sums of the determination errors, and storage means for storing the sampling phase signal in the sampling phase register And processing means. Data demodulation apparatus according to symptoms. 2. The method according to claim 1, wherein the received signal is a π / 4 shift QPSK.
2. The data demodulation device according to claim 1, wherein the data demodulation is performed. 3. The decision error calculating means is a decision error squaring means for squaring the difference between the phase of the phase difference signal and the decision phase of the decision data to generate the decision error. The data demodulation device according to claim 1. 4. The determination error calculating means is an absolute value calculating means for calculating an absolute value of a difference between a phase of the phase difference signal and a determination phase of the determination data to generate the determination error. The data demodulation device according to claim 1, wherein 5. The data demodulation device according to claim 1, further comprising timing signal generating means for generating said clock signal, said sampling signal, and said clear signal. 6. An input / output means, wherein said signal processing means reads a sum of said judgment errors from each of said N judgment error registers at a predetermined cycle and writes said sampling phase signal into said sampling phase register. And a calculating means for sending any phase of the clock signal as the sampling phase signal to the input / output means in response to the sum of the N read determination errors. The data demodulation device according to claim 1. 7. The data demodulation device according to claim 6, wherein said calculating means sets a phase of said clock signal corresponding to a sum of said judgment errors indicating a minimum value as said sampling phase signal. 8. The input / output means further receives reception information indicating a reception state of the reception signal, and the calculation means further responds to the reception information, wherein the determination error is obtained by a weighting coefficient corresponding to the reception information. 8. The data demodulation device according to claim 7, wherein the phase of the clock signal indicating the minimum value of the sum of the correction determination errors is used as the sampling phase signal. 9. The data demodulation according to claim 8, wherein the sum of the correction judgment errors is a weighted average of the sum of the judgment errors in the preceding addition period and the sum of the newly added judgment errors. apparatus. 10. A first selector for selecting one of the sampling phase signals under the control of the channel number indication signal, and a sampling means controlling the sampling phase signal from the first selector. A second selector for selecting one of the N-phase clock signals; and a sampling circuit for sampling the determination data with the clock signal selected by the second selector to generate the demodulated data at a symbol rate. The data demodulation device according to claim 7, wherein: 11. Receiving a π / 4 shift QPSK modulated received signal, comparing the phase of the received signal with the phase of a reference signal substantially equal to the center frequency of the received signal, and detecting the phase of the received signal. The symbol period of the received signal is N
(N is a positive integer) phase detection means for sampling the phase of the received signal detected each time the clock signal divided into phases is supplied to obtain a phase signal in a parallel signal format, and the phase signal is equal to the symbol period. Delay means for providing a delay of a length to produce a delayed phase signal; phase difference detection means for subtracting the delayed phase signal from the phase signal to produce a phase difference signal; and the phase difference signal in response to the phase difference signal. A data demodulation device comprising: a determination unit that generates determination data that is a result of signal phase determination; wherein the data demodulation device includes a timing signal generation unit that generates a sampling signal, a clear signal, and the clock signal; A decision error 2 that squares the difference between the phase and the decision phase of the decision data to produce a squared value of the decision error.
Multiplying means, and adding the square value of the determination error each time the clock signal of the corresponding phase is supplied to generate a sum of the square values of the determination error, and receiving the clear signal and receiving the clear signal. N decision error adding means for clearing the sum of
N decision error registers each storing a sum of the decision errors from the decision error adding means corresponding to each supply of a sampling signal, a sampling phase register storing a sampling phase signal, the clock signal and the sampling phase Sampling means for sampling the decision data at a phase indicated by a signal to generate demodulated data at a symbol rate; and summing the sum of the squares of the decision errors from each of the N decision error registers at a predetermined cycle. I / O means for reading and writing the sampling phase signal to the sampling phase register, and corresponding to the sum of the squares of the decision errors indicating the minimum value of the sum of the N square values of the read decision errors. The input / output means using the phase of the clock signal as the sampling phase signal. Data demodulation apparatus further comprising a signal processing means including calculation means for sending. 12. Receiving a π / 4-shifted QPSK-modulated received signal, comparing the phase of the received signal with the phase of a reference signal substantially equal to the center frequency of the received signal, and detecting the phase of the received signal. The symbol period of the received signal is N
(N is a positive integer) phase detection means for sampling the phase of the received signal detected each time the clock signal divided into phases is supplied to obtain a phase signal in a parallel signal format, and the phase signal is equal to the symbol period. Delay means for giving a delay to produce a delayed phase signal; phase difference detecting means for subtracting the delayed phase signal from the phase signal to produce a phase difference signal; and a phase of the phase difference signal in response to the phase difference signal. A data demodulation device including a determination unit that generates determination data that is a determination result, wherein the data demodulation device includes a timing signal generation unit that generates a sampling signal, a clear signal, and the clock signal; A decision error 2 that squares the difference between the decision data and the decision phase to generate a square value of the decision error.
Multiplying means, and adding the square value of the determination error each time the clock signal of the corresponding phase is supplied to generate a sum of the square values of the determination error, and receiving the clear signal and receiving the clear signal. N decision error adding means for clearing the sum of
N decision error registers each storing a sum of the decision errors from the decision error adding means corresponding to each supply of a sampling signal, a sampling phase register storing a sampling phase signal, the clock signal and the sampling phase Sampling means for sampling the decision data at a phase indicated by a signal to generate demodulated data at a symbol rate; and summing the sum of the squares of the decision errors from each of the N decision error registers at a predetermined cycle. An input means for reading and receiving reception information indicating a reception state of the reception signal; an output means for writing the sampling phase signal to the sampling phase register; a sum of squares of the read N judgment errors and a preceding addition period A weighted average decision that is a weighted average of the sum of the squares of the N decision errors A signal processing unit including a weighted average determination error calculation unit for calculating an error and a calculation unit for sending a phase of the clock signal indicating the minimum value of the sum of the weighted average determination errors to the output unit as the sampling phase signal. A data demodulation device comprising: 13. The phase of a differentially coded phase-modulated received signal is compared with the phase of a reference signal that is substantially equal to the center frequency of the received signal to detect the phase of the received signal and to change the symbol period of the received signal. Phase detection means for sampling the phase of the received signal detected every time a clock signal divided into N (N is a positive integer) is supplied to obtain a phase signal in a parallel signal format; and delaying the phase signal by one symbol. A delay means for generating a delayed phase signal, a phase difference detecting means for subtracting the delayed phase signal from the phase signal to generate a phase difference signal, and a phase determination result of the phase difference signal in response to the phase difference signal. A data demodulation device comprising: a determination unit for generating certain determination data; wherein the received signal is an M (M is a positive integer) channel TDMA signal; A determination error calculating means for calculating a determination error based on a difference between a phase of the phase difference signal and a determination phase of the determination data in response to the difference signal and the determination data; and for each supply of the clock signal of a corresponding phase. The sum of the judgment errors is generated by adding the judgment error to the sum, and the sum of the judgment errors is cleared by receiving a clear signal.
Determination error adding means, N determination error registers respectively storing the sum of the determination errors from the determination error adding means corresponding to each supply of the sampling signal, and a sampling phase signal stored for each channel. M sampling phase registers, sampling means for sampling the decision data at phases indicated by the clock signal, the M sampling phase signals, and the channel number indication signal to generate demodulated data at a symbol rate; Reading means for reading the sum of the judgment errors from each of the judgment error registers for each channel, and calculating the sampling phase signal for each channel by a predetermined calculation method in response to each of the sums of the judgment errors Sampling phase calculating means and each of the sampling phase signals Data demodulating apparatus according to claim further comprise a a signal processing means including storage means for storing each of said M sampling phase registers. 14. The received signal is π / 4 shifted QPS.
14. The data demodulation device according to claim 13, wherein the data demodulation is K-modulated. 15. The decision error calculating means is a decision error squaring means for generating the decision error by squaring the difference between the phase of the phase difference signal and the decision phase of the decision data. The data demodulation device according to claim 13. 16. The determination error calculation means is an absolute value calculation means for calculating an absolute value of a difference between a phase of the phase difference signal and a determination phase of the determination data to generate the determination error. 14. The data demodulation device according to claim 13, wherein: 17. A timing signal generating means for receiving a frame signal notifying the TDMA channel switching of the received signal and generating the clock signal, the sampling signal, the clear signal, and the channel number indication signal synchronized with the frame signal. The data demodulation device according to claim 13, further comprising: 18. The method according to claim 18, wherein the sampling signal is generated immediately before the reception of each TDMA channel of the received signal is completed, and the clear signal is generated between the generation of the sampling signal and the reception of the frame signal. 18. The data demodulation device according to claim 17, wherein the number indication signal is created simultaneously with the reception of the frame signal. 19. The signal processing means reads the sum of the determination errors from each of the N determination error registers each time the sampling signal is supplied, and reads the sampling phase of the channel corresponding to the sampling phase signal. Input / output means for writing to a register; and calculation means for sending any phase of the clock signal as the sampling phase signal to the input / output means in response to the sum of the read N determination errors. 19. The data demodulation device according to claim 18, wherein: 20. The data demodulation device according to claim 18, wherein said sampling phase calculation means sets a phase of said clock signal corresponding to a sum of said judgment errors indicating a minimum value as said sampling phase signal. 21. The input / output unit further receives reception information indicating a reception state of the reception signal, and the calculation unit further responds to the reception information, wherein the determination error is determined by a weighting coefficient corresponding to the reception information. 19. The data demodulation device according to claim 18, wherein the phase of the clock signal indicating the minimum value of the sum of the correction determination errors is used as the sampling phase signal. 22. The method according to claim 18, wherein the sum of the correction judgment errors is a weighted average of the sum of the judgment errors in the preceding addition period and the sum of the newly added judgment errors.
The data demodulator according to any one of the preceding claims. 23. Receiving a π / 4 shift QPSK modulated reception signal, comparing the phase of the reception signal with the phase of a reference signal substantially equal to the center frequency of the reception signal, and detecting the phase of the reception signal. The symbol period of the received signal is N
(N is a positive integer) phase detection means for sampling the phase of the received signal detected each time the clock signal divided into phases is supplied to obtain a phase signal in a parallel signal format, and the phase signal is equal to the symbol period. Delay means for providing a delay of a length to produce a delayed phase signal; phase difference detection means for subtracting the delayed phase signal from the phase signal to produce a phase difference signal; and the phase difference signal in response to the phase difference signal. A data demodulation device comprising: determination means for generating determination data as a result of signal phase determination, wherein the received signal is an M (M is a positive integer) channel TDMA signal, and the data demodulation device performs TDMA of the received signal. Upon receiving a frame signal notifying frame switching, the clock signal synchronized with the frame signal and a sample signal created immediately before the reception of the TDMA frame is completed. Timing signal generating means for generating a clear signal created between the creation of the ring signal and the sampling signal and the reception of the frame signal and a channel number indication signal created simultaneously with the reception of the frame signal; A decision error squaring means for squaring a difference between a phase and a decision phase of the decision data to generate a square value of the decision error, and a square value of the decision error for each supply of the clock signal of the corresponding phase. N pieces of determination error adding means for adding the square value of the determination error to generate the sum of the square values of the determination error and for receiving the clear signal to clear the sum of the square values of the determination error; N decision error registers for respectively storing the sums of the decision errors from the decision error adding means, and M samples for storing a sampling phase signal for each of the channels A ring phase register, sampling means for sampling the determination data at a phase indicated by the clock signal, the M sampling phase signals, and the channel number indication signal to generate demodulated data at a symbol rate, and generating the sampling signal Input / output means for reading the sum of the squares of the decision errors from each of the N decision error registers at the same time and writing the sampling phase signal to the sampling phase register of the corresponding channel; 2 of the above judgment errors
Signal processing means further comprising calculation means for sending the phase of the clock signal corresponding to the sum of the squares of the determination errors indicating the minimum value of the sum of the power values to the input / output means as the sampling phase signal. A data demodulator characterized by the above-mentioned. 24. Receiving a π / 4 shift QPSK modulated reception signal, comparing the phase of the reception signal with the phase of a reference signal substantially equal to the center frequency of the reception signal, and detecting the phase of the reception signal. The symbol period of the received signal is N
(N is a positive integer) phase detection means for sampling the phase of the received signal detected each time the clock signal divided into phases is supplied to obtain a phase signal in a parallel signal format, and the phase signal is equal to the symbol period. Delay means for giving a delay to produce a delayed phase signal; phase difference detecting means for subtracting the delayed phase signal from the phase signal to produce a phase difference signal; and a phase of the phase difference signal in response to the phase difference signal. A data demodulation device comprising: a determination unit that generates determination data as a determination result, wherein the received signal is an M (M is a positive integer) channel TDMA signal, and the data demodulation device switches a TDMA frame of the received signal. A sampler that receives a frame signal to be notified and generates the clock signal synchronized with the frame signal and a TDMA frame immediately before reception of the TDMA frame is completed. A timing signal generating means for generating a clear signal generated between the generation of the signal and the sampling signal and the reception of the frame signal, and a channel number indication signal generated simultaneously with the reception of the frame signal; and a phase of the phase difference signal. And a decision error squaring means for squaring a difference between the decision data and the decision phase of the decision data to generate a square value of the decision error, and adding the square value of the decision error every time the clock signal of the corresponding phase is supplied. Means for generating a sum of the squares of the determination errors and receiving the clear signal to clear the sum of the squares of the determination errors; and the determination means corresponding to each supply of the sampling signal. N decision error registers each storing the sum of the decision errors from the error adding means, and M sampling errors storing a sampling phase signal for each channel. A phase register, sampling means for sampling the decision data at a phase indicated by the clock signal, the M sampling phase signals, and the channel number indication signal to generate demodulated data at a symbol rate, and a generation timing of the sampling signal Input means for receiving the sum of the squares of the judgment errors from each of the N judgment error registers and receiving reception information indicating the reception state of the reception signal, and transmitting the sampling phase signal to the corresponding channel. Output means for writing to the sampling phase register, weighting the sum of the squares of the read N pieces of the decision errors and the sum of the squares of the N pieces of the decision errors in the preceding addition period with a weighting coefficient according to the received information A weighted average judgment error calculating means for calculating an averaged weighted average judgment error, respectively, Data demodulation apparatus further comprising a signal processing means including storage means for sending a phase of the clock signal indicating the minimum value of the sum of average decision error in said output means as said sampling phase signal. 25. The phase of the differentially coded phase-modulated M-channel TDMA received signal is compared with the phase of a reference signal substantially equal to the center frequency of the received signal to detect the phase of the received signal. Set the symbol period of the signal to N
(N is a positive integer) phase detection means for sampling the phase of the received signal detected each time the clock signal divided into phases is supplied to obtain a phase signal in a parallel signal format, and the phase signal is equal to the symbol period. Delay means for providing a delay of a length to produce a delayed phase signal; phase difference detection means for subtracting the delayed phase signal from the phase signal to produce a phase difference signal; and the phase difference signal in response to the phase difference signal. A data demodulation device comprising: a determination unit that generates determination data as a phase determination result of a signal, wherein the data demodulation device is inserted between the phase difference detection unit and the determination unit and a position where the phase difference detection unit generates Subtracting means for subtracting from the phase difference signal a correction value for correcting the DC offset of the phase difference signal and supplying the corrected phase difference signal to the determination means; A determination error detecting means for detecting a difference between the phase of the phase difference signal and the determination phase of the determination data in response to the phase difference signal and the determination data; and A determination error adding means for adding a determination error every time the clock signal is supplied to generate a sum of the determination errors and receiving a clear signal to clear the sum of the determination errors; and A determination error register that samples the sum of the above and stores the sum of the determination errors; and M correction registers that store the correction values corresponding to each TDMA channel of the received signal;
A selector for selecting the correction value from one of the M correction registers in accordance with the instruction of the channel number instruction signal, reading means for reading the sum of the determination errors from the determination error register, and a sum of the read determination errors And signal processing means including correction value storage means for storing the correction values in the correction register of the corresponding channel in response to the TDMA channel. Data demodulator. 26. The received signal is π / 4 shifted PSK.
26. The data demodulation device according to claim 25, wherein the data is modulated. 27. A timing signal generating means for receiving a frame signal indicating TDMA channel switching of the received signal and generating the clock signal, the sampling signal, the clear signal, and the channel number indication signal in synchronization with the frame signal. 26. The data demodulation device according to claim 25, further comprising: 28. The method according to claim 28, wherein the sampling signal is created immediately before the end of the reception of each TDMA channel of the received signal, the clear signal is created between the creation of the sampling signal and the reception of the frame signal, 28. The data demodulation device according to claim 27, wherein the number indication signal is created simultaneously with the reception of the frame signal. 29. An input / output means wherein said signal processing means reads the sum of said judgment errors from said judgment error register at the timing of said sampling signal and writes each of said correction values to said correction register of a corresponding channel. And a correction value calculating means for calculating the correction values for each of the TDMA channels in response to the sum of the read determination errors and outputting these correction values to the input / output means. 28. The data demodulation device according to claim 28. 30. The calculation means calculates an average value of the sum of the determination errors for each of a predetermined period and for each of the TDMA channels, and applies the average value to the correction value stored in the correction register of the corresponding channel. 28. The data demodulation device according to claim 27, wherein addition is performed to obtain a new correction value. 31. The data demodulation device according to claim 30, wherein the predetermined period is one frame period of the TDMA signal. 32. The input / output unit further receives reception information indicating a reception state of the reception signal, and the calculation unit responds to the reception information to calculate the average value with a weighting coefficient corresponding to the reception information. 31. The data demodulation device according to claim 30, wherein the correction is performed, and the corrected average value is added to the correction value to obtain a new correction value. 33. When the calculating means receives the reception information indicating the first burst reception of the reception signal, calculates the average without correction, and receives the reception information indicating reception of the same TDMA channel. 33. The data demodulation device according to claim 32, wherein in the case, the average value corrected by the weighting factor is calculated. 34. A phase of the received signal of the M-channel TDMA system modulated by π / 4 shift QPSK modulation is compared with a phase of a reference signal substantially equal to a center frequency of the received signal to detect a phase of the received signal. Phase detection means for sampling a phase of the received signal detected each time a clock signal obtained by dividing a symbol period of the received signal into N (N is a positive integer) phases to obtain a phase signal in a parallel signal format; Delay means for providing a signal with a delay equal to the symbol period to generate a delayed phase signal, phase difference detecting means for subtracting the delayed phase signal from the phase signal to generate a phase difference signal, and the phase difference signal A determination unit that generates determination data that is a phase determination result of the phase difference signal in response to the data demodulation device. Receiving a frame signal notifying TDMA channel switching, the clock signal synchronized with the frame signal, a sampling signal created immediately before the end of reception of the TDMA channel, and a clear signal created between the creation of the sampling signal and the reception of the frame signal. A timing signal generating means for generating a signal and a channel number indication signal created simultaneously with the reception of the frame signal, and a phase difference signal generated between the phase difference detecting means inserted between the phase difference detecting means and the judging means. Subtracting means for subtracting the corrected phase difference signal by a correction value for correcting the DC offset of the phase difference signal and supplying the corrected phase difference signal to the determining means, and responding to the phase difference signal from the subtracting means and the determination data. Determination error detection means for detecting a difference between the phase of the phase difference signal and the determination phase of the determination data A determination error adding unit that adds the determination error every time the clock signal is supplied in the cycle in which the channel number indication signal is supplied to generate a sum of the determination errors, and receives the clear signal to clear the sum of the determination errors. Means, a decision error register that samples the sum of the decision errors for each supply of the sampling signal, and stores the sum of the decision errors, and stores M correction values corresponding to each TDMA channel of the received signal. A selector for selecting the correction value from one of the M correction registers in accordance with the instruction of the channel number instruction signal; reading means for reading the sum of the determination errors from the determination error register; Calculating an average value of the sum of the determination errors for each frame period of the TDMA signal in response to the sum of the determined determination errors. Calculating means for adding the average value to the correction value stored in the correction register of the corresponding TDMA channel to obtain a new correction value; and correcting values for storing these correction values in the correction register of the corresponding channel A data demodulation device, further comprising: signal processing means including storage means. 35. A phase of the received signal of the M-channel TDMA system modulated by π / 4 shift QPSK modulation is compared with a phase of a reference signal substantially equal to a center frequency of the received signal to detect a phase of the received signal. Phase detection means for sampling a phase of the received signal detected each time a clock signal obtained by dividing a symbol period of the received signal into N (N is a positive integer) phases to obtain a phase signal in a parallel signal format; Delay means for providing a signal with a delay equal to the symbol period to generate a delayed phase signal, phase difference detecting means for subtracting the delayed phase signal from the phase signal to generate a phase difference signal, and the phase difference signal A determination unit that generates determination data that is a phase determination result of the phase difference signal in response to the received signal. Receiving a frame signal notifying TDMA channel switching, the clock signal synchronized with the frame signal, a sampling signal created immediately before the end of reception of the TDMA channel, and a clear signal created between the creation of the sampling signal and the reception of the frame signal. A timing signal generating means for generating a signal and a channel number indication signal created simultaneously with the reception of the frame signal, and a phase difference signal generated between the phase difference detecting means inserted between the phase difference detecting means and the judging means. Subtracting means for subtracting the corrected phase difference signal by a correction value for correcting the DC offset of the phase difference signal and supplying the corrected phase difference signal to the determining means, and responding to the phase difference signal from the subtracting means and the determination data. Determination error detection means for detecting a difference between the phase of the phase difference signal and the determination phase of the determination data A determination error for adding the determination error in each cycle of the supply of the clock signal in a cycle in which the channel number indication signal is supplied to generate a sum of the determination errors and for receiving the clear signal to clear the sum of the determination errors An adder, a decision error register that samples the sum of the decision errors each time the sampling signal is supplied and stores the sum of the decision errors, and an M that stores the correction value corresponding to each TDMA channel of the received signal. Correction registers, a selector for selecting the correction value from one of the M correction registers in accordance with the instruction of the channel number instruction signal, and reading the sum of the determination errors from the determination error register, Reading means for receiving the reception information indicating the reception state, wherein the reading means reads out the TDMA signal every frame period. The average value of the sum of the errors is corrected by a weighting coefficient corresponding to the received information and calculated, and this average value is added to the correction value stored in the correction register of the corresponding TDMA channel to obtain a new correction value. And a signal processing means including a correction value storing means for storing these correction values in the correction registers of the corresponding channels. 36. The calculation means, when receiving the reception information indicating the first burst signal reception of the reception signal, calculates the average value without correction, and calculates the reception information indicating reception of the same TDMA channel. 36. The data demodulation device according to claim 35, wherein, when receiving, the average value corrected by the weighting factor is calculated.