JP3146993B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device comprising a memory cell region and a peripheral circuit region,
The present invention relates to a semiconductor device used as a memory (Dynamic Random Access Memory: DRAM) and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, DRAMs have been highly integrated, and accordingly, elements have been miniaturized.
When a DRAM is formed of a MOS (Metal Oxide Semiconductor) transistor, the gate length is reduced with miniaturization of the element, and various problems are caused by the so-called short channel effect. That is, the electric field intensity in the channel region increases due to the short channel, and hot carriers are generated near the drain, which are trapped in the gate oxide film or generate surface states.
As a result, characteristic deterioration such as a change in threshold voltage or a decrease in transconductance was caused. In order to prevent the characteristic fluctuation due to such hot carriers,
LDD (Lightly Doped) formed by offsetting a low concentration N ^- impurity diffusion region and a high concentration N ⁺ impurity diffusion region.
ped Drain) structures have been used. The low-concentration N ^- impurity diffusion region having the LDD structure is used to reduce the electric field intensity by suppressing the junction inclination of the PN junction, thereby suppressing generation of hot carriers.

In a DRAM, a signal charge stored in a capacitor of a memory cell disappears after a certain period of time due to a disturbance such as a leak current. Therefore, each signal is periodically stored in order to keep storing data. A refresh operation for updating the storage information of the memory cell is required. Since this refresh operation needs to be performed at a time interval shorter than the time during which the signal charge is held in the capacitor of the memory cell, the number of times of the refresh operation increases as the holding time of the signal charge becomes shorter. However, conventionally,
Since the capacitance of the capacitor was sufficiently large, the influence of the loss of the signal charge due to the leak current from the capacitor on the retention time of the signal charge was not so large. However, since the capacitance of the capacitor has been reduced due to the recent high integration of DRAMs and miniaturization of elements, the loss of the signal charge due to the leak current has an influence on the retention time of the signal charge, and the number of refresh operations has been reduced. There was a problem that it would increase. Therefore, in the N ⁻ type memory cell transistor in the memory cell region where charge retention characteristics are required, the source / drain region is formed of an N ⁻ diffusion layer which is excellent in relaxing the electric field strength and has little loss of signal charges. . A technique for preventing the characteristic deterioration due to the short channel effect described above and preventing signal charge leakage is disclosed in, for example, Japanese Patent Application Laid-Open No. 3-204969.

Hereinafter, a conventional method for manufacturing a semiconductor device disclosed in the above publication will be described with reference to FIG.
First, as shown in FIG. 5A, an element isolation oxide film 2 and an element formation region 3 are formed on a P-type substrate 1. Thereafter, a gate oxide film and a gate polysilicon film are formed in the element formation region 3, and then a gate 4 is formed in each of the memory cell region and the peripheral circuit region using a photolithography technique and a dry etching technique. Next, as shown in FIG. 5B, phosphorus ions are implanted using the gate 4 as a mask to form a low-concentration N ⁻ diffusion layer 5. Thereafter, for example, 80
At a high temperature of 0 ° C., a silicon oxide film (HTO)
After growing the film about 1000 to 2000 angstroms, anisotropic etching is performed to form sidewalls 6 on the side walls of the gate 4 (see FIG. 5C).

Next, a photoresist mask 7 having an opening in the peripheral circuit region is formed by using a photolithography technique, and then, as shown in FIG.
Using the gate 4a and the sidewall 6a in the peripheral circuit region as a mask, arsenic ions are implanted at an implantation energy of 50 keV and a dose of about 1 × 10 ¹⁵ atoms / cm ² , for example, to form a high concentration N ⁺ diffusion layer 8. As a result, FIG.
(E), the in the peripheral circuit region, NMOS transistors 9 of LDD structure, the memory cell area, N ^-
Type memory cell transistor 10 is formed.

[0006]

[SUMMARY OF THE INVENTION Incidentally, in the method of manufacturing the conventional semiconductor device, N of the NMOS transistor 9 ^- diffusion layer, the memory cell transistor 10 N ^-
The diffusion layer is formed with the same ion species and the same concentration. Examples of the ion species forming the N ^- diffusion layer include phosphorus ions and arsenic ions. In general, N
^- concentration profile gradual, phosphorous ions the electric field strength in the vicinity of the drain gradually changes have been used.
However, the NMOS transistor 9 having the N ⁻ diffusion layer formed by implantation of phosphorus ions having a large diffusion coefficient
When a heat treatment process for activation is performed in a later step,
Due to the thermal diffusion of the N ^- diffusion layer, the short channel effect becomes remarkable, and the threshold voltage is greatly reduced, so that it is difficult to shorten the gate length. For this reason, it is an obstacle to miniaturization of the element and, hence, high integration.

On the other hand, if arsenic ions are used to form the N ^- diffusion layer, the short channel effect can be suppressed and the resistance of the N ^- diffusion layer can be reduced, so that a high driving capability can be realized. However, the N ⁻ diffusion layer using arsenic ions has a steep concentration profile and a sharp change in electric field strength, so that signal charges are often lost, causing deterioration of signal charge holding characteristics in the memory cell region. There was a problem.

The present invention has been made in view of the above circumstances, and prevents loss of signal charges in a memory cell, and prevents deterioration of characteristics due to a short channel effect.
It is another object of the present invention to provide a semiconductor device capable of improving driving capability and a method for manufacturing the same.

[0009]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: a memory cell region in which an element for storing signal charges is formed;
A semiconductor device in which a peripheral circuit region on which elements for driving each element of the memory cell region are formed is provided on the same semiconductor substrate, and a arsenic ion concentration is formed in the peripheral circuit region. N having a source / drain region composed of a first impurity diffusion layer having a dual structure of a very low N ⁻ diffusion layer and an N ⁺ diffusion layer having a relatively high arsenic ion concentration
A channel MOS transistor and a memory cell transistor formed in the memory cell region and having a source / drain region formed of a second impurity diffusion layer having a phosphorus ion concentration lower than the arsenic ion concentration of the N ⁺ diffusion layer. It is characterized by being provided.

In a semiconductor device according to a second aspect of the present invention, a memory cell region in which elements for accumulating signal charges are formed, and elements for driving each element in the memory cell region are formed. A peripheral circuit region provided on the same semiconductor substrate, an N ^- diffusion layer formed in the peripheral circuit region and containing arsenic ions and phosphorus ions, a concentration of the arsenic ions and a concentration of the phosphorus ions. An N-channel MOS transistor having a source / drain region comprising a first impurity diffusion layer having a double structure with an N ⁺ diffusion layer containing arsenic ions having a concentration higher than the sum of are formed on, the concentration of phosphorus ions N ^- memory cells having substantially equal source-drain region of a second impurity diffusion layer and the concentration of phosphorus ion diffusion layer It is characterized by comprising a transistor.

Further, according to a third aspect of the present invention, there is provided the semiconductor device according to the first or second aspect, wherein at least the N-channel MOS transistor among the N-channel MOS transistor and the memory cell transistor is provided.
A sidewall is formed on a side wall of a gate of the OS transistor.

According to a fourth aspect of the present invention, there is provided a semiconductor device including a memory cell region in which elements for accumulating signal charges are formed, and elements for driving each element in the memory cell region. And a source / drain region formed in the peripheral circuit region and comprising a first impurity diffusion layer using arsenic ions without using phosphorus ions. And an N-channel MOS transistor having a second impurity diffusion layer formed in the memory cell region and having a phosphorus ion concentration lower than the arsenic ion concentration.
And a memory cell transistor having a drain region.

Further, according to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a memory cell region in which an element for storing signal charges is formed; and an element for driving each element in the memory cell region. A method of manufacturing a semiconductor device in which a peripheral circuit region in which is formed on the same semiconductor substrate, wherein a first step of forming a gate in each of the memory cell region and the peripheral circuit region; Forming a first photoresist mask having an open region;
And a third step of implanting phosphorus ions using the first photoresist mask and the gate of the memory cell region as a mask to form a low-concentration first impurity diffusion layer in the source / drain regions of the memory cell region. And a fourth step of forming a second photoresist mask having an opening in the peripheral circuit region; and implanting arsenic ions using the second photoresist mask and the gate in the peripheral circuit region as a mask. A fifth step of forming a low-concentration second impurity diffusion layer in the source / drain region of the circuit region, a sixth step of forming a third photoresist mask having an opening in the peripheral circuit region, and Arsenic ions are implanted using the photoresist mask and the gate in the peripheral circuit region as masks, and are implanted into the source / drain regions in the peripheral circuit region. It is characterized in that it comprises a seventh step of forming a third impurity diffusion layer of the concentration.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the fifth aspect of the present invention, wherein at least one of the N-channel MOS transistor and the memory cell transistor is provided. An eighth step of forming a sidewall on the sidewall of the gate of the N-channel MOS transistor is provided.

Further, according to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a memory cell region in which an element for storing signal charges is formed; and an element for driving each element in the memory cell region. Forming a gate in each of the memory cell region and the peripheral circuit region; and forming the gate in the peripheral circuit region on the same semiconductor substrate. A second step of implanting phosphorus ions as a mask to form a low-concentration first impurity diffusion layer in each of the source / drain regions of the memory cell region and the peripheral circuit region, and opening the peripheral circuit region; A third step of forming a first photoresist mask, and using the first photoresist mask and the gate of the peripheral circuit region as a mask.
Arsenic ions are implanted to form a low-concentration second impurity diffusion layer in the source / drain regions of the peripheral circuit region.
Using the first photoresist mask or the newly formed second photoresist mask and the gate of the peripheral circuit region as a mask, arsenic ions are implanted into the source / drain region of the peripheral circuit region. And a fifth step of forming a third impurity diffusion layer having a high concentration.

According to an eighth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the seventh aspect of the present invention, wherein at least one of the N-channel MOS transistor and the memory cell transistor is provided. A sixth step is to form a sidewall on the side wall of the gate of the N-channel MOS transistor.

Further, according to a ninth aspect of the present invention, in a method of manufacturing a semiconductor device, a memory cell region in which an element for storing signal charges is formed, and an element for driving each element in the memory cell region A method of manufacturing a semiconductor device in which a peripheral circuit region in which is formed on the same semiconductor substrate, wherein a first step of forming a gate in each of the memory cell region and the peripheral circuit region; Forming a first photoresist mask having an open region;
And a third step of implanting phosphorus ions using the first photoresist mask and the gate of the memory cell region as a mask to form a low-concentration first impurity diffusion layer in the source / drain regions of the memory cell region. And a fourth step of forming a second photoresist mask having an opening in the peripheral circuit region; and implanting arsenic ions using the second photoresist mask and the gate of the peripheral circuit region as a mask, Forming a high-concentration second impurity diffusion layer in the source / drain region of the peripheral circuit region without implanting phosphorus ions when the arsenic ions are implanted. And a step of implanting phosphorus ions into the source / drain regions.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. The description will be made specifically using an embodiment. First Embodiment FIGS. 1 and 2 are process diagrams showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention. Hereinafter, the manufacturing process of this example will be described step by step. First, as shown in FIG. 1A, an element isolation oxide film 12 and an element formation region 13 are formed on a P-type substrate 11. Thereafter, as shown in FIG. 1B, a gate oxide film 14 and a gate polysilicon film 15 are formed in the element forming region 13, and then, as shown in FIG. 1C, using photolithography. Then, a photoresist mask 16 for forming a gate pattern is formed.

Next, as shown in FIG. 1D, a gate 17 is formed in each of the memory cell region and the peripheral circuit region by using a photoresist mask 16 as a mask by a dry etching technique. Thereafter, a photoresist mask 18 having an opening in the memory cell region is formed by using the photolithography technique, and as shown in FIG. 1E, the photoresist mask 18 and the gate 17a in the memory cell region are used as a mask, for example, as shown in FIG. Then, phosphorus ions are implanted at an implantation energy of 30 keV and a dose of about 1.5 × 10 ¹³ atoms / cm ² to form a low-concentration N ⁻ diffusion layer 19 in the source / drain regions of the memory cell transistor.

Next, after the photoresist mask 18 is removed, a photoresist mask 20 having an opening in the peripheral circuit region is formed by photolithography. Thereafter, as shown in FIG. 2A, using the photoresist mask 20 and the gate 17b in the peripheral circuit region as a mask, for example, an implantation energy of 50 keV and a dose of 3 × 10 ¹³ atoms / cm ^{2 are used.}
Arsenic is ion-implanted to a degree to form a lightly doped N ^- diffusion layer 21 in the source / drain region of the NMOS transistor. Next, after removing the photoresist mask 20, a silicon oxide film is grown on the entire surface of the substrate at about 1000 to 2000 angstroms, and then anisotropically etched to form sidewalls 22 on the side walls of the gate 17 (FIG. 2).
(B)).

Next, a photoresist mask 23 having an opening in the peripheral circuit region is formed by using the photolithography technique, and then, as shown in FIG.
3. Gate 17b and sidewall 2 in peripheral circuit area
Using 2a as a mask, for example, an implantation energy of 50 ke
V, arsenic ions are implanted at a dose of about 1 × 10 ¹⁵ atoms / cm ² , and a high concentration N ⁺ diffusion layer 2 is formed in the source / drain regions.
4 is formed. As a result, as shown in FIG.
In the peripheral circuit region, an NMOS transistor 25 having a source / drain region having an LDD structure using arsenic ions is used.
However, in the memory cell region, a memory cell transistor 26 whose source / drain region is formed of an N ⁻ diffusion layer using phosphorus ions is formed.

Second Embodiment Next, a second embodiment will be described. FIG. 3 is a process chart showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention. Hereinafter, this manufacturing process will be described step by step. In the manufacturing process of this example, up to the step of forming the element isolation oxide film 32, the element formation region 33, and the gate 34 in the memory cell region and the peripheral circuit region on the P-type substrate 31, respectively, the first embodiment described above. Since this is the same as the example (see FIGS. 1A to 1D), the description thereof is omitted (FIG.
(A)). Subsequently, as shown in FIG.
Using the gate 34 as a mask, for example, the implantation energy 30
Phosphorus ions are implanted at a keV and a dose of about 1.5 × 10 ¹³ atoms / cm ² to form low-concentration N ⁻ diffusion layers 35 in the source / drain regions of the NMOS transistor and the memory cell transistor.

Next, a photoresist mask 36 having an opening in the peripheral circuit region is formed by photolithography. Thereafter, as shown in FIG. 3C, using the photoresist mask 36 and the gate 34a in the peripheral circuit region as a mask, for example, an implantation energy of 50 keV and a dose of 3 × 1 are used.
Arsenic is ion-implanted at about 0 ¹³ atoms / cm ² to form a low-concentration N ⁻ diffusion layer 21 composed of phosphorus ions and arsenic ions in the source / drain regions of the NMOS transistor.
Here, the dose amount of phosphorus ions may be a sufficiently small value that satisfies the driving capability value of the memory cell transistor. In the NMOS transistor, the dose amount is 1 × 10 ¹³ to prevent the short channel effect from occurring.
It is about 1.5 × 10 ¹³ atoms / cm ² .

Next, after removing the photoresist mask 36, a silicon oxide film is grown on the entire surface of the substrate by about 1000 to 2000 angstroms, and then anisotropically etched to form sidewalls 38 on the side walls of the gate 34 ( FIG. 3D). Next, using a photolithography technique, a photoresist mask 3 having an opening in a peripheral circuit region is formed.
Then, as shown in FIG. 3E, using the photoresist mask 39, the gate 34a in the peripheral circuit region and the side wall 38a as a mask, for example, an implantation energy of 50 keV and a dose of 1 × 10 ¹⁵ atoms / cm ^{2 are formed.} Arsenic is ion-implanted to a degree to form a high concentration N ⁺ diffusion layer 40 in the source / drain region of the NMOS transistor. As a result, as shown in FIG. 3F, the NMOS transistor 41 having a source / drain region having an LDD structure using phosphorus ions and arsenic ions in the peripheral circuit region, and the source / drain region in the memory cell region. Is formed of an N ⁻ diffusion layer using phosphorus ions to form a memory cell transistor 42. According to the second embodiment described above, the first
Compared with the embodiment, the number of times of forming a photoresist mask using the photolithography technique is reduced by one time.

Third Embodiment Next, a third embodiment will be described. FIG. 4 is a process chart showing a method for manufacturing a semiconductor device according to a third embodiment of the present invention. Hereinafter, this manufacturing process will be described step by step. In the manufacturing process of this example, after forming an element isolation oxide film 52, an element formation region 53, and a gate 54 on a P-type substrate 51 (see FIG. 4A), a photoresist mask 5 is formed.
5 and the gate 54a of the memory cell region as a mask,
A low-concentration N ^- diffusion layer 56 is formed in the source / drain region of the memory cell transistor (see FIG. 4B), and after removing the photoresist mask 55, the peripheral circuit region is opened using photolithography. The steps up to the step of forming the photoresist mask 57 are the same as those in the first embodiment (see FIGS. 1A to 1E), and a description thereof will be omitted.

Subsequently, as shown in FIG. 4C, a photoresist mask 57 and a gate 54b in the peripheral circuit region are formed.
Is used as a mask, for example, arsenic is ion-implanted at an implantation energy of 50 keV and a dose of about 1 × 10 ¹⁵ atoms / cm ² to form a high-concentration N ⁺ diffusion layer 58 in the source / drain regions of the NMOS transistor. As a result, FIG.
As shown in FIG. 1D, an NMOS transistor 59 having a single drain structure is provided in the peripheral circuit region, and an N-type transistor having a source / drain region using phosphorus ions is provided in the memory cell region.
^- the memory cell transistor 60 formed of a diffusion layer is formed.

Although the embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and changes in design and the like can be made without departing from the gist of the present invention. Even if there is, it is included in the present invention. For example, in each of the above-described embodiments, only the source / drain regions of the memory cell transistor are doped with low-concentration N using phosphorus ions.
^Although the example in which the transistor is formed by the diffusion layer is shown, the source / drain region of the transistor in the sense amplifier circuit portion may be formed by a low-concentration N ⁻ diffusion layer using phosphorus ions. Can be obtained.

In the first and second embodiments described above, the example is shown in which the sidewall is formed also on the side wall of the gate of the memory cell transistor. However, the sidewall may not be provided. In this case, in the first embodiment, after the formation of the N ⁻ diffusion layer 21, the formation of the sidewall 22 of the gate 17 b in the peripheral circuit region and the formation of the N ⁺ diffusion layer 24 are performed without removing the photoresist mask 20. Can be performed continuously. In the second embodiment, after the formation of the N ⁻ diffusion layer 37, the formation of the sidewall 38 of the gate 34 a in the peripheral circuit region and the formation of the N ⁺ diffusion layer 40 are performed without removing the photoresist mask 36.
Can be continuously formed. By doing so, the manufacturing process can be omitted and the efficiency is high. However, since the photoresist masks 20 and 36 are used successively in three steps, it is necessary to use those having higher durability than those in the other steps.

Further, the present invention is not limited to a DRAM,
It can be widely applied to logic devices and memories including dynamic memory cells. Further, the present invention can be applied to a device having a static memory cell or a device in which inverters are connected in a plurality of stages in series. In other words, the present invention can be widely applied to a semiconductor device which operates with a small current and includes a circuit portion which needs to hold electric charges for a certain period of time.

[0030]

As described in the foregoing, according to the semiconductor device and its manufacturing method of the present invention, N of the source and drain regions of the memory cell transistor ^- the diffusion layer, by using a phosphorus field strength is relaxed form In addition, since the N ⁻ diffusion layer of the transistor formed in the peripheral circuit region is formed using arsenic, loss of signal charges in the memory cell can be prevented, and characteristic deterioration due to the short channel effect can be prevented. In addition, there is an effect that the driving ability can be improved. Thereby, the reliability of the semiconductor device,
Productivity can be improved.

[Brief description of the drawings]

FIG. 1 is a process chart showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process chart showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 3 is a process chart showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a process chart showing a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

FIG. 5 is a process chart showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

11, 21, 31, 51 P-type substrate 17, 17a, 17b Gate 34, 34a, 54, 54a, 54b Gate 19, 21, 35, 37, 56 N ^- diffusion layer 22, 22a, 38, 38a Sidewall 16, 18, 20, 23 Photoresist mask 36, 39, 55, 57 Photoresist mask 24, 40, 58 N ⁺ diffusion layer 25, 41, 59 NMOS transistor 26, 42, 60 Memory cell transistor

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/108 H01L 21/8234 H01L 21/8242 H01L 27/088 H01L 29/78

Claims (9)

(57) [Claims] 1. A memory cell region in which elements for accumulating signal charges are formed and a peripheral circuit region in which elements for driving each element of the memory cell region are provided on the same semiconductor substrate. An N ⁻ diffusion layer formed in the peripheral circuit region and having a relatively low arsenic ion concentration, and N ⁺ having a relatively high arsenic ion concentration.
An N-channel MOS transistor having a source / drain region comprising a first impurity diffusion layer having a dual structure with a diffusion layer; and an arsenic ion formed in the memory cell region and having a phosphorus ion concentration of the N ⁺ diffusion layer. And a memory cell transistor having a source / drain region formed of a second impurity diffusion layer having a lower concentration than that of the semiconductor device. 2. A memory cell region in which elements for accumulating signal charges are formed and a peripheral circuit region in which elements for driving each element of the memory cell region are formed on the same semiconductor substrate. A N ^- diffusion layer formed in the peripheral circuit region and containing arsenic ions and phosphorus ions, and an arsenic ion having a concentration higher than the sum of the arsenic ion concentration and the phosphorus ion concentration. and N-channel MOS transistor having a source-drain region of a first impurity diffusion layer having a double structure of the N ⁺ diffusion layer containing said formed in the memory cell region, wherein the concentration of phosphorus ions N ^- diffusion A memory cell transistor having a source / drain region composed of a second impurity diffusion layer substantially equal to the concentration of phosphorus ions in the layer. Conductor device. 3. A side wall is formed on at least a side wall of a gate of the N-channel MOS transistor among the N-channel MOS transistor and the memory cell transistor. 3. The semiconductor device according to 2. 4. A memory cell region in which elements for accumulating signal charges are formed and a peripheral circuit region in which elements for driving each element of the memory cell region are provided on the same semiconductor substrate. A source device formed in the peripheral circuit region and comprising a first impurity diffusion layer using arsenic ions without using phosphorus ions.
An N-channel MOS transistor having a drain region; and a memory cell transistor formed in the memory cell region and having a source / drain region formed of a second impurity diffusion layer having a phosphorus ion concentration lower than the arsenic ion concentration. A semiconductor device, comprising: 5. A memory cell region in which elements for accumulating signal charges are formed and a peripheral circuit region in which elements for driving each element of the memory cell region are provided on the same semiconductor substrate. A first step of forming a gate in each of the memory cell region and the peripheral circuit region, and a second step of forming a first photoresist mask having an opening in the memory cell region. And a third step of implanting phosphorus ions using the first photoresist mask and the gate of the memory cell region as a mask to form a low-concentration first impurity diffusion layer in the source / drain regions of the memory cell region. Forming a second photoresist mask having an opening in the peripheral circuit region; and forming a second photoresist mask having an opening in the peripheral circuit region. A fifth step of implanting arsenic ions using the gate as a mask to form a low-concentration second impurity diffusion layer in the source / drain regions of the peripheral circuit region; and a third step of opening the peripheral circuit region. A sixth step of forming a photoresist mask, arsenic ions are implanted using the third photoresist mask and the gate of the peripheral circuit region as a mask, and a high concentration And a seventh step of forming an impurity diffusion layer of (3). 6. An eighth step of forming a sidewall on at least a side wall of a gate of the N-channel MOS transistor among the N-channel MOS transistor and the memory cell transistor. Item 6. The method for manufacturing a semiconductor device according to Item 5. 7. A memory cell region in which elements for accumulating signal charges are formed and a peripheral circuit region in which elements for driving each element of the memory cell region are provided on the same semiconductor substrate. A first step of forming a gate in each of the memory cell region and the peripheral circuit region, and implanting phosphorus ions using the gate as a mask to form the memory cell region and the peripheral region. A second step of forming a low-concentration first impurity diffusion layer in each source / drain region of the circuit region, a third step of forming a first photoresist mask having an opening in the peripheral circuit region, Arsenic ions are implanted using the first photoresist mask and the gate of the peripheral circuit region as a mask, and a low-concentration second ion is implanted into the source / drain regions of the peripheral circuit region. A fourth step of forming an impurity diffusion layer; and implanting arsenic ions using the first photoresist mask or the newly formed second photoresist mask and the gate of the peripheral circuit region as a mask, Forming a high concentration third impurity diffusion layer in the source / drain region of the region. 8. A sixth step of forming a sidewall on at least a side wall of a gate of the N-channel MOS transistor among the N-channel MOS transistors and the memory cell transistors. Item 8. The method for manufacturing a semiconductor device according to Item 7. 9. A memory cell region in which elements for accumulating signal charges are formed and a peripheral circuit region in which elements for driving each element of the memory cell region are formed on the same semiconductor substrate. A first step of forming a gate in each of the memory cell region and the peripheral circuit region, and a second step of forming a first photoresist mask having an opening in the memory cell region. And a third step of implanting phosphorus ions using the first photoresist mask and the gate of the memory cell region as a mask to form a low-concentration first impurity diffusion layer in the source / drain regions of the memory cell region. Forming a second photoresist mask having an opening in the peripheral circuit region; and forming a second photoresist mask having an opening in the peripheral circuit region; Implanting arsenic ions by using the gate as a mask and forming a high-concentration second impurity diffusion layer in the source / drain regions of the peripheral circuit region without implanting phosphorus ions when implanting the arsenic ions; And a step of implanting phosphorus ions into the source / drain regions of the peripheral circuit region.