JP3147155B2 - Semiconductor device and resistor arrangement method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of arranging a resistance element of a semiconductor device for obtaining a predetermined resistance value by connecting a plurality of unit resistors, and a semiconductor device according to the method.

[0002]

2. Description of the Related Art A feature of a semiconductor integrated circuit is that elements having similar characteristics can be manufactured by making the shapes of adjacent elements uniform. FIG. 6 shows a conventional example in which a resistor having a uniform characteristic is produced by utilizing this feature.

In the conventional example shown in FIG. 6, unit resistors R1 and R2 of the same size manufactured in the same process are arranged in parallel, and contacts 603 and 604 provided at one end of each unit resistor R1 and R2 are connected. By connecting, the resistance value between the point A and the point B on the side opposite to the contact 603, 604 of each unit resistor R1, R2 is set as the combined resistance value of each unit resistor R1, R2.

The resistors R1 and R2 arranged as described above have the same accuracy, but with such an arrangement, the parasitic capacitances Cd1 and Cd2 are connected to the resistors R1 and R2 between the points A and B.
Therefore, depending on the circuit, the frequency characteristics in a high frequency range are deteriorated. The parasitic capacitance C between the adjacent resistors R1 and R2
d1 and the parasitic capacitance Cd2 between the resistor and the substrate can be represented as shown in FIG.

The parasitic capacitance Cd1 can be considered as a parallel plate. If the sectional area of the resistors is S1, the distance between the resistors is d1, and the dielectric constant of the material between the resistors is ε, Cd1 = ε × (S1
/ D1). The parasitic capacitance Cd2 can be expressed as Cd2 = S2 × x, where S2 is the bottom area of the resistor and x is the capacitance per unit area of the resistor with respect to the substrate.

FIG. 8 is an equivalent circuit in which a second-order low-pass filter using an operational amplifier 801 is formed by the above-described resistors and the parasitic capacitance shown in FIG. 7 is added. Here, Cd is the combined capacitance of the parasitic capacitances Cd1 and Cd2 of R1 and R2.

The transfer function of the active filter circuit is

[0008]

(Equation 1) Is expressed by the following expression. By adding the parasitic capacitance Cd,
The transfer function is as follows.

[0009]

(Equation 2) As is clear from the transfer function of the equation (2), when the frequency increases (S → ∞), V _out / V _in = Cd / C2, and a finite value is obtained. to degrade.

FIG. 9 is a diagram showing a simulation result of frequency characteristics of the low-pass filter shown in FIG.
(A) is the equivalent circuit of FIG. 8 where Cd1 = 0.1 pF, Cd1
The case where 2 = 0.1 pF (Cd = 0.15 pF) is shown. As is apparent from this result, if a slight parasitic capacitance is formed between the point A and the point B, the gain in a high frequency band is deteriorated.

When a low-pass filter is constructed using a plurality of resistors, the deterioration of the frequency characteristics in the high frequency band is caused by the fact that the third-order low-pass filter other than the second-order filter and the first-order low-pass filter Occurs in any of the filters.

FIG. 10A is an ideal circuit diagram of a first-order low-pass filter, and FIG. 10B is a diagram illustrating a first-order low-pass filter constituted by the above-described resistors, and the parasitic capacitance shown in FIG. 7 is added. This is an equivalent circuit represented by

[0013] In this case, the transfer function considering the parasitic capacitance Cd between V _in and V _out is as shown below.

V _out / V _in = (SCd + R0) / (S2
CdC0R0SCd + R0) When the frequency increases (S → ∞), V _out / V _in = Cd /
(C0 + Cd), which is a finite value, so that the frequency characteristics in the high frequency range are degraded.

FIG. 11 is a diagram showing a simulation result of frequency characteristics of the low-pass filter shown in FIG.
10A is an ideal circuit diagram shown in FIG.
(B) is an equivalent circuit of 8 in the circuit diagram shown in FIG. 10 (b), where Cd = 1 pF, C0 = 0.1 μF, R1
This shows a case where the combined resistance of R2 and R2 is R0 = 100K. As is apparent from this result, it is understood that the gain in a high frequency band is deteriorated if a slight parasitic capacitance is formed.

[0016]

In the above-described conventional resistor arrangement, coupling occurs due to the parasitic capacitance of the resistor, and the frequency characteristic in a high frequency band is degraded. There is a problem that shortage occurs and operation failure occurs in a high frequency range.

The present invention has been made in view of the above-mentioned problems of the prior art, and obtains a predetermined resistance value by connecting a plurality of unit resistors formed in the same step and the same size. In this case, it is an object of the present invention to realize a resistor arrangement method capable of reducing the influence of a parasitic capacitance of a resistor and improving frequency characteristics in a high frequency range.

[0018]

A semiconductor device according to the present invention is arranged between the unit resistors in a semiconductor device which obtains a predetermined resistance value by connecting a plurality of unit resistors formed in the same step and the same size. A dummy resistor formed in the same step and the same size as the unit resistor provided with a plurality of contacts , and a plurality of contours provided in the dummy resistor.
First voltage applying means for making the potential of the dummy resistor uniform via a circuit, a substrate mounted so as to surround the unit resistance and the dummy resistance, and second voltage applying means for making the potential of the substrate uniform And characterized in that:

A method of arranging a resistor in a semiconductor device according to the present invention is a method of arranging a plurality of unit resistors formed in the same step and the same size to obtain a predetermined resistance value. A dummy resistor formed in the same step and the same size as the unit resistor and provided with a plurality of contacts is provided , and a plurality of the dummy resistors are provided on the dummy resistor.
The potential of the dummy resistor is made uniform through the contact, and the surrounding potential surrounding the unit resistor and the dummy resistor is made uniform.

In the present invention configured as described above, each unit resistor is shielded by a dummy resistor provided between the unit resistors and maintained at the same potential. No high-frequency characteristics are degraded.

[0021]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing the configuration of an embodiment according to the present invention.

In this embodiment, two unit resistors R1 and R2 of the same size manufactured in the same process are connected to the respective resistors R1 and R2.
Dummy resistor 1 of the same size manufactured in the same process as 2
The resistors R1 and R2 and the dummy resistors 101 to 103 are alternately arranged so as to be sandwiched by 01 to 103. The dummy resistors 101 to 103 are connected to each other by a wiring 106 and placed at a uniform predetermined potential Vb1, and the substrate 104 on which the unit resistors R1 and R2 and the dummy resistors 101 to 103 are mounted has a uniform potential Vb2. Has been placed. One ends of the unit resistances R1 and R2 are connected to each other by a wiring 105, so that a resistance value between the other points A and B of the unit resistances R1 and R2 is a combined value of the unit resistances R1 and R2.

In this embodiment, the dummy resistors 101 to 1
A large number of contacts (not shown) are arranged to make 03 a uniform potential and have a low impedance, and each contact is connected by an aluminum wiring 106.

FIG. 2 is a view showing a sectional structure of the present embodiment. By performing the above arrangement, the resistance between the resistors R1 and R2 is shielded by the dummy resistor 102 and the wiring 106 on the dummy resistor 102, and is further shielded by a region connected to the uniform power supply Vb1. The capacitance Cd1 is between the resistance R1 and the dummy resistance 102 (power supply Vb1) and the resistance R
2—between the dummy resistor 102 (power supply Vb1) and the parasitic capacitance Cd2 between the area surrounding the resistors R1 and R2 (power supply Vb2) to eliminate the coupling between the resistors R1 and R2. Is possible.

When this arrangement is used for a low-pass filter circuit, an equivalent circuit shown in FIG. 3 is obtained. Parasitic capacitance Cd1, Cd2 can be to a virtual ground of the input V _in and OP-AMP. Since the capacity of a virtual ground point of the input V _in and the operational amplifier 301 is not related to the transfer function, the transfer function is given by equation (1) will not occur the deterioration of the frequency characteristic in the high frequency range.

Here, in this equivalent circuit, Cd1 = 0.1p
The simulation result when F and Cd2 = 0.1 pF is shown in FIG. As is clear from this result, the state is equivalent to the ideal state, and between the power supply (Vb1, Vb
When the parasitic capacitances Cd1 and Cd2 are added to b2), the high-frequency characteristics do not deteriorate.

The resistors R1 and R2 and each of the dummy resistors 101 to 103 are composed of a plurality of resistance elements as shown in FIG. When the parasitic resistance Rd2 between Vb2 cannot be ignored (for example, Rd1 = Rd2 = 500
Ω), when these are taken into consideration, the sectional view is as shown in FIG. 4A, and its equivalent circuit is shown in FIG. The simulation result at this time is as shown in (c) of FIG. 9, and the frequency characteristics in the high frequency range are improved as compared with the conventional example.
There is an effect of about 30 dB at 00 MHz.

The arrangement method of the present invention shown in FIG.
When applied to the following low-pass filter, FIG.
It was possible to obtain characteristics close to the ideal shown in FIG.

[0030]

As described above, the resistor arrangement according to the present invention can be used to connect a plurality of unit resistors formed in the same step and the same size to obtain a predetermined resistance value. There is an effect that the number of rings can be reduced and frequency characteristics in a high frequency range can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment according to the present invention.

FIG. 2 is a diagram showing a cross-sectional configuration of the embodiment shown in FIG.

FIG. 3 is an equivalent circuit diagram when the embodiment of the present invention is applied to a low-pass filter.

FIG. 4A shows a parasitic resistance R between dummy resistance elements.
When the parasitic resistance Rd2 between d1 and the substrate-Vb2 cannot be ignored (for example, Rd1 = Rd2 = 500Ω), a cross-sectional view in which these are considered, and FIG. It is.

FIG. 5 is an equivalent circuit diagram of the circuit shown in FIG.

FIG. 6 is a diagram showing a configuration of a conventional example.

FIG. 7 is a sectional view of a conventional example.

FIG. 8 is an equivalent circuit diagram when the conventional example is applied to a secondary low-pass filter.

FIG. 9 is a diagram showing the result of simulating the characteristics of a secondary low-pass filter.

10A is an ideal circuit diagram of a primary low-pass filter, and FIG. 10B is an equivalent circuit diagram of the primary low-pass filter with the parasitic capacitance shown in FIG. 7 added.

FIG. 11 is a diagram showing a result of simulating the characteristics of a first-order low-pass filter.

[Explanation of symbols]

 R1, R2 Resistance 101 to 103 Dummy resistance 104 Substrate 105, 106 Wiring 301 Operational amplifier

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/04 H01L 21/822

Claims (6)

(57) [Claims] 1. A semiconductor device which obtains a predetermined resistance value by connecting a plurality of unit resistors formed in the same step and the same size, wherein the unit resistors arranged between the unit resistors have the same process and the same size. is formed, a dummy resistor having a plurality of contacts are provided, a first voltage applying means for uniform potential of the dummy resistor via a plurality of contacts provided in the dummy resistor, the unit resistors and the dummy resistor And a second voltage applying means for making the potential of the substrate uniform. 2. A first-order low-pass filter comprising the semiconductor device according to claim 1. 3. A second-order low-pass filter comprising the semiconductor device according to claim 1. 4. A method for arranging a plurality of unit resistors formed in the same step and the same size to obtain a predetermined resistance value, the method comprising the steps of: A dummy resistor provided with a plurality of contacts is formed, and the potential of the dummy resistor is made uniform through the plurality of contacts provided on the dummy resistor. A potential around the unit resistor and the dummy resistor is provided. A resistance arrangement method for a semiconductor device, wherein 5. A first-order low-pass filter formed by the method for arranging resistors of a semiconductor device according to claim 4. 6. A secondary low-pass filter formed by the method for arranging resistors of a semiconductor device according to claim 4.