JP3147456B2 - Cache memory system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory system, and more particularly to a cache memory system configured to transfer a data block between memories when a cache miss occurs.

[0002]

2. Description of the Related Art As shown in FIGS. 6A and 6B, a conventional cache memory system includes a main memory 3 for writing and reading data blocks according to a main memory control signal MMC and a main memory address MA. A cache memory 2 for writing / reading data blocks in accordance with a cache memory control signal CMC and a cache memory address CA; and a cache mishit signal CM which sequentially generates an upper address AH at a predetermined timing.
When IS is inactive, a lower cache address CAL is generated at a predetermined timing to generate a cache address CA composed of these addresses, and when the cache mishit signal CMIS becomes active, an address generator for invalidating the generation of the cache address CA. 11a, when the cache mishit signal CMIS becomes active, the count of the clock signal CK is started, and a lower main memory address MAL of a value sequentially counted up according to the clock signal CK is generated to generate an address generator 11a.
The counter 14 generates an active overflow signal OVFL when the count value reaches the maximum value by combining with the higher address AH from the main memory address MA.
a, an OR gate 13 that supplies the clock signal CK to the counter 14a when the overflow signal OVFL is inactive and masks the clock signal CK to the counter 14a when it becomes active, and when no cache miss occurs and the overflow signal OVFL Is active, the cache miss signal CMIS is made inactive, and the control signal CNT is changed to the cache memory control signal CMC. When a cache miss occurs, the cache miss signal CMIS is activated and the control signal CNT is changed to the main memory. Control signal MM
C includes a memory control unit 10a having a control signal generation unit 1a that outputs a data block, and controls writing, reading, and transfer of data blocks in the main memory 3 and the cache memory 2, and reading from the main memory 3 and the cache memory 2. A CPU 1a for performing various control processes including a process for a data block, a CPU 1a, a cache memory 2,
The configuration has a data bus 6 for transferring a data block between the main memories 3.

Next, the operation of the cache memory system will be described. FIG. 7 is a timing chart of signals at various parts for explaining the operation of the cache memory system.

While a cache miss does not occur, the cache miss signal CMIS is a low level inactive, the control signal CNT is a cache memory control signal CMC, and the CPU 1a is
To perform high-speed operation.

Now, the lower cache memory address CAL
Is "A", a cache miss signal CMIS becomes active at a high level, and the occurrence of a cache miss is notified to the address generation unit 1.
1a, inform the counter 14a. The counter 14a detects the high level of the cache mishit signal CMIS at the high rise (t1) of the clock signal KC, starts counting at this timing, and inactivates the over signal OVFL if it is active. A lower main memory address MAL which sequentially counts up according to CK is generated. At the timing of this t1, the control signal CNT switches to the main memory control signal MMC. On the other hand, the lower cache memory address CAL is undefined. As a result, the main memory 3 is accessed, the data block read from the main memory 3 is transferred to the CPU 1a via the data bus 6, and the processing for this data block is performed.

The maximum count value of the counter 14a is "3"
Then, the count value of the counter 14a (ie, MAL) is obtained by the fourth clock signal CK from the timing of t1.
Becomes "3" and the overflow signal OVFL becomes active at a high level. Then, at the next rise (t2) of the clock signal CK, the cache mishit signal CMIS becomes inactive (low level). As a result, the control signal CNT becomes the cache memory control signal CMC, and the cache memory address C
A becomes valid, and the access to the CPU 1a moves from the main memory 3 to the cache memory 2. That is, the number of data blocks read and transferred from the main memory 3 when a cache miss occurs is fixed to the maximum count value of the counter 14a ("4" in this example).

[0007]

In this conventional cache memory system, since the number of data blocks read from the main memory 3 and transferred when a cache miss occurs is fixed, the order of instructions and the cache There is a problem that a number of instructions that are read into the cache memory 2 but are not executed may occur depending on the position where the miss occurs. If there are many unexecuted instructions, the cache miss rate will be relatively high,
System performance decreases.

FIGS. 8A to 8C are schematic diagrams for explaining the relationship between the number of data block transfers at the time of a cache miss and the execution pattern of the CPU 1a. In FIG.
It is assumed that the cache memory 2 does not store four consecutive instructions from the instruction X to the instruction Y, and the CPU 1a continuously executes these four instructions, and the instruction 7 is a branch instruction. The number of cache misses by the CPU 1a is represented by “C
It is assumed that four clocks (Tm) are required until a cache miss occurs and the transfer of the data block is started, and one clock (Tt) is required to transfer one instruction during the transfer of the data block. Assuming that the number of data blocks is Tb, the number of clocks (T) required for the execution of the instruction Y besides the instruction execution until the execution of the instruction Y is completed is represented by T = (Tm + Tb.Tt) .C 8 (A), T = (4 + 1.1) ・ 4 = 20 clocks In FIG. 8 (B), T = (4 + 8.1) ・ 1 = 12 clocks In FIG. 4 + 4−1) · 1 = 8 clocks, and the loss time in the event of a cache miss is minimized in FIG. 8C.

In FIG. 8 (A), only instructions for which a cache miss has occurred are read from the main memory 3. However, the number of cache misses increases, resulting in a long time loss other than the instruction execution. 8B, the loss time is shorter than that of FIG. 8A, but in a program in which a branch instruction is executed and the frequency of branching is high, an instruction written in the cache memory 2 by data block transfer due to a cache miss is performed. Is often not executed by branching.

[0010] In these cases, the lost time difference differs by eight clocks. This also indicates that the selection of the number of data blocks greatly affects the performance of the entire system. However, the optimal number of data block transfers that occur at the time of a cache miss varies depending on the form of the program, the arrangement of instructions, and the like, so that it is very difficult to determine the number of data block transfers.

[0011]

A cache memory system according to the present invention comprises: a main memory for writing and reading a data block including a tag bit to and from a data bus in accordance with a main memory control signal and a main memory address; A cache memory for writing / reading data blocks in accordance with signals and cache memory addresses; write / read / transfer control of the data blocks in the main memory and the cache memory; and processing for data blocks read from the main memory and the cache memory A CPU for performing
A stop register for storing a reference tag bits, a cache memory system wherein the starts reading of the main memory to the cache memory for the cache memory and a cache miss occurs, is stored in the stop register Means for terminating reading of the data block of the main memory when the reference tag bit and the value of the tag bit of the data block read from the main memory match
Characterized in that it comprises a.

A tag bit corresponding to each data block and read at the time of reading these data blocks is provided, the same number of reference tag bits as the tag bits is stored in a stop register, and the comparator is read. And comparing the tag bit of each data block with the reference tag bit.

[0013]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIGS. 1A and 1B are a block diagram of a first embodiment of the present invention and an internal block diagram of a memory control unit of this embodiment, respectively.

This embodiment uses a main memory control signal MM
C and a main memory 3 for writing and reading data blocks in accordance with the main memory address MA; a cache memory 2 for writing and reading data blocks in accordance with the cache memory control signal CMC and the cache memory address CA; When AH is generated and the cache mishit signal CMIS is inactive (low level), a lower cache memory address CAL is generated at a predetermined timing to generate a cache address CA composed of these addresses, and the cache mishit signal CMIS is generated. The address generator 11 invalidates the cache memory address CA when it becomes active (high level), and the cache mishit signal C
When MIS becomes active, a lower cache memory address CAL is fetched, a lower main memory address MAL which sequentially counts up from the fetched value is generated according to a clock signal, and is combined with an upper address AH to generate a main memory address MA. 14. When the cache mishit signal CMIS is inactive, the control signal CNT is transmitted to the cache memory control signal (CM
C), the cache miss signal CMIS is activated when a cache miss occurs, and the control signal CNT is output as the main memory control signal MMC. When the comparison result signal RSTP becomes active (high level), a cache miss occurs. A control signal generator 12 for inactivating the hit signal CMIS and outputting the control signal CNT as the cache memory control signal CMC, and an OR gate for masking the supply of the clock signal CK to the counter 14 when the comparison result signal RSTP is active. 13 includes a memory control unit 10 having a main memory 3
A CPU 1 for performing various control processes including writing and reading transfer control of data blocks in the cache memory 2 and processing for data blocks read and transferred from the main memory 3 and the cache memory 2; and a stop register for storing comparison reference data RDT. 4 and a comparator 5 that compares the comparison reference data RDT with a predetermined portion of the data block read from the main memory and generates a comparison result signal RSTP that becomes active when they match. .

Next, the operation of this embodiment will be described.
FIG. 2 is a timing chart of signals at various parts for explaining the operation of this embodiment.

While no cache miss occurs, the cache miss signal CMIS and the comparison result signal RS
TP is a low level inactive, and the control signal CNT is a cache memory control signal CMC.
Access the cache memory 2 and perform high-speed operation.

Now, the lower cache memory address CAL
Is "A", a cache miss signal CMIS becomes active at a high level, and the occurrence of a cache miss is notified to the address generation unit 1.
1. Notify the counter 14. When the cache mishit signal CMIS goes high, the counter 14 takes in the rising edge (t1) of the clock signal CK and uses this value as an initial value to generate a lower main memory address MAL which sequentially counts up in accordance with the clock signal CK. This t1
At this timing, the control signal CNT switches to the main memory control signal MMC. On the other hand, the lower cache memory address CAL is undefined. As a result, the main memory 3 is accessed, and the data block read from the main memory is transferred to the CPU 1 via the data bus 6,
Processing is performed on this data block.

A predetermined instruction code is stored in the stop register 4 as comparison reference data RDT. Each time a data block is read from the main memory 3, the comparator 5 stores the instruction code (CDT) of this data block. The instruction code from the stop register 4 is compared with the instruction code, and when they match, the comparison result signal RSTP becomes active.
Occurs.

If the comparison result signal RSTP becomes active when the lower main memory address MAL is "A + 3" (t2), the cache mishit signal CMIS becomes inactive by the comparison result signal RSTP, and the counter 14 Stops the generation of the lower main memory address MAL, the address generator 11 generates the lower cache memory address CAL again, and
NT switches to the cache memory control signal CMC, and C
The access by the PU 1 moves from the main memory 3 to the cache memory 2.

As described above, when a cache miss occurs, the reading of the data block from the main memory 2 is terminated when the content of the data block read from the main memory 2 matches the content stored in the stop register 4. , The number of data blocks suitable for the sequence of instructions, the position where a cache miss occurs, and the like can be read.

FIG . 3 is a block diagram showing a specific example of the internal configuration of the stop register 4 and the comparator 5 of this embodiment .

The stop register 4 comprises a plurality of internal registers 41, and the comparator 5
And a plurality of internal comparators 51 for respectively comparing the stored contents (RDT) of the main memory 3 with predetermined data (CDT) in the data block from the main memory 3, and an OR for integrating the comparison results of the internal comparators 51 Gate 52 and this OR
Flip-flop 5 that latches the output of the gate in synchronization with clock signal CK and outputs the result as comparison result signal RSTP
3 is provided.

FIGS. 4A and 4B are a data format diagram of an example of a data block of this embodiment and a schematic diagram showing an example of contents stored in the stop register 4, respectively.

Each internal register 41 of the stop register 4
, The 6-bit instruction code IC is compared with the comparison reference data RD.
Stored as T. Generally, a branch instruction is likely to cause a cache miss in the flow of instructions. Since the cache memory 2 uses the locality of instructions, a high hit rate can be obtained with a small memory capacity. However, the hit rate is extremely high in a program in which the flow of instructions frequently shifts to a portion other than a local portion. descend. The flow of instructions changes when a branch or exception occurs due to execution of a branch instruction. This embodiment is particularly effective for a branch instruction whose instruction flow can be expected to change. That is, if the flow of the instruction is changed by the execution of the branch instruction, there is a possibility that the instruction after the branch instruction is not executed even if the block is read at the time of a cache miss. The instructions read from the main memory 3 due to the cache miss are limited to the instructions that are surely executed.
The cache memory 2 can be used effectively.

FIGS. 5A and 5B are a block diagram of a second embodiment of the present invention, and a data format diagram of data blocks and tag bits handled in this embodiment, respectively.

In this embodiment, 1-bit tag bit TG corresponds to each 16-bit data block DT.
Are stored in the main memory 3a. Then, one data block DT is read from main memory 3a, and at the same time, the corresponding tag bit TG is read. On the other hand, the stop register 4a stores the tag bit T
A reference tag bit RTG serving as a reference for G comparison is stored. The comparator 5a compares the read tag bit TG with the reference tag bit RTG, and outputs a comparison result signal RSTP which becomes active when they match. Other than the above, it is the same as the first embodiment.

Since this embodiment takes a form in which tag data TG corresponding to the data block DT is added to the main memory 3a, it is applicable not only to instructions but also to data cache misses. Further, since the comparison target is 1 bit, there is an advantage that hardware is simplified.

[0029]

As described above, according to the present invention, the comparison reference data is stored in the stop register, and when the data block or the tag bit read from the main memory coincides with the comparison reference data at the time of a cache miss, By ending the reading of the data blocks in the memory, it is possible to read the number of data blocks suitable for the instruction sequence, the location of the cache miss, and the like.
There is an effect that the loss time during which U does not execute an instruction can be reduced, and the processing speed of the system can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention and an internal block diagram of a memory control unit of this embodiment.

FIG. 2 is a timing chart of signals of respective parts for explaining the operation of the embodiment shown in FIG. 1;

FIG. 3 is a circuit diagram showing an example of an internal configuration of a stop register and a comparator of the embodiment shown in FIG.

FIG. 4 is a schematic diagram showing an example of a data format of a data block handled in the embodiment shown in FIG. 1 and an example of storage contents of a stop register.

FIG. 5 is a block diagram of a second embodiment of the present invention and a data format diagram of data blocks and tag bits handled in this embodiment.

FIG. 6 is a block diagram illustrating an example of a conventional cache memory system and a block diagram illustrating an internal configuration of a memory control unit of the cache memory system.

FIG. 7 is a timing chart of signals of respective units for explaining the operation of the cache memory system shown in FIG. 6;

8 is a schematic diagram illustrating a relationship between an execution pattern of a CPU and the number of data block transfers for explaining a problem of the cache memory system illustrated in FIG. 6;

[Explanation of symbols]

 1, 1a CPU 2 cache memory 3, 3a main memory 4, 4a stop register 5, 5a comparator 6 data bus 10, 10a memory control unit 11, 11a address generation unit 12, 12a control signal generation unit 13 OR gate 14, 14a counter

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12/08-12/12 G06F 9/44 501

Claims (1)

(57) [Claims] 1. A main memory for writing and reading a data block including a tag bit to and from a data bus in accordance with a main memory control signal and a main memory address, and writing and reading of a data block in accordance with a cache memory control signal and a cache memory address. A CPU that performs write, read, and transfer control of the data block in the main memory and the cache memory, and a process for the data block that is read from the main memory and the cache memory; and a stop that stores a reference tag bit. a cache memory system comprising a register, wherein the start the reading of the main memory to the cache memory for the cache memory and a cache miss occurs, the stopper And characterized in that it comprises means for terminating the reading of data blocks of the main memory when said tag bit value of the data block and the reference tag bits stored in Purejisuta read from the main memory match Cache memory system.