JP3147487B2 - Synchronous signal generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for controlling a system clock of an audio device that handles digital signals.

[0002]

2. Description of the Related Art Conventionally, when two or more types of system clocks exist in the same device in an audio device that handles digital signals, a PLL is used as a method of synchronizing one basic system clock with the other system clock. Control schemes have been adopted.

FIG. 3 shows a basic configuration of the device, which is composed of three elements, a phase comparator, a loop filter, and a voltage controlled oscillator. Since the technology and operation principle of the PLL control are widely known, the description of the basic operation is omitted.
As a feature, stable control can be achieved by proper circuit design even if there is no special relation between frequencies to be controlled. On the other hand, general conditions required in design include covering frequency fluctuations of the voltage controlled oscillator due to changes in the operating environment such as temperature characteristics, quick response characteristics, and little influence of input noise. Can be raised.

In order to satisfy these demands, adopting a PLL control system with a high performance today is being attempted by changing the order of the loop filter, or promoting the integration of each component from a separate IC into a single chip. Has become possible.

[0005]

As described above, the conventional PL
The L control method has a great feature that synchronization between system clocks can be achieved even if there is no special relationship between two frequencies, but has a disadvantage that the circuit scale is large and the cost is generally high.

The present invention has been made in view of the above problems, and has been described in
It is an object of the present invention to provide a synchronization signal generator capable of achieving synchronization between two frequencies.

[0007]

According to the present invention, there is provided a synchronizing signal generating apparatus for processing a digital signal.
System clocks with different frequencies
There are two types in one device, between the two system clocks
A synchronizing signal generating apparatus for synchronizing a first underlying
Of when the frequency is present as a common factor between the system clock and the other of the second system clock, comprising an oscillator whose oscillation frequency is set to the same frequency as the frequency of the second system <br/>-time clock, wherein A first system clock frequency or a frequency equal to the greatest common divisor thereof is applied to the input terminal of the oscillator as a synchronization input signal, and the output terminal of the oscillator outputs the same.
It is configured to output to the second system clock .

[0008]

The object of the present invention is to provide a synchronous signal generator which stably achieves synchronization between two kinds of system clocks having different frequencies at low cost.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a synchronizing signal generator according to the present invention.

FIG. 1 shows the configuration of a synchronization signal generator according to one embodiment of the present invention. In FIG. 1, 1 is a basic system clock source, 2 is a frequency divider, 3 is an oscillator, and 4 and 5 are input and output terminals of the oscillator 3, respectively.

The operation of this embodiment will be described below. In FIG. 1, the frequency of the system clock source 1 is represented by f
1. The dividing ratio of the frequency dividing circuit 2 is N, the frequency at the input terminal 4 of the oscillator 3 is fc, and the frequency at the output terminal 5 of the oscillator 3 is fosc.

Assuming that the required frequency of the second system clock is f2, the frequency f1 of one of the basic system clocks and the frequency f2 of the other one of the system clocks are assumed to have common divisor frequencies. If the frequency of the greatest common divisor is f12, the following relational expression holds.

[0013]

(Equation 1)

[0014]

(Equation 2)

In FIG. 1, f1 and fc are

[0016]

(Equation 3)

The following relationship is established. Here, if the frequency dividing ratio N of the frequency dividing circuit 2 is set to be the same as N1, the frequency f12, which is the greatest common divisor of f1 and f2, becomes the same as fc.

On the other hand, if the oscillation frequency of the oscillator 3 is fosc,

[0019]

(Equation 4)

However, L, L are set to values close to the frequency f2 of the other system clock requiring fosc.
By setting each constant such as C1, C2, C3, etc., the oscillation frequency fosc becomes

[0021]

(Equation 5)

As described above, an attempt is made to stabilize around the frequency of an integral multiple of N2 of the input signal fc. This is because the pull-in phenomenon occurs when the Q of the oscillator and the input level of the synchronous input signal fc are appropriately set to the values of R, C1, C2, and C3, and the (N2) th harmonic component among the harmonic components of the input signal fc. This is because the oscillation frequency fosc is synchronized by the wave.

In such a synchronous oscillation state, the stability of the oscillation frequency fosc is dominated by the stability of the basic system clock f1, which is the source signal of the synchronous input signal. A stable state with almost no cause of distortion is obtained. Therefore, as long as the stability of the basic system clock f1 is ensured, inexpensive logic elements such as inverters can be used as oscillators for the main components of the synchronous signal generator, and the peripheral parts such as coils and capacitors are particularly precise parts. It will be in a stable state without using.

Further, the frequency f1 of one of the basic system clocks and the frequency f2 of the other one of the system clocks are changed.

[0025]

(Equation 6)

When there is a relationship, the frequency dividing circuit 2 of FIG. 1 becomes unnecessary, and the frequency f1 of the basic system clock can be used as it is as a synchronization input signal, so that the apparatus can be further simplified.

FIG. 2 is a circuit diagram of a synchronizing signal generator according to another embodiment of the present invention. 1 to 5 in FIG.
Has the same configuration as that of FIG. Reference numeral 6 denotes a waveform shaping circuit, reference numeral 7 denotes a circuit block which operates on one basic system clock f1, and reference numeral 8 denotes a circuit block which operates on the other one system clock f2. A digital signal data line synchronized with one of the basic system clocks f1 is connected between the circuit block 7 and the circuit block 8.

This embodiment is an example in which a crystal oscillator is used as one of the basic system clock sources 1. The frequency f1 is 512.fs used in general digital audio equipment, and the other one is the other. The system clock f2 is assumed to be 384 · fs. Where fs is the sampling frequency and generally 44.1kHz or 48kHz
Just think.

The operation of the synchronizing signal generator constructed under such conditions will be described below.

Since the frequency which is the greatest common divisor between one basic system clock f1 and the other system clock f2 is 128 · fs, the frequency dividing ratio N of the frequency dividing circuit 2 is N.
Should be set to 4. At this time, the frequency at the input terminal 4 of the oscillator 3 is fc.

[0031]

(Equation 7)

## EQU1 ## Also, the oscillation frequency fosc of the oscillator 3
Can be easily set to a frequency close to 384 · fs by appropriately setting each constant such as L, C1, C2, and C3.

Since the frequency fc applied to the input terminal 4 of the oscillator 3 is generally not a perfect sine wave, the third harmonic component becomes 384 · fs, and the oscillation frequency fos of the oscillator 3
Since the frequency is close to c, the oscillator 3 enters the synchronous oscillation state if the Q of the oscillation circuit and the level of the applied injection signal are appropriately set in the same manner as described in the first embodiment, and the oscillation frequency fosc becomes the synchronous input signal. fc, the phase is synchronized with one of the basic system clocks f1, and the frequency is also 384 · fs, which coincides with the other required system clock f2.

The synchronous oscillation frequency fosc (=
f2) By making the output into an appropriate level and waveform through the waveform shaping circuit 6, the output can be supplied to the other circuit block 8 operated by the other system clock f2.
As a result, digital signal data transferred between the circuit blocks 7 and 8 can be processed without any problem.

[0035]

As described above, according to the present invention, the frequency is
Two different system clocks exist in the same device,
Synchronization signal generator for synchronizing the two system clocks
The base first system clock and other
When there is a common divisor frequency between the second system clocks, the same frequency as the second system clock is used.
An oscillator in which an oscillation frequency of a frequency is set;
The input end of the oscillator, the first system clock frequency or its
Applied as a synchronizing input signal a frequency equal to the greatest common divisor
Output to the second system clock from the output terminal of the oscillator.
With the arrangements to force a synchronization signal generator for generating a first sheet <br/> system clock frequency equal frequency synchronization other second system clock with a good underlying, PLL circuit , And can be realized at low cost.

[Brief description of the drawings]

FIG. 1 is a block diagram of a synchronization signal generator according to one embodiment of the present invention.

FIG. 2 is a circuit diagram of a synchronization signal generator according to another embodiment of the present invention.

FIG. 3 is a block diagram of a synchronous control device configured by a conventional PLL control method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Basic system clock source 2 Divider 3 Oscillator 4 Input terminal of oscillator 3 5 Output terminal of oscillator 3 6 Waveform shaping circuit 7 Circuit block operated by system clock f1 8 Circuit block operated by system clock f2 10 Phase comparison Vessel 11 loop filter 12 voltage controlled oscillator

Claims (1)

(57) [Claims] 1. An audio device for handling digital signals,
There are two types of system clocks with different frequencies in the same device, and a synchronization signal that synchronizes the two system clocks.
No. A generator, when the underlying first system clock and the other frequencies of common divisor between the second system <br/> time clock is present, those
Comprising an oscillator whose oscillation frequency is set to the same frequency as the frequency of the second system clock, the input of the oscillator, the first sync input system clock frequency <br/> or frequency equal to the greatest common divisor Signal as the second system clock from the output terminal of the oscillator.
A synchronization signal generator configured to output the synchronization signal to a synchronization signal.