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JP3147758B2 - Evaluation method of insulation layer - Google Patents
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JP3147758B2 - Evaluation method of insulation layer - Google Patents

Evaluation method of insulation layer

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Publication number
JP3147758B2
JP3147758B2 JP34168595A JP34168595A JP3147758B2 JP 3147758 B2 JP3147758 B2 JP 3147758B2 JP 34168595 A JP34168595 A JP 34168595A JP 34168595 A JP34168595 A JP 34168595A JP 3147758 B2 JP3147758 B2 JP 3147758B2
Authority
JP
Japan
Prior art keywords
insulating layer
electric field
field strength
voltage
breakdown
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP34168595A
Other languages
Japanese (ja)
Other versions
JPH09178800A (en
Inventor
一弘 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Sumitomo Metal Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal Industries Ltd filed Critical Sumitomo Metal Industries Ltd
Priority to JP34168595A priority Critical patent/JP3147758B2/en
Publication of JPH09178800A publication Critical patent/JPH09178800A/en
Application granted granted Critical
Publication of JP3147758B2 publication Critical patent/JP3147758B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Relating To Insulation (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子に設け
てある絶縁層の耐電圧及び耐久性,又は絶縁層の良・不
良等を評価する方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for evaluating the withstand voltage and durability of an insulating layer provided on a semiconductor device, and the quality of an insulating layer.

【0002】[0002]

【従来の技術】半導体基板に形成したMOSキャパシタ
の酸化層又はトランジスタのゲート酸化層等,半導体素
子に設けられた絶縁層は、半導体素子の高密度化に伴い
その厚みが減じられている一方、電源電圧を低くするこ
とは困難であるため、絶縁層は高い電界強度の下で使用
されている。従って、半導体素子の信頼性を確保する上
で、絶縁層を詳細に評価することが重要である。
2. Description of the Related Art An insulating layer provided on a semiconductor element such as an oxide layer of a MOS capacitor or a gate oxide layer of a transistor formed on a semiconductor substrate has been reduced in thickness as the density of the semiconductor element has increased. Since it is difficult to lower the power supply voltage, the insulating layer is used under a high electric field strength. Therefore, it is important to evaluate the insulating layer in detail in order to secure the reliability of the semiconductor element.

【0003】そのような評価方法に絶縁破壊耐圧測定法
がある。この方法では、半導体基板に形成した複数の半
導体素子の絶縁層それぞれに印加する電圧を段階的に昇
圧し、所定の電流が検出されたときの電圧を絶縁破壊電
圧とする。(絶縁破壊電圧/絶縁層の厚み)で表される
絶縁破壊電界強度が所定の値以上,例えば8MV/cm
以上である絶縁層を良とし、そうでないものを不良とす
る。そして、印加した総数に対する良であった数の割合
に基づいて、絶縁層の優劣を評価する。しかし、このよ
うな絶縁破壊耐圧測定法は、短時間で評価を行うことは
できるものの、半導体素子の使用状態に応じた評価,即
ち経時的な評価を行うことができないという問題があっ
た。
[0003] One such evaluation method is a dielectric breakdown voltage measurement method. In this method, the voltage applied to each of the insulating layers of a plurality of semiconductor elements formed on the semiconductor substrate is stepped up, and the voltage when a predetermined current is detected is defined as the breakdown voltage. The dielectric breakdown electric field strength represented by (dielectric breakdown voltage / thickness of insulating layer) is not less than a predetermined value, for example, 8 MV / cm
The above-mentioned insulating layer is regarded as good, and the others are regarded as defective. Then, the quality of the insulating layer is evaluated based on the ratio of the good number to the total number of applied layers. However, such a dielectric breakdown voltage measurement method has a problem that although it can be evaluated in a short time, it cannot perform an evaluation according to a use state of a semiconductor element, that is, an evaluation over time.

【0004】そのため、絶縁層に一定の電圧を連続的に
印加し続け、所定の時間間隔で電流を検出して経時的な
変化を求め、絶縁破壊に至るまでの時間,その経過等を
詳細に評価するTDDB(Time Dependent Dielect
ric Breakdown)法が開発されており、このTDDB法
の改良方法として、印加する電圧を段階的に昇圧すると
共にChen −Holland−Hu モデルを適用する方法が特
開平 6-34704号公報に記載されている。
Therefore, a constant voltage is continuously applied to the insulating layer, a current is detected at predetermined time intervals, a change with time is obtained, and the time until the dielectric breakdown, its progress, and the like are described in detail. TDDB (Time Dependent Dietect)
A method of increasing the applied voltage stepwise and applying a Chen-Holland-Hu model is described in JP-A-6-34704 as an improved method of the TDDB method. I have.

【0005】図6は、その評価方法の実施に使用する装
置の構成を示すブロック図であり、図中11は導電性の基
板である。基板11上には絶縁層12が形成してあり、該絶
縁層12上には電極13が形成してある。電極13は印加する
電圧の大きさを段階的に変化し得る可変電源15の一端子
に接続してあり、可変電源15の他端子は電流計14を介し
て基板11に接続してある。そして、可変電源15は0V近
傍の所定の電圧から段階的に昇圧し、絶縁破壊が生じる
まで複数回,所定時間ずつ絶縁層12に印加するようにな
っている。
FIG. 6 is a block diagram showing a configuration of an apparatus used for carrying out the evaluation method. In the figure, reference numeral 11 denotes a conductive substrate. An insulating layer 12 is formed on a substrate 11, and an electrode 13 is formed on the insulating layer 12. The electrode 13 is connected to one terminal of a variable power supply 15 capable of changing the magnitude of the applied voltage stepwise, and the other terminal of the variable power supply 15 is connected to the substrate 11 via an ammeter 14. Then, the variable power supply 15 is stepped up from a predetermined voltage near 0 V in a stepwise manner and is applied to the insulating layer 12 a plurality of times for a predetermined time until dielectric breakdown occurs.

【0006】電流計14の検出電流Iは比較器17に与えら
れる。また、比較器17には、その値を越えた場合は絶縁
破壊が生じたと判断する閾値電流を発生する閾値電流発
生装置18から、印加した電界強度が6MV/cm以下の
場合は閾値電流JCR1 が、また印加した電界強度が6M
V/cmを越える場合は閾値電流JCR2 (JCR1 <J
CR2 )が与えられるようになっており、比較器17は閾値
電流JCR1 又は閾値電流JCR2 と検出電流Iとを比較す
る。その結果、印加電圧が6MV/cm以下であり、J
CR1 <Iである場合、その絶縁破壊は絶縁層12に存在す
るピンホール等の初期不良又は絶縁層12のムラ等の欠陥
によって生じたと判断する。一方、印加した電圧が6M
V/cmを越えており、JCR2 <Iである場合、その絶
縁破壊は欠陥のない絶縁層において耐電圧を越えたこと
によって生じたと判断する。
The detection current I of the ammeter 14 is supplied to a comparator 17.
It is. In addition, the comparator 17 is insulated when the value is exceeded.
A threshold current generator that generates a threshold current that determines that breakdown has occurred
The electric field intensity applied from the raw device 18 is 6 MV / cm or less.
If the threshold current JCR1But the applied electric field strength is 6M
If it exceeds V / cm, the threshold current JCR2(JCR1<J
CR2) Is given, and the comparator 17
Current JCR1Or threshold current JCR2And the detection current I
You. As a result, the applied voltage was 6 MV / cm or less, and J
CR1If <I, the dielectric breakdown exists in the insulating layer 12
Defects such as initial defects such as pinholes or unevenness of the insulating layer 12
Is determined to have occurred. On the other hand, when the applied voltage is 6M
V / cm, JCR2If <I, the absolute
Edge breakdown exceeds breakdown voltage in defect-free insulating layer
Is determined to have occurred.

【0007】そして、絶縁破壊に至るまでの印加回数,
印加時間,及び印加した電界強度を用い、Chen −Hol
land−Hu モデルに基づいて絶縁層破壊寿命を求め、求
めた絶縁層破壊寿命にワイブル分布を適用してTDDB
曲線を算出し、算出したTDDB曲線に基づいて絶縁層
12の経時的な絶縁破壊を評価する。このように段階的に
印加電圧を高くすることによって、いわゆる加速度試験
を実施してTDDB曲線を計算によって求めるため、前
述した従来のTDDB法よりは短い時間でTDDB曲線
を得ることができる。
Then, the number of times of application until dielectric breakdown occurs,
Using the application time and the applied electric field strength, Chen-Hol
Based on the land-Hu model, the insulation layer breakdown life was obtained, and the Weibull distribution was applied to the obtained insulation layer breakdown life to obtain TDDB.
Calculating an insulating layer based on the calculated TDDB curve;
Evaluate the 12 dielectric breakdowns over time. Since the so-called acceleration test is performed and the TDDB curve is obtained by calculation by gradually increasing the applied voltage in this manner, the TDDB curve can be obtained in a shorter time than in the above-described conventional TDDB method.

【0008】[0008]

【発明が解決しようとする課題】しかしながら、従来の
評価方法にあっては、Chen −Holland−Hu モデルに
基づいて計算によってTDDB曲線を求めているため、
該モデルに適合しない絶縁破壊、特に初期不良領域が存
在する場合については正確なTDDB曲線が得られず、
評価の信頼性が低いという問題があった。本発明はかか
る事情に鑑みてなされたものであって、その目的とする
ところは印加する電圧を段階的に昇圧して絶縁破壊電界
を検出する操作を同じ半導体素子の絶縁層に対して複数
回行うことによって、いかなる場合でも短時間でTDD
B法と同程度に絶縁破壊を評価し得る絶縁層の評価方法
を提供することにある。
However, in the conventional evaluation method, the TDDB curve is obtained by calculation based on the Chen-Holland-Hu model.
An accurate TDDB curve cannot be obtained for a dielectric breakdown that does not fit the model, especially when there is an initial failure region,
There was a problem that the reliability of evaluation was low. The present invention has been made in view of such circumstances, and a purpose thereof is to perform an operation of detecting a dielectric breakdown electric field by stepwise increasing an applied voltage a plurality of times with respect to an insulating layer of the same semiconductor element. By doing so, in any case, TDD in a short time
An object of the present invention is to provide a method for evaluating an insulating layer, which can evaluate dielectric breakdown to the same degree as the method B.

【0009】[0009]

【課題を解決するための手段】本発明に係る絶縁層の評
価方法は、半導体基板に形成した複数の半導体素子に設
けてある絶縁層に印加する電圧を段階的に昇圧して絶縁
破壊電界強度を検出し、検出した絶縁破壊電界強度に基
づいて絶縁層を評価する方法において、複数の半導体素
子の絶縁層に対して前記絶縁破壊電界強度をそれぞれ検
出するステップと、検出した各絶縁破壊電界強度と予め
定めた閾値とをそれぞれ比較するステップと、前記半導
体素子の数に対する、絶縁破壊電界強度が閾値を越えた
半導体素子の数の比率を算出するステップとを備え、こ
れらの各ステップを複数回数繰り返し、算出した複数の
比率に基づいて絶縁層を評価することを特徴とする。
According to the method for evaluating an insulating layer according to the present invention , a voltage applied to an insulating layer provided on a plurality of semiconductor elements formed on a semiconductor substrate is stepwise increased to increase a breakdown field strength. A plurality of semiconductor elements in a method of detecting an insulation layer based on the detected breakdown electric field strength.
The breakdown electric field strength of each of the
And the detected breakdown electric field strength
Comparing each with a determined threshold value;
Breakdown electric field strength exceeds the threshold for the number of body elements
Calculating a ratio of the number of semiconductor elements.
Each of these steps is repeated multiple times,
It is characterized in that the insulating layer is evaluated based on the ratio .

【0010】[0010]

【0011】本発明にあっては、印加する電圧を段階的
に昇圧して絶縁破壊電界強度を検出する操作を、同じ半
導体素子の絶縁層に対して複数回行うことによって、絶
縁層に過大なストレスを反復して負荷する。これによっ
て、電圧を長時間印加した場合に絶縁破壊を生じさせる
ような僅かな歪み又は不均一な部分等が絶縁層に存在す
る場合、一度目の負荷では所定の絶縁破壊電界強度を有
していても、過大ストレスの反復負荷によって、それら
が欠陥にまで拡大され、絶縁破壊電界強度の急激な低下
として検出される。このように計算によってではなく実
測値に基づいて評価を行うため、いかなる場合であって
もTDDB法と同等の評価を短時間で行うことができ
る。
In the present invention, the operation of detecting the breakdown electric field strength by stepwise increasing the applied voltage is performed on the insulating layer of the same semiconductor element a plurality of times, so that an excessively large voltage is applied to the insulating layer. Apply stress repeatedly. As a result, when a slight distortion or non-uniform portion or the like that causes dielectric breakdown when a voltage is applied for a long time is present in the insulating layer, the first load has a predetermined dielectric breakdown electric field strength. However, due to the repetitive load of excessive stress, they are extended to defects and detected as a sharp decrease in the breakdown electric field strength. As described above, since the evaluation is performed not based on the calculation but on the basis of the actually measured value, the evaluation equivalent to the TDDB method can be performed in a short time in any case.

【0012】[0012]

【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて具体的に説明する。図1は本発明に係る評価
方法の実施に使用する装置の構成を示す模式図であり、
図中1は基板である。基板1上には絶縁層2,2,…及
び電極3,3,…を備える複数の半導体素子が所定パタ
ーンになるように形成してある。電極3には前後左右移
動自在に支持されているプローブ7の下端が接触してあ
り、プローブ7の移動は制御装置8によって制御される
ようになっている。
Embodiments of the present invention will be specifically described below with reference to the drawings. FIG. 1 is a schematic diagram showing a configuration of an apparatus used for performing an evaluation method according to the present invention.
In the figure, reference numeral 1 denotes a substrate. On the substrate 1, a plurality of semiconductor elements having insulating layers 2, 2,... And electrodes 3, 3,. The lower end of a probe 7 supported movably back and forth and left and right is in contact with the electrode 3, and the movement of the probe 7 is controlled by a control device 8.

【0013】プローブ7の上端は、印加電圧の大きさを
段階的に変化させ得る可変電源5の一端子に接続してあ
り、可変電源5の他端子は基板1に接続してある。この
可変電源5のオン・オフは制御装置8によって制御され
ている。また、可変電源5の印加電圧を測定する電圧計
6が並列接続してあり、プローブ7と可変電源5との間
には電流計4が介装してある。この電流計4及び電圧計
6の測定値は制御装置8に与えられる。
The upper end of the probe 7 is connected to one terminal of a variable power supply 5 capable of changing the magnitude of the applied voltage stepwise, and the other terminal of the variable power supply 5 is connected to the substrate 1. ON / OFF of the variable power supply 5 is controlled by the control device 8. A voltmeter 6 for measuring the applied voltage of the variable power supply 5 is connected in parallel, and an ammeter 4 is interposed between the probe 7 and the variable power supply 5. The measured values of the ammeter 4 and the voltmeter 6 are given to the control device 8.

【0014】図2は図1に示した制御装置8の要部構成
を示すブロック図である。図中82は前述したプローブ7
(図1参照)の移動を制御するプローブ制御部、83は絶
縁破壊電界強度を検出する検出部、84は可変電源のオン
・オフを制御する電源制御部であり、これらの動作は中
央制御部81によって制御されている。また、中央制御部
81には検出部83が検出した絶縁破壊電界強度を記憶する
第1メモリ85と、第1メモリ85に記憶された絶縁破壊電
界強度と予め設定された閾値電界強度とを比較して、絶
縁破壊電界強度が閾値電界強度以上であったものの割合
(良品率)を算出する算出部86と、算出部86が算出した
良品率を記憶する第2メモリ87とが接続してあり、中央
制御部81はこれらの動作も制御している。
FIG. 2 is a block diagram showing a main configuration of the control device 8 shown in FIG. In the figure, 82 is the probe 7 described above.
(See FIG. 1) A probe control unit that controls the movement of the probe, 83 is a detection unit that detects the breakdown electric field strength, and 84 is a power supply control unit that controls ON / OFF of the variable power supply. It is controlled by 81. Also, the central control unit
The first memory 85 stores the breakdown electric field strength detected by the detection unit 83, and compares the breakdown electric field strength stored in the first memory 85 with a preset threshold field strength. A calculating unit 86 for calculating the ratio (non-defective product ratio) of the electric field intensity being equal to or higher than the threshold electric field intensity and a second memory 87 for storing the non-defective product ratio calculated by the calculating unit 86 are connected. Also controls these actions.

【0015】プローブ制御部82には、所定のパターンに
形成された半導体素子の絶縁層2,2,…の内,絶縁破
壊電界強度を検出する半導体素子の部位及び検出順が設
定してあり、プローブ制御部82は、中央制御装置81から
の指令に従って、絶縁層2の絶縁破壊電界強度の検出が
終了すると次の絶縁層2の部位にプローブ7を移動し、
該絶縁層2上に形成された電極3に接触させる。プロー
ブ7が電極3に接触されると、電源制御部84は可変電源
5をオンし、電圧の低い側から高い側へ所定時間ずつ電
圧を印加させる。
In the probe control section 82, of the insulating layers 2, 2,... Of the semiconductor elements formed in a predetermined pattern, the portions of the semiconductor elements for detecting the breakdown electric field strength and the detection order are set. The probe control unit 82 moves the probe 7 to the next part of the insulating layer 2 when the detection of the breakdown electric field strength of the insulating layer 2 ends according to a command from the central control device 81,
It is brought into contact with the electrode 3 formed on the insulating layer 2. When the probe 7 comes into contact with the electrode 3, the power supply control unit 84 turns on the variable power supply 5 and applies a voltage from a low voltage side to a high voltage side for a predetermined time.

【0016】検出部83には絶縁層2,2,…の厚み及び
閾値電流が予め設定されており、検出部83は電流計4の
検出電流と閾値電流とを比較し、前者が後者を越えたと
き絶縁破壊が生じたと判断して、そのときの電圧計6の
検出電圧及び絶縁層2,2,…から絶縁破壊電界強度を
求め、それを第1メモリ85に記憶させる。また、検出部
83によって絶縁破壊が生じたと判断されると、電源制御
部84は可変電源5をオフにする。このような操作を所定
部位の絶縁層2,2,…全てに対して行う。そして、前
同様の操作を所定回数だけ繰り返す。
The thickness and the threshold current of the insulating layers 2, 2,... Are preset in the detection unit 83, and the detection unit 83 compares the detection current of the ammeter 4 with the threshold current, and the former exceeds the latter. Then, it is determined that a dielectric breakdown has occurred, and a dielectric breakdown electric field strength is obtained from the detected voltage of the voltmeter 6 and the insulating layers 2, 2,. Also, the detection unit
When it is determined by 83 that insulation breakdown has occurred, the power supply control unit 84 turns off the variable power supply 5. Such an operation is performed on all of the insulating layers 2, 2,. Then, the same operation as before is repeated a predetermined number of times.

【0017】算出部86は前述した操作が1回行われる都
度、第1メモリ85に記憶された各絶縁破壊電界強度と、
予め設定された閾値電界強度とを比較して良品率を算出
し、それを第2メモリ87に記憶させる。そして、出力部
88は第2メモリ87に記憶された複数の良品率をプリンタ
又はモニタ等に出力する。
Each time the above-described operation is performed once, the calculating unit 86 calculates the breakdown electric field strength stored in the first memory 85,
A non-defective rate is calculated by comparing the threshold electric field strength with a preset threshold field strength, and is stored in the second memory 87. And the output section
Reference numeral 88 outputs a plurality of non-defective ratios stored in the second memory 87 to a printer or a monitor.

【0018】図3は本発明に係る評価方法による絶縁層
の評価手順を示すフローチャートである。プローブ7を
所定の電極3に接触させ(ステップS1)、可変電源5
を作動させて電圧の印加を開始し(ステップS2)て、
絶縁層2に流れる電流の値を電流計4で検出する(ステ
ップS3)。所定時間だけ電圧を印加する間に検出され
た検出電流と予め設定した閾値電流,例えば1μAとを
比較し(ステップS4)、検出電流が閾値電流以下であ
れば、ステップS2に戻って一段高い電圧を印加する。
そして、検出電流が閾値電流を越えた場合、電圧の印加
を停止し(ステップS5)、そのときの電圧及び予め測
定した絶縁層2の厚みから絶縁破壊電界強度を求める
(ステップS6)。
FIG. 3 is a flowchart showing a procedure for evaluating an insulating layer by the evaluation method according to the present invention. The probe 7 is brought into contact with the predetermined electrode 3 (step S1), and the variable power source 5
To start applying voltage (step S2),
The value of the current flowing through the insulating layer 2 is detected by the ammeter 4 (step S3). The detected current detected during application of the voltage for a predetermined time is compared with a preset threshold current, for example, 1 μA (step S4). If the detected current is equal to or less than the threshold current, the process returns to step S2 to increase the voltage by one step. Is applied.
When the detected current exceeds the threshold current, the application of the voltage is stopped (step S5), and the breakdown electric field strength is obtained from the voltage at that time and the thickness of the insulating layer 2 measured in advance (step S6).

【0019】絶縁破壊電界強度が求まると、当該電極3
が検出対象の最後の絶縁層2に係る電極であるか否かを
判断し(ステップS7)、そうであると判断されるま
で、ステップS1〜ステップS7までの操作を繰り返
す。そして、評価対象である全ての絶縁層2について絶
縁破壊電界強度をそれぞれ求めると、各絶縁破壊電界強
度と閾値電界強度,例えば8MV/cmとを比較し(ス
テップS8)、良品率を算出し(ステップS9)、それ
を一次良品率とする。
When the breakdown electric field strength is determined, the electrode 3
Is determined to be the electrode relating to the last insulating layer 2 to be detected (step S7), and the operations from step S1 to step S7 are repeated until it is determined that this is the case. Then, when the breakdown electric field strengths are obtained for all the insulating layers 2 to be evaluated, each breakdown electric field strength is compared with a threshold electric field strength, for example, 8 MV / cm (step S8), and a non-defective rate is calculated (step S8). Step S9), and set it as the primary non-defective rate.

【0020】一次良品率の算出が終了すると、良品率の
算出を所定回数だけ行ったか否かを判断し(ステップS
10)、そうであると判断されるまでステップS1〜ステ
ップS10までの操作を繰り返し、それぞれ二次良品率,
三次良品率,…とする。そして、一次良品率,二次良品
率,…に基づいて絶縁層2を評価する(ステップS1
1)。このように、段階的に高い電圧を印加して絶縁破
壊電界を検出する操作を、同じ絶縁層2に対して複数回
行うことによって、絶縁層2に過大なストレスを反復し
て加え、電圧を長時間印加した場合に絶縁破壊を生じさ
せるような僅かな歪み又は不均一な部分等が絶縁層に存
在する場合、それらを欠陥にまで拡大して絶縁破壊とし
て検出する。従って、前述したTDDB法と同等の評価
を短時間で行うことができる。
When the calculation of the primary non-defective rate is completed, it is determined whether the non-defective rate has been calculated a predetermined number of times (step S).
10) Repeat steps S1 to S10 until it is determined to be so.
Tertiary non-defective rate, ... Then, the insulating layer 2 is evaluated based on the primary non-defective rate, the secondary non-defective rate,... (Step S1).
1). As described above, the operation of detecting a breakdown electric field by applying a high voltage stepwise is performed on the same insulating layer 2 a plurality of times, so that excessive stress is repeatedly applied to the insulating layer 2 and the voltage is increased. When a slight distortion or a non-uniform portion or the like that causes dielectric breakdown when applied for a long time is present in the insulating layer, these are expanded to defects and detected as dielectric breakdown. Therefore, the same evaluation as the TDDB method described above can be performed in a short time.

【0021】[0021]

【実施例】次に、比較試験を行った結果について説明す
る。図4は本発明方法による測定結果を示すグラフであ
り、図5は従来のTDDB法による測定結果を示すグラ
フである。試料には、チョクラルスキ(CZ)法によっ
て得たウェハの表面を、A〜Eの互いに異なる組成の溶
液で洗浄した後、600個のMOSキャパシタを形成し
たものと、対照として洗浄を行うことなく同数のMOS
キャパシタを形成したもの(F)を用いた。また、エピ
タキシャル(Epi)成長させたウェハの表面を、A組
成で洗浄した後に600個のMOSキャパシタを形成し
たもの、及び対照として洗浄を行うことなく同数のMO
Sキャパシタを形成したものも用いた。
Next, the results of a comparative test will be described. FIG. 4 is a graph showing a measurement result by the method of the present invention, and FIG. 5 is a graph showing a measurement result by the conventional TDDB method. In the sample, after cleaning the surface of the wafer obtained by the Czochralski (CZ) method with solutions having different compositions of A to E, 600 MOS capacitors were formed, and the same number of samples without cleaning was used as a control. MOS
The capacitor (F) was used. In addition, the surface of a wafer grown epitaxially (Epi) was cleaned with an A composition, and then 600 MOS capacitors were formed.
An S capacitor was also used.

【0022】図4に示した本発明方法にあっては、MO
Sキャパシタを200個ずつ3つのグループにわけ、各
グループに対して二次良品率まで検出しており、図中、
○は一次良品率を、また●は二次良品率をそれぞれ表し
ている。図5に示した従来のTDDB法にあっては、2
00個のMOSキャパシタについて11MV/cmとな
るように電圧を印加し、累積破壊率を対数時間に対して
プロットしてある。
In the method of the present invention shown in FIG.
The S capacitors were divided into three groups of 200 each, and the secondary non-defective rate was detected for each group.
○ indicates the primary non-defective rate, and ● indicates the secondary non-defective rate. In the conventional TDDB method shown in FIG.
Voltage is applied to the 00 MOS capacitors so as to be 11 MV / cm, and the cumulative destruction rate is plotted against logarithmic time.

【0023】図5から明らかな如く、従来のTDDB法
による評価結果は、CZウェハについてはE≒C≒D>
A>B>Fであり、EpiウェハについてはA<Fであ
った。また、ウェハの比較では、CZウェハ≪Epiウ
ェハであった。一方、図3から明らかな如く、本発明に
よる評価結果は、CZウェハについてはC≒D≒E>A
>B>Fであり、EpiウェハについてはA<Fであ
り、ウェハの比較では、CZウェハ≪Epiウェハであ
った。このように、本発明方法によってTDDB法と同
様な評価を行うことができることが分かる。
As is clear from FIG. 5, the evaluation result by the conventional TDDB method shows that ECC ≒ D> for the CZ wafer.
A>B> F, and A <F for the Epi wafer. In comparison of wafers, CZ wafer≪Epi wafer. On the other hand, as is clear from FIG. 3, the evaluation result according to the present invention indicates that C ≒ D ≒ E> A for the CZ wafer.
>B> F, and A <F for Epi wafers. In comparison of wafers, CZ wafer≪Epi wafer. Thus, it can be seen that the same evaluation as the TDDB method can be performed by the method of the present invention.

【0024】[0024]

【発明の効果】以上詳述した如く、本発明に係る絶縁層
の評価方法にあっては、TDDB法と同程度に詳細な評
価を短時間で行うことができ、また、計算モデルによら
ないため、絶縁層のいかなる不良をも正確に評価するこ
とができる等、本発明は優れた効果を奏する。
As described in detail above, in the method for evaluating an insulating layer according to the present invention, a detailed evaluation can be performed in a short time as well as the TDDB method, and a calculation model is not used. Therefore, the present invention has an excellent effect such that any defect of the insulating layer can be accurately evaluated.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る評価方法の実施に使用する装置の
構成を示す模式図である。
FIG. 1 is a schematic diagram showing a configuration of an apparatus used for performing an evaluation method according to the present invention.

【図2】図1に示した制御装置の要部構成を示すブロッ
ク図である。
FIG. 2 is a block diagram illustrating a main configuration of a control device illustrated in FIG. 1;

【図3】本発明に係る評価手順を示すフローチャートで
ある。
FIG. 3 is a flowchart showing an evaluation procedure according to the present invention.

【図4】本発明方法による測定結果を示すグラフであ
る。
FIG. 4 is a graph showing measurement results obtained by the method of the present invention.

【図5】従来のTDDB法による測定結果を示すグラフ
である。
FIG. 5 is a graph showing a measurement result by a conventional TDDB method.

【図6】従来の評価方法の実施に使用する装置の構成を
示すブロック図である。
FIG. 6 is a block diagram showing a configuration of an apparatus used for implementing a conventional evaluation method.

【符号の説明】[Explanation of symbols]

1 基板 2 絶縁層 3 電極 4 電流計 5 可変電源 7 プローブ DESCRIPTION OF SYMBOLS 1 Substrate 2 Insulating layer 3 Electrode 4 Ammeter 5 Variable power supply 7 Probe

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体基板に形成した複数の半導体素子
に設けてある絶縁層に印加する電圧を段階的に昇圧して
絶縁破壊電界強度を検出し、検出した絶縁破壊電界強度
に基づいて絶縁層を評価する方法において、複数の半導体素子の絶縁層に対して前記絶縁破壊電界強
度をそれぞれ検出するステップと、 検出した各絶縁破壊電界強度と予め定めた閾値とをそれ
ぞれ比較するステップと、 前記半導体素子の数に対する、絶縁破壊電界強度が閾値
を越えた半導体素子の数の比率を算出するステップと
備え、 これらの各ステップを複数回数繰り返し、算出した複数
の比率に基づいて絶縁層を評価する ことを特徴とする絶
縁層の評価方法。
A voltage applied to an insulating layer provided on a plurality of semiconductor elements formed on a semiconductor substrate is increased stepwise to detect a breakdown electric field strength, and based on the detected breakdown electric field strength, the insulating layer is provided. Evaluating the dielectric breakdown field strength against the insulating layers of a plurality of semiconductor elements.
Detecting degrees, respectively, and a predetermined threshold and the dielectric breakdown field intensity detected it
And a step of comparing the breakdown electric field strength with respect to the number of the semiconductor elements.
Calculating a ratio of the number of semiconductor elements beyond the the steps
Multiple comprising, where each of these steps a plurality of times repeatedly, calculated
A method for evaluating an insulating layer based on the ratio of the insulating layer .
JP34168595A 1995-12-27 1995-12-27 Evaluation method of insulation layer Expired - Fee Related JP3147758B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34168595A JP3147758B2 (en) 1995-12-27 1995-12-27 Evaluation method of insulation layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34168595A JP3147758B2 (en) 1995-12-27 1995-12-27 Evaluation method of insulation layer

Publications (2)

Publication Number Publication Date
JPH09178800A JPH09178800A (en) 1997-07-11
JP3147758B2 true JP3147758B2 (en) 2001-03-19

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Country Status (1)

Country Link
JP (1) JP3147758B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5020271B2 (en) * 2008-08-11 2012-09-05 三菱電機株式会社 Semiconductor test apparatus and semiconductor test method
KR101711477B1 (en) 2010-05-11 2017-03-14 삼성전자 주식회사 Time dependent dielectric breakdown (TDDB) test structure of semiconductor device and TDDB test method using the same
JP7412922B2 (en) * 2019-08-23 2024-01-15 デンカ株式会社 Method for evaluating withstand voltage characteristics of insulation materials and device for measuring withstand voltage characteristics
CN112946428A (en) * 2019-11-26 2021-06-11 杭州通产机械有限公司 Detection method
CN111812196B (en) * 2020-07-16 2023-03-21 浙江云联智能制造研究院有限公司 Gas pipe electric spark detection equipment with gas pipe insulating layer electric leakage
GB2616875B (en) * 2022-03-23 2025-03-19 Megger Instruments Ltd Measurement of Insulation Resistance of an Electrical Insulator

Also Published As

Publication number Publication date
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