JP3148399B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a gate array.

[0002]

2. Description of the Related Art A conventional full-element-forming gate array (S)
OG) is shown in FIG. Each basic cell 1 is a PMOS
The transistor 2 and the NMOS transistor 3 are configured to be adjacent to each other. A number of basic cells 1 are spread on a semiconductor substrate to form an SOG. The high power supply line VDD is arranged to pass over the PMOS transistor 2 of each basic cell 1, and the low power supply line VSS is arranged to pass over the NMOS transistor 3 of each basic cell 1. For this reason, even if a certain cell 5 is arranged at any of the arrangement places α and β, the pattern in the cell for connecting to the high power supply line VDD and the low power supply line VSS can be fixedly determined.

For example, as shown in FIG. 8, a two-input NAN having two input terminals A1 and A2 and one output terminal X is provided.
Let's look at the case where the D circuit 6 is arranged. 2-input NA
The ND circuit 6 has a PMO as shown in FIG.
S transistors 7, 8 and NMOS transistors 9, 10
It is composed of The drains of the PMOS transistors 7 and 8 are both connected to the output terminal X and the drain of the NMOS transistor 9. The source of the NMOS transistor 9 is connected to the drain of the NMOS transistor 10, and the source of the transistor 10 is connected to the low power supply line V
Connected to SS. Then, PMOS and NMOS gates of the transistors 7 and 9 input terminal A 2 becomes, PM
The gate of the OS and the NMOS transistor 8, 10 is an input terminal A 1.

Accordingly, the actual pattern of the two-input NAND circuit 6 is, as shown in FIG.
8 and the high power supply line VDD are connected by contact holes 11 and 12. NMOS transistor 10
And the low power supply line VSS are connected by a contact hole 13. The common drain of the PMOS transistors 7 and 8 and the wiring 14 in the cell are connected to the contact hole 1.
5, the drain of the NMOS transistor 9 and the wiring 14 in the cell are connected by a contact hole 16.

Therefore, in the conventional gate array shown in FIG. 10, if one actual pattern shown in FIG.
An ND circuit can be arranged.

[0006]

However, in the conventional gate array, a high power supply line VDD is provided above the basic cell 1.
And the low power supply line VSS. for that reason,
The wiring area above the placed cell becomes smaller,
There is a problem that the degree of freedom of the internal wiring of the cell is low.

In order to solve the above-mentioned problems, a full-element-forming gate array (SOG) 20 shown in FIG. 7 has recently been developed. Each basic cell 21 is a PMOS transistor 2
2 and the NMOS transistor 23 are arranged adjacent to each other. The high power supply lines VDD and the low power supply lines VSS are alternately arranged between the basic cells along the transistors 22 and 23 of the basic cell 21. Therefore, in this gate array 20, the power supply lines VDD, V
Since the SS does not pass above the basic cell 21, the wiring area above the arranged cell can be enlarged, and the degree of freedom of the internal wiring can be improved.

However, in the gate array 20, when a certain cell is arranged so as to sandwich the power supply line, the positional relationship between the cell, the high power supply line, and the low power supply line differs depending on the place where the cell is arranged. For this reason, there is a problem that the cells cannot be arranged with one actual pattern in which the information of the internal wiring and the contact hole is fixed for each cell as in the related art.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to allow cells to be freely arranged despite restrictions on power supply.

[0010]

According to a first aspect of the present invention, a basic cell in which a PMOS transistor and an NMOS transistor are arranged adjacent to each other is laid on a semiconductor substrate to form a high power supply line and a low power supply line. A method of manufacturing a semiconductor device in which a real pattern of a cell is arranged in a semiconductor device formed between each basic cell so that power supply lines alternately extend along both transistors of the basic cell. high power first connection line including the contact hole with the supply line, Ri Na <br/> from the second connection lines and internal wiring including the contact hole with the low power supply line, across a predetermined power supply line Te Line when placed in
A plurality of real patterns having a symmetric relationship are prepared. And
A predetermined actual pattern is arranged according to the positional relationship of the power supply determined by the arrangement location of each cell.

According to a second aspect of the present invention, a basic cell in which a PMOS transistor and an NMOS transistor are arranged adjacent to each other is spread over a semiconductor substrate, and a high power supply line and a low power supply line are alternately provided in both transistors of the basic cell. A semiconductor device formed between each of the basic cells so that the actual pattern of the cell is arranged along the basic cell, wherein the high power supply line and the low power supply line are previously set for each cell. One real pattern is prepared which extends to the third power supply line connected to the high power supply line, the fourth power supply line connected to the low power supply line, and the internal wiring. Then, after arranging a predetermined actual pattern at the location of each cell, a contact hole between the high power supply line and the third connection line and a contact hole between the low power supply line and the fourth connection line are arranged.

Further, according to a third aspect of the present invention, a basic cell comprising a PMOS transistor and an NMOS transistor adjacent to each other is spread over a semiconductor substrate, and a high power supply line and a low power supply line are alternately provided in both transistors of the basic cell. A method of manufacturing a semiconductor device in which the actual pattern of a cell is arranged in a semiconductor device formed between each of the basic cells so as to conform to the method described above, wherein a high power supply line to a low power supply line are previously set for each cell. One actual pattern is prepared, which is extended and includes fifth and sixth connection lines including contact holes for the high power supply line and the low power supply line, and the internal wiring. Then, after arranging a predetermined actual pattern at the location of each cell, a contact hole between the low power supply line and the fifth connection line, and a high power supply line and the sixth
The contact hole with the connection line was removed.

[0013]

[Action] In the first invention, the cell placement process, after position determination of a cell, depending on the positional relationship between the power determined by the location, a predetermined electrostatic you have more prepared for each cell
Line symmetrical relationship when placed across the power supply line
The cell layout is completed by selecting a suitable real pattern from among the real patterns and arranging it.

According to a second aspect of the present invention, in a cell placement process, after a placement position of a certain cell is determined, a corresponding actual pattern is placed, and a contact for connecting to a power supply line based on a positional relationship between the real pattern and a power source in the post-placement process. The cell layout is completed by generating holes.

In a third aspect of the present invention, in the cell placement process, after determining the placement position of a certain cell, a corresponding real pattern is placed, and unnecessary post-placement contact holes are deleted from the positional relationship between the real pattern and the power source in the post-placement process. Cell layout is completed.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the first invention will be described below with reference to FIGS.

FIG. 1 shows an actual pattern 30 when the two-input NAND circuit 6 shown in FIGS. The connection line 31 of the actual pattern 30 is connected to the source of each of the PMOS transistors 7 and 8 and the high power supply line VDD by contact holes 31a to 31c. The connection lines 32 are contact holes 32a, 3
2b is connected to the source of the NMOS transistor 10 and the low power supply line VSS. Also, wiring 3 in the cell
Reference numeral 3 is connected to the common drains of the PMOS transistors 7 and 8 and the drain of the NMOS transistor 9 through contact holes 33a and 33b.

In this embodiment, a plurality of actual patterns as shown in FIG. 1 are prepared for the two-input NAND circuit 6. FIG. 2 shows two 2-input NAND circuits 6 connected to a low power supply line V.
The example which arrange | positions so that SS is interposed is shown. In FIG. 2, the actual pattern 30 shown in FIG. 1 is arranged for a basic cell in which the low power supply line VSS is located above the basic cell. In addition, an actual pattern 34 is arranged for a basic cell in which the low power supply line VSS is located below the basic cell. Actual pattern 34 sandwiches low power supply line VSS
Thus, the relationship is line-symmetric with the actual pattern 30 .

As described above, in this embodiment, when each cell is previously arranged with a predetermined power supply line interposed therebetween, the line pair
A plurality of actual patterns having a relationship which is referred to as a name are prepared, and a predetermined actual pattern is arranged according to the cell arrangement location of the gate array 20. Therefore, the cells can be freely arranged even though the power supply is restricted.

Further, the gate array 20 of this embodiment uses the high power supply line VDD and the low power supply line VSS
They are alternately arranged between the basic cells along the two transistors 22 and 23. Therefore, the reduction of the wiring area above the basic cell is suppressed, so that the degree of freedom of the internal wiring in the actual pattern prepared for each cell can be improved.

(Second Embodiment) Next, a second embodiment of the second invention will be described with reference to FIGS. Note that the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

FIG. 3 shows an actual pattern 40 for arranging the two-input NAND circuit 6 shown in FIGS. Connection lines 41 and 4 of actual pattern 40
2 is a high power supply line VDD to a low power supply library V
It extends to SS. The connection line 41 is a contact hole 41
a and 41b are connected to the sources of the PMOS transistors 7 and 8, respectively. Connection line 42 is contact hole 4
2a is connected to the source of the NMOS transistor 10. The connection lines 41 and 42 and the high power supply line V
No contact hole is formed between DD and the low power supply line VSS.

In this embodiment, only one actual pattern 40 as shown in FIG. 3 is prepared for the two-input NAND circuit 6. FIG. 4 shows an example in which two two-input NAND circuits 6 are arranged so as to sandwich the low power supply line VSS. In FIG. 4, after arranging the actual pattern 40, a contact hole 43 is automatically generated as wiring information at the intersection of the high power supply line VDD and the connection line 41, and the intersection of the low power supply line VSS and the connection line 42. By automatically generating a contact hole 44 as wiring information in a part,
The cell can be arranged at the arrangement place.

As described above, in this embodiment, only one actual pattern needs to be prepared for each cell in advance, so that the number of actual patterns can be reduced and the number of steps required for creating the actual patterns can be reduced. Also in the present embodiment, the cells can be freely arranged even though the power supply is restricted.

Third Embodiment Next, a third embodiment of the present invention will be described with reference to FIGS. Note that the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

FIG. 5 shows an actual pattern 50 for arranging the two-input NAND circuit 6 shown in FIGS. Connection lines 51 and 5 of actual pattern 50
2 is a high power supply line VDD to a low power supply library V
It extends to SS. The connection line 51 is a contact hole 51
a, 51b are connected to the sources of the PMOS transistors 7, 8, and the connection line 51 is connected to the power supply line through contact holes 51c, 51d. The connection line 52 is connected to the NMO by the contact hole 52a.
The connection line 52 is connected to the power supply line via contact holes 52b and 52c, while being connected to the source of the S transistor 10.

In this embodiment, only one actual pattern 50 as shown in FIG. 5 is prepared for the two-input NAND circuit 6. FIG. 6 shows an example in which two two-input NAND circuits 6 are arranged so as to sandwich the low power supply line VSS. In FIG. 6, after arranging the actual pattern 50, the contact hole at the intersection of the low power supply line VSS and the connection line 51 is automatically deleted, and the high power supply line V
By automatically deleting the contact hole at the intersection of the SS and the connection line 52, the cell can be arranged at the arrangement location.

As described above, in this embodiment, only one actual pattern needs to be prepared for each cell in advance, so that the number of actual patterns can be reduced and the man-hour required for creating the actual patterns can be reduced. Also in the present embodiment, the cells can be freely arranged even though the power supply is restricted.

[0029]

As described in detail above, according to the present invention,
There is an excellent effect that the cells can be freely arranged despite the power supply restriction.

[Brief description of the drawings]

FIG. 1 is a layout diagram showing an actual pattern of a first embodiment.

FIG. 2 is a layout diagram using the actual pattern of FIG. 1;

FIG. 3 is a layout diagram showing an actual pattern according to a second embodiment.

FIG. 4 is a layout diagram using the actual pattern of FIG. 3;

FIG. 5 is a layout diagram showing an actual pattern according to a third embodiment.

FIG. 6 is a layout diagram using the actual pattern of FIG. 5;

FIG. 7 is a diagram showing a bulk configuration of a gate array used in the present invention.

FIG. 8 is a logic diagram showing a two-input NAND circuit.

FIG. 9 is a circuit diagram of the two-input NAND circuit of FIG. 8;

FIG. 10 is a bulk configuration diagram of a conventional gate array.

FIG. 11 is a layout diagram showing a conventional actual pattern.

[Explanation of symbols]

 21 Basic Cell 22 PMOS Transistor 23 NMOS Transistor 30, 40, 50 Actual Pattern 31, 32 Connection 33 Internal Wiring VDD High Power Supply Line VSS Low Power Supply Line

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/118 G06F 17/50 H01L 21/82

Claims (3)

(57) [Claims] 1. A basic cell in which a PMOS transistor and an NMOS transistor are arranged adjacent to each other is spread over a semiconductor substrate, and a high power supply line and a low power supply line are alternately arranged along both transistors of the basic cell. A method of manufacturing a semiconductor device, wherein an actual pattern of a cell is arranged in a semiconductor device formed between basic cells, comprising: a first connection including a contact hole with the high power supply line for each cell in advance. Line, the second connection line including the contact hole with the low power supply line, and the internal wiring.
Line pair when the power supply line is
A method of manufacturing a semiconductor device, comprising: preparing a plurality of actual patterns having a relationship that is referred to as a name, and arranging a predetermined actual pattern according to a positional relationship of a power supply determined by an arrangement location of each cell. 2. A basic cell in which a PMOS transistor and an NMOS transistor are arranged adjacent to each other is spread over a semiconductor substrate, and a high power supply line and a low power supply line are alternately arranged along both transistors of the basic cell. A method of manufacturing a semiconductor device in which a real pattern of a cell is arranged in a semiconductor device formed between basic cells, wherein the method previously extends from the high power supply line to the low power supply line for each cell, and One actual pattern including a third connection line connected to the high power supply line, a fourth connection line connected to the low power supply line, and internal wiring is prepared.
After arranging a predetermined actual pattern at the location of each cell, a contact hole between the high power supply line and the third connection line and a contact hole between the low power supply line and the fourth connection line are arranged. A method for manufacturing a semiconductor device, comprising: 3. A basic cell in which a PMOS transistor and an NMOS transistor are arranged adjacent to each other is spread over a semiconductor substrate, and a high power supply line and a low power supply line are alternately arranged along both transistors of the basic cell. A method of manufacturing a semiconductor device in which a real pattern of a cell is arranged in a semiconductor device formed between basic cells, wherein the method previously extends from the high power supply line to the low power supply line for each cell, and After preparing one real pattern including the fifth and sixth connection lines including the contact holes for the high power supply line and the low power supply line and the internal wiring, and arranging a predetermined actual pattern at the location of each cell And removing the contact hole between the low power supply line and the fifth connection line and the contact hole between the high power supply line and the sixth connection line. The method of manufacturing a semiconductor device characterized by the.