JP3149146B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device used for various digital data processing devices and the like, and more particularly, to a high integration density equivalent to a NAND type and a high speed by random access. And a small, high-speed nonvolatile semiconductor memory.

[0002]

2. Description of the Related Art A non-volatile semiconductor memory, which has been attracting attention as a substitute for a magnetic disk storage device or the like, has a floating gate via an electric insulating layer on a channel region between a source / drain region of a field effect transistor (FET). And a control gate are stacked, and a conductive / non-conductive state that can be changed according to the charged state of the floating gate is stored as 1-bit information. This nonvolatile semiconductor memory is
Various types are known depending on the method of changing the charged state of the floating gate. Typical ones are the erasing of electrical information using the FN tunnel phenomenon between the floating gate and the channel region. There is an EEPROM that enables writing.

In a nonvolatile semiconductor memory device having the above-mentioned EEPROM as a minimum unit of memory cell, a memory block is formed by arranging each memory cell two-dimensionally. With respect to such an arrangement of memory cells and a method of connecting them, NOR type and NAND type are known, but both have advantages and disadvantages. That is, the NOR type has the advantage of high speed because random access is possible, but has the disadvantage of low integration density. Conversely, the NAND type has the advantage of high integration density, but has the disadvantage of low speed because random access is not possible. The details of the configuration and operation of the above-mentioned NAND type nonvolatile semiconductor memory device are described in JP-A-1-133290 and JP-A-1-17 as needed.
See Japanese Patent Publication Nos. 3398 and 1-228873.

[0004]

As described above, NAN
D-type and NOR-type nonvolatile semiconductor memory devices have advantages and disadvantages in terms of integration density and high-speed operation. Accordingly, a main object of the present invention is to provide a novel nonvolatile semiconductor memory device having both high integration density equivalent to a NAND type and high speed associated with random access equivalent to a NOR type.

Further, in the conventional NAND type storage device, it is necessary to temporarily erase retained data and re-write data before erasure even for memory cells which do not need to be arranged and arranged near the bit line. In addition, since it is necessary to write simultaneously to all the memory cells sharing a word line, the same data must be rewritten for the memory cells that do not need to change the data being held.
For this reason, there is a problem that the number of times of erasing and writing is increased, the tunnel oxide film is deteriorated, and the reliability is reduced. Further, in the conventional NAND type storage device, the tunnel voltage is supplied from the bit line, so that the F voltage between the floating gate and the floating gate is low.
There is also a problem that N tunneling tends to occur more in the drain / source region than in the channel region, and the tunnel oxide film near the drain / source region is likely to deteriorate.
Therefore, another object of the present invention is to provide a nonvolatile semiconductor memory device having improved reliability by avoiding unnecessary erase and write operations.

[0006]

According to the nonvolatile semiconductor memory device of the present invention which solves the above-mentioned problems, a memory cell group is formed by arranging a plurality of nonvolatile memory cells in the row direction. By arranging a plurality of cell groups in the column direction, a memory block in which each memory cell is two-dimensionally arranged is formed, and the number of each memory block is appropriately arranged in the column direction. Each memory cell constituting the memory cell group in each memory block is connected in series with each other by sharing the source region with the drain region of one adjacent memory cell and sharing the drain region with the source region of the other adjacent memory cell. The memory cells at both ends are connected to the output line and one of the plurality of sub-bit lines, respectively. The first conductivity type semiconductor layer in which each memory cell group in each memory block is formed on the surface is extended in the row direction while being divided into a plurality in the column direction, and each of the plurality of main bit lines is provided with a plurality of main bit lines. Connected to one. The control gate of the memory cell in the same row between each memory cell group in each memory block is connected to one of a plurality of word lines extending in the column direction.

Further, by selecting a memory cell to be erased in each memory block by a combination of a main bit line and a word line, a selected memory cell located at an intersection of each line is tunneled with a channel region. Erasing means for changing the charged state of the floating gate; and a selected memory located at the intersection of each line by selecting a memory cell to be written in each memory block by a combination of one of the main bit lines and one of the word lines. Writing means for changing the charge state of the floating gate by tunneling between the cell and the channel region, and memory cells to be read in each memory block are selected by a combination of one of the sub-bit lines and one of the word lines. Reading means.

[0008]

First, memory cells constituting a memory cell group in each memory block are connected in series while sharing a source / drain region with an adjacent memory cell, and each of the memory cells at both ends is connected to an output line. Since the configuration for connecting to one of the plurality of sub-bit lines is substantially the same as that of the conventional NAND type, high integration density equivalent to that of the NAND type is realized. Further, by extending the first conductivity type semiconductor layer in the row direction while separating the semiconductor layer into a plurality in the column direction and connecting each to one of the plurality of main bit lines, each of the NAND structures in each memory block is provided. The potential of the channel region can be controlled by one of the main bit lines independently between the memory cell groups and commonly for all the memory cells in the same memory cell group. Further, for all the memory cells located in the same row in each memory cell group, the potential of the control gate can be commonly controlled by the word line.

Therefore, by selecting a memory cell to be erased by a combination of a main bit line and a word line,
One memory cell in each memory block located at the intersection of each line or a plurality of memory cells arranged in the extension direction of the main bit line or the word line is floated based on tunneling with the channel region. It is possible to change the charge state of the gate. In addition, by selecting one memory cell to be written in each memory block by a combination of one main bit line and one word line, one memory cell located at the intersection of each line is provided with a channel area. By changing the charged state of the floating gate based on the tunneling between 1 and 2, 1-byte parallel data is written into, for example, eight memory cells located in the same row and the same column in eight memory blocks. Further, by selecting one memory cell to be read in each memory block by a combination of one main bit line and one word line, the memory cells are located in the same row and the same column in, for example, eight memory blocks. One byte of parallel data is read from eight memory cells.

As described above, since the configuration of each memory cell group is the same as that of the conventional NAND type, the same high integration density is realized. Further, in addition to the sub-bit lines corresponding to the NAND-type bit lines, a main bit line for commonly controlling the potential of the channel region of all the memory cells belonging to each memory cell group is newly provided, so that the memory cell Erasing, writing and reading of the unit become possible. Hereinafter, the present invention will be described in more detail with reference to examples.

[0011]

FIG. 1 is an equivalent circuit diagram of a memory block constituting a nonvolatile semiconductor memory device according to one embodiment of the present invention.
In this memory block, nonvolatile memory cells M ₁₁ ,
M _12, M ₁₃ ··· M _1n memory cell group MG1 are formed by being arrayed in a row direction, a non-volatile memory cells _{M 21, M 22, M 23} ··· M 2n is the row direction A memory cell group MG1 is formed by arranging a plurality of the memory cells, and similarly, nonvolatile memory cells M _m1 , M _m2 , M _m3.
· M _mn memory cell group MGn is formed by being arrayed in a row direction. Such a plurality of memory cell groups MG1, MG2 ··· MGm memory cell M ₁₁ ~M _mn are two-dimensionally arranged memory blocks are formed by being arranged in the column direction.

Memory cell M belonging to memory cell group MG1
₁₁ , M ₁₂ , M ₁₃ ... M _1n are the semiconductor layers 1 of the first conductivity type.
A second conductivity type source and drain regions that are formed on one _first surface, a channel region formed between the source region and the drain region, are stacked while upward is interposed an insulating layer of the channel region It consists of a floating gate and a control gate. Each memory cell while being connected in series to each other by sharing the source region of one of the adjacent drain region of the memory cell and the share and the other a drain region of the adjacent memory cell source regions, one end of the memory cell M ₁₁ Is connected to the sub-bit line b1, and the source region of the memory cell _M1n at the other end is connected to the output line O1.
It has a general NAND structure connected to T. This is the same for all the other memory cell groups MG2 to MGm.

A feature of the present invention that is fundamentally different from the conventional nonvolatile semiconductor memory device based on the NAND structure is that the memory cells MG1, MG2,.
The first conductive type semiconductor layers 11 ₁ , 11 _2, ... 11 _m that form the respective MGm on the surface are extended in the row direction while being separated from each other in the column direction to form the main bit lines B1, B2.
.. Is connected to one of Bm, whereby the potentials are controlled independently of each other. The separation into these first conductivity type semiconductor layer 11 _1, 11 column direction of ₂ · · · 11 _m,
This is realized by inter-element insulating layers extending in the row direction parallel to each other while maintaining the same interval in the column direction, the details of which will be described later. Thus, the first conductive type semiconductor layers 11 ₁ , 11 ₂ ... 11 _m via the corresponding main bit lines.
Is independently controlled between the memory cell groups, and the potential of the channel region can be controlled independently of all the memory cells in the same memory cell group.

The memory cell groups MG1, MG2,.
The control gates of the memory cells in the same row belonging to the
, W2, W3,..., Wn. Further, in the nonvolatile semiconductor memory device of this embodiment, the memory cells to be written and erased are stored in the main bit lines B1, B2,.
.. by selecting a combination of Bm and word lines W1, W2... Wn and supplying an operating voltage thereto,
Means for selectively operating the memory cells arranged at the respective intersections, and setting the memory cells to be read as sub-bit lines b1, b2... Bm and word lines W1, W2.
means for selectively operating memory cells arranged at respective intersections by selecting the memory cells in accordance with n and supplying an operating voltage thereto.

The memory cells M _{11 to} M _mn in the memory block
Hold one bit (one bit) of parallel data of one word (8 bits) arranged in the extension direction of the word lines W1 to Wn. That is, as shown in FIG. 2, eight memory blocks MP1 to MP8 having the configuration shown in FIG. 1 are arranged in the extending direction of the word lines W1 to Wn, and the same word line in each of the memory blocks MB1 to MB8 is Each of eight memory cells arranged at intersections with the same main / sub bit line B · b, for example, memory blocks MB1 to MB8
Each of the memory cells M ₁₁ of the inner, parallel data of one byte is written at the same time, parallel data of one byte from each are read at the same time.

First, an erasing operation in units of memory cells of the semiconductor memory device of this embodiment will be described with reference to FIG.
However, in this embodiment, the erasing operation is an operation of accumulating electrons in the floating gate. It is assumed that the erase operation is performed only for the memory cell M _12. As shown in the figure, a positive potential of an appropriate magnitude, for example, a potential of +12 volts is set for the word line W2, and a ground potential (0 volt) is set for all other word lines. Also, an appropriate magnitude of negative potential, for example, -10 volts, is set for the main bit line B1, and the ground potential (0 V) is set for all other main bit lines B1 to Bm.
volt). Note that all the sub-bit lines b1 to bm are set to an open (high impedance) state. Word line W2
In the main bit line B1 is arranged at the intersection of the memory cell M ₁₂ (first conductive semiconductor layer 11 ₁₎ is
A channel region formed between the source and drain regions of a first conductivity type semiconductor layer 11 _first surface, the voltage of 22volt is applied between the control gate. Accordingly, a strong electric field that enables FN tunneling is generated between the channel region and the floating gate, electrons are transferred and accumulated from the channel region to the floating gate by FN tunneling, and the erase operation is completed.

The voltage applied between the control gate and the channel in all other unselected memory cells M ₁₁ , M _{13 to} M _1n in the memory cell group MG 1 to which the selected memory cell M ₁₂ at the time of erasing belongs. Is only 10 volts, so that electrons are not transferred from the channel region to the floating gate by FN tunneling, and thus the charged state of the floating gate does not change. Also, for all the other non-selected memory cells M ₂₂ ~M _{m @ 2} that share the selected memory cell M ₁₂ and the word line W2, the voltage applied between the control gate and the channel region 1
Since it is only 2 volts, electrons are not transferred from the channel region to the floating gate by FN tunneling, and the charged state of the floating gate does not change. The selected memory cell M ₁₂ at the time of erasing operation, calculates the electric field strength between the floating gate and the channel region for each of the non-selected memory cells M _11, M _22.

As shown in the equivalent circuit of FIG. 10, the potentials of the floating gate, control gate and channel are set in the same order as Vfg and Vcg.
, Vch, and the capacitance between the floating gate and the channel is C
1. The capacitance between the control gate and the floating gate is C2, and the charge amount of the floating gate is Q. For simplicity, C1 = C2 =
If C / 2, the potential Vfg of the floating gate is Vfg = 0.5 Vcg + 0.5 Vch + Q / C (1) Further, if the distance between the floating gate and the channel (the thickness of the tunnel oxide film) is Tt and the electric field strength between the floating gate and the channel is Et, then Et = (Vfg-Vch) / Tt = [0.5 (Vcg-Vch) + Q / C] / Tt (2)

Here, assuming that the threshold voltage of each memory cell in the written state (set to "1") is Vt, Vt = Q / C2 = 2Q / C (3) From the equations (2) and (3), Et = 0.5 [(Vcg−Vch) + Vt] / Tt (4) Here, -2Volt the Vt, when the Tt and 10nm, 22volt for the selected memory cell M ₁₂ as Vcg-Vch, the non-selected memory cell M ₁₁ is 10vol
t, Substituting 12volt for non-selected memory cells M _22, Et in the same order, 10MV / cm, 4MV / cm , 5MV / cm
Next, it is possible to cause the FN tunneling only for the selected memory cell M _12.

Although the erasing operation in units of memory cells has been described above, by simultaneously selecting one of the main bit lines and all the word lines, the erasing operation is performed simultaneously on all the memory cells in the corresponding memory selection group. You can also. Further, by simultaneously selecting one of the word lines and all the main bit lines, the erasing operation can be performed simultaneously for all the memory cells in the same row of each memory cell group.

Next, a write operation of the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIG. However, writing a binary signal “1” is an operation of removing electrons by moving electrons from the floating gate to the channel region by FN tunneling. Writing a binary signal “0” is the same as the above-described case of erasing. Similarly, the operation is to inject electrons into the floating gate. It is assumed that writing a "1" only in the memory cell M _12. As shown in FIG. 3, a negative potential of an appropriate magnitude, for example, -9 volt is set for the word line W2, and the ground potential (0 volt) is set for all other word lines.
In addition, an appropriate magnitude of positive potential, for example, +9 volts, is set for the main bit line B1, and a ground potential (0 volt) is set for all other main bit lines. Note that the sub-bit line b
1 to bm are all kept open (high impedance).
Memory cells M ₁₂ arranged at intersections between word lines W2 and main bit lines B1 (first conductive type semiconductor layer 11 ₁ ).
In this case, a strong electric field is generated between the channel region formed between the source and the drain and the floating gate, and electrons are moved and removed from the floating gate to the channel region by FN tunneling, and the "1" write operation is performed. Is completed.

[0022] The selected memory cell M _12, for each of the non-selected memory cells M _11, M _22, if calculated field strength Et on the basis of the above equation (4), in the same order, 10 MV / cm, 5.
5MV / cm, 5.5MV / cm, and the only for the selected memory cell M _11, it is possible to cause the movement and removal of electrons from the floating gate by FN tunneling. The writing of "0" into the selected memory cell M ₁₂ may be carried out in the same erase operation described in FIG. As in the case of the erasing operation, by simultaneously selecting one of the main bit lines and all the word lines, the writing operation can be simultaneously performed on all the memory cells in the corresponding memory selection group. Also, by simultaneously selecting one of the word lines and all the main bit lines, the write operation can be performed simultaneously on all the memory cells in the same row of each memory cell group.

Next, a read operation of the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIG. Assume a case of reading one bit of data in held in the memory cell M _12. As shown in the figure, a ground potential is set for the word line W2, and a positive potential of an appropriate magnitude, for example, +5 volt is set for all other word lines. In addition, an appropriate magnitude of positive potential, for example, +5 volt, is set for the sub-bit line b1, and the ground potential (0 vo) is set for all other sub-bit lines.
lt). The ground potential is set for all the main bit lines B1 to Bm.

[0024] The word line W2 and the sub-bit line b1 selection are arranged at the intersection of the memory cell M ₁₂ (first conductive semiconductor layer 11 _1), the binary signal being held at "1" If there is, that is, unless electrons are being accumulated in the floating gate, conduction between the source and the drain is established. The selection if the binary signal being held in the memory cell M ₁₂ is "0", ie electrons in the floating gate between the source and the drain as long as during the accumulation becomes nonconductive. Incidentally, all of the other memory cells M _11, M ₁₃ ~M _1n in the memory cell group MG1 which the selected memory cell M ₁₂ belongs, between the control gate and the channel region +
Since a voltage of 5 volts is applied, all conduction is performed regardless of the charged state of the floating gate. Change in current due to the conduction / non-conduction of the selected memory cell M ₁₂ is read via the output line OT and the sense amplifier SA.

As shown in FIG. 2, the 8 of the configuration shown in FIG.
Memory blocks MP1 to MP8 are connected to word lines W1 to W
n, the memory cells to be written / read are selected one by one for each memory block, so that eight memory cells occupying the same position in each memory block have one byte. Parallel data is simultaneously written, and one byte of parallel data is simultaneously read from these eight memory cells.

FIG. 6 is a plan view of a memory block constituting the nonvolatile semiconductor memory device of the present embodiment shown in FIG. 1 as an equivalent circuit. FIG. 7 is a sectional view taken along the line AA 'of FIG. FIG. 7 is a sectional view taken along the line BB ′ of FIG. First, referring to the plan view of FIG. 6, in this nonvolatile semiconductor memory device, m memory cell groups MG1, MG2,..., MGm each composed of n nonvolatile memory cells arranged in the row direction are provided. , M in the column direction
Memory cells M ₁₁ ~M _mn are two-dimensionally arranged memory block is formed by being number sequence.

The memory cell groups MG1, MG2,.
Are the memory cells M ₂₁ , M ₂₂ , M ₂₃ ... Of the memory cell group MG2.
M _2n , as shown in the cross-sectional view of FIG. 7, a source region including a so-called n ⁺ -type diffusion layer 13 is shared with a drain region of one adjacent memory cell, and the n ⁺ -type diffusion layer 13 Are connected in series by sharing the drain region with the source region of the other adjacent memory cell. Drain region of one end of the memory cell M ₂₁ is embedded through the tungsten plug 16 is connected to a corresponding sub-bit line b2, the memory cell source regions of the memory cell M _2n of the other end through a buried tungsten plug 17 It is connected to an output line OT common to the groups.

Further, referring to FIG. 7, a first gate oxide film having a thickness of about 10 nm called a tunnel oxide film is formed above the source region and the drain region of each memory cell. An about 150 nm-thick floating gate FG made of an n ⁺ -doped polycrystalline silicon layer is formed thereon. Further, on the floating gate FG, a second gate insulating film having a stacked structure of a silicon oxide film / silicon nitride film / silicon oxide film (an oxide film equivalent thickness of about 20 nm) is formed. ⁺ About 300 type doped
control gate CG made of a polycrystalline silicon layer having a thickness of 10 nm
Are formed. Thus, each memory cell has an n-channel floating gate type EEPROM structure.

As best shown in the cross-sectional view of FIG. 8, the p-type silicon layers 11 ₁ , 11 ₂ ,... Forming the respective memory cell groups MG1, MG2,.
11 _m is separated by element isolation insulating layers 12 ₁ , 12 _2, ..., 12 _{m + 1 that} are equally spaced in the column direction and extend in the row direction in parallel with each other on the n-type high-resistance silicon substrate 10. Are extended in the row direction while being separated from each other in the column direction. p-type silicon layers 11 ₁ , 11 ₂ ... 11 _m
Each, p-type silicon layer 11 ₂ in a representative as shown in FIG. 6, p ⁺ B1 type contact layer 14 and the buried tungsten plug 15 via the main bit line, B2
.. Bm, the potentials can be controlled independently of each other via corresponding bit lines.

Referring to FIG. 7, an n ⁺ type diffusion layer 13 forming a source region of a memory cell M _2n located at one end of a memory cell group connected in series, and a p ⁺ type contact layer 14
Between them, a shield gate 18 for shielding both is formed. This shield gate 18 has a structure in which the floating gate FG and the control gate CG are short-circuited and the potential of this gate is fixed to a reference potential. Shield gate 19 of similar structure to form a drain region of the memory cell M ₂₁ located at the other end of the memory cell group n
It is also formed outside the ⁺ type diffusion layer 13. Furthermore, as shown in FIG. 7 as a representative word line W3, the memory cell group MG1, MG2 memory cell M ₁₃ is the memory cell (word line W3 located in the same row in each of · · · MGm, M _23, M control gate CG of the _{33 ····} M _m3)
Are connected to one of a plurality of word lines that are separated from each other in the row direction and extend in the column direction.

As described above, one feature of the present invention resides in that the first conductivity type semiconductor layer forming the memory cell group corresponding to the conventional NAND structure on the surface is formed separately in the column direction. . The method of forming the first conductivity type silicon layer separated in the column direction may be any other appropriate method. For example, as shown in the cross-sectional view of FIG. 9, after forming a first conductivity type silicon layer on the buried oxide film 12a,
The element isolation insulating film 12 has a depth reaching the buried oxide film.
_An SOI structure that forms _{1 to} 12 _m may be used.

[0032]

As described above in detail, according to the nonvolatile semiconductor memory device of the present invention, a memory cell group having substantially the same configuration as that of the conventional NAND type is separated so that the potential can be individually controlled. Since the structure is formed on the semiconductor layer of the first conductivity type, the NO.
The same random access as that of the R type can be performed, and the effect of realizing both high integration and high speed can be achieved.

Further, in the nonvolatile semiconductor device of the present invention,
Since the tunneling between the floating gate and the floating gate is performed from the wide channel region, the tunneling is not localized in the drain / source region and the tunnel oxide film is not deteriorated as in the conventional NAND type. The effect of prolonging the life is also achieved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a memory block constituting a nonvolatile semiconductor memory device according to an embodiment of the present invention by an equivalent circuit.

FIG. 2 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to an embodiment of the present invention, which is configured by arranging eight memory blocks in FIG. 1 in a word line direction.

FIG. 3 is an equivalent circuit diagram for explaining an erasing operation of the nonvolatile semiconductor memory device of the embodiment.

FIG. 4 is an equivalent circuit diagram for explaining a write operation of the nonvolatile semiconductor memory device of the embodiment.

FIG. 5 is an equivalent circuit diagram for explaining a read operation of the nonvolatile semiconductor memory device according to the embodiment.

FIG. 6 is a plan view showing a configuration of a main part of a memory block shown by an equivalent circuit in FIG. 1;

FIG. 7 is a sectional view taken along the line A-A 'of FIG.

8 is a sectional view taken along the line B-B 'of FIG.

FIG. 9 is a cross-sectional view showing an example of another configuration of the memory block shown in FIGS. 6 to 8;

FIG. 10 is an equivalent circuit diagram of a stacked structure of a floating gate and a control gate formed on a channel of each memory cell.

[Explanation of symbols]

MG1 ～MGm memory cell group M ₁₁ ~Mmn memory cell 11 ₁ to 11 _m first conductive type semiconductor layer B1~Bm main bit line b1~bm sub bit lines W ₁ wn word line OT output lines SA the sense amplifier MB1 ~ MB8 memory block

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁷ identification code FI H01L 29/792 (58) Investigated field (Int.Cl. ⁷ , DB name) H01L 21/8247 G11C 16/04 G11C 16/06 H01L 27/115 H01L 29/788 H01L 29/792

Claims (4)

(57) [Claims] A source region and a drain region of a second conductivity type are formed on a surface of a semiconductor layer of a first conductivity type; and a channel region is formed between the source and drain regions. The floating gate and control gate are formed with an insulating layer interposed above
Non-volatile memory cells that hold 1-bit information according to the state of charge of the floating gate are formed, and a plurality of memory cells are arranged in a row direction to form a memory cell group. A plurality of memory blocks are arranged in the same direction to form a memory block in which each of the memory cells is two-dimensionally arranged. Further, a predetermined number of each memory block are arranged in the column direction to form the same row in each memory block. A nonvolatile semiconductor memory device in which parallel data of a predetermined number of bits simultaneously read / written by memory cells positioned at the intersection of the same column is held, and constitutes each memory cell group in each memory block. Each memory cell shares the source region with the drain region of one adjacent memory cell and shares the drain region of the other adjacent memory cell. The memory cells at both ends are connected to an output line and one of a plurality of sub-bit lines, respectively, and are connected to each other in series by sharing with the source region, and each memory cell group in each memory block is formed on the surface. The semiconductor layer of the first conductivity type is extended in the row direction while being separated in the column direction and connected to one of the plurality of main bit lines, in each of the memory cell groups in each of the memory blocks. The control gate of each memory cell in the same row is connected to one of a plurality of word lines extending in the column direction, and a memory cell to be erased in each memory block is connected to the main bit line and the word. Erasing means for controlling the state of charge of the floating gate by tunneling between the channel region and a selected memory cell located at the intersection of each line by selecting by a combination with a line; By selecting a memory cell to be written in each of the memory blocks by a combination of one of the main bit lines and one of the word lines, a selected memory cell located at an intersection of each line is connected to the channel region. Writing means for controlling the charging state of the floating gate by tunneling; and reading means for selecting a memory cell to be read in each of the memory blocks by a combination of one of the sub-bit lines and one of the word lines. A nonvolatile semiconductor memory device. 2. The non-volatile memory according to claim 1, wherein a main bit line and a word line connected to the memory cell selected by the erasing means are supplied with substantially equal potentials of opposite polarities. Semiconductor storage device. 3. The non-volatile memory according to claim 1, wherein a main bit line and a word line connected to the memory cell selected by said writing means are supplied with substantially equal potentials of opposite polarities of absolute values. Semiconductor memory device. 4. The nonvolatile semiconductor memory device according to claim 1, wherein a ground potential is applied to one of a sub-bit line and a word line connected to the memory cell selected by the read means.