JP3149231B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and, more particularly, to a technology effective when applied to a semiconductor device having a capacitance element.

[0002]

2. Description of the Related Art Semiconductor devices, in particular, MISFETs for selection
DRAM which connects the capacitive element in series with the (D ynamic R
In a semiconductor device having a andom A ccess M emory) memory cells, in order to improve the integration degree, the size of the memory cells have been reduced small. Accordingly, the size of the capacitive element has been reduced. However, for example, in order to maintain the reliability against soft errors due to α-rays, the amount of charge stored in the capacitor cannot be reduced to a predetermined value or less.
Therefore, in order to reduce the size of the memory cell and improve the reliability against soft errors, a capacitor having a stacked structure is used.

[0003] The capacitive element is composed of a lower electrode and an upper electrode provided on the lower electrode via a charge storage insulating film. The lower electrode is made of, for example, a polycrystalline silicon film. This lower electrode is connected to the source or drain region of the selection MISFET. The charge storage insulating film is made of, for example, a silicon oxide film formed by thermally oxidizing a polycrystalline silicon film constituting the lower electrode. Alternatively, a silicon nitride film formed on the polycrystalline silicon film, and a stacked film including a silicon oxide film formed on the silicon nitride film by thermally oxidizing the silicon nitride film. I have. The upper electrode is made of, for example, a polycrystalline silicon film.

However, in order to further reduce the size of the memory cell, for example, the dielectric constant of the charge storage insulating film is increased, the amount of stored charge per unit area is increased, and the size of the capacitor is reduced. There is a need to. Therefore, instead of the silicon oxide film and the silicon nitride film, a metal oxide film having a higher dielectric constant than the silicon oxide film and the silicon nitride film, for example, a tantalum oxide (Ta ₂ O ₅ ) film is used as a charge storage insulating film. Has been proposed.

The tantalum oxide film is formed by, for example, a CVD method. For this type of technology, see, for example, IEE, Symposium on VSI Technology (1990), pages 13 to 1.
Page 4 (IEEE, Symposiumon VLSI Technolog
y (1990) pp. 13-14).

The tantalum oxide film is formed, for example, by forming a tantalum film by an electron beam evaporation method or a high-frequency sputtering method, and then oxidizing the tantalum film. For this type of technology, for example,
American Institute of Physics, Journal of Applied Physics, 5
4, 11 (1983) pp. 6502-6508 (American Institute of Physics, Journal of
Applied Physics, 54 (11) (1983) pp65
02-6508).

However, in the method of forming a tantalum oxide film by thermal oxidation after forming a tantalum film by the above-mentioned electron beam evaporation method or high frequency sputtering method, irregularities are formed on the surface when the tantalum film is formed. The thickness of the tantalum oxide film formed by oxidation varies. If the film thickness varies, the withstand voltage of the tantalum oxide film is reduced, which causes a problem that the reliability of the semiconductor device is reduced.

[0008] Therefore, there has been proposed a method of performing reoxidation after forming a tantalum oxide film by a reactive sputtering method. By performing re-oxidation, in a region where the thickness of the tantalum oxide film is small, silicon underlying the tantalum oxide film is thermally oxidized to form a silicon oxide film. According to this method, the withstand voltage of the thin portion of the tantalum oxide film is improved by the silicon oxide film formed in the reoxidation step, so that the withstand voltage of the charge storage insulating film can be improved. . Thereby, the reliability of the semiconductor device can be improved. Regarding this kind of technology, for example, the Japan Society of Applied Physics, Applied Physics, 58, 11 (1989),
It is described on pages 22 to 1628.

[0009]

However, the present inventor has found the following problems as a result of studying the above prior art.

When a tantalum oxide film is formed by a CVD method, underlying silicon (polycrystalline silicon film) reacts with the tantalum oxide to reduce the tantalum oxide. In order to prevent the reduction reaction of tantalum oxide by silicon, a tantalum oxide film must be formed on the silicon oxide film after forming a silicon oxide film on the underlying silicon. Therefore, the charge storage insulating film is composed of a stacked film of a silicon oxide film and a tantalum oxide film.

In the case where a tantalum oxide film is formed by thermal oxidation after a tantalum film is formed by the electron beam evaporation method or the high frequency sputtering method, the tantalum oxide film is formed in a thermal oxidation step for forming the tantalum oxide film. A silicon oxide film is formed at the interface between the silicon and the underlying silicon. Therefore,
The charge storage insulating film is composed of a laminated film of a silicon oxide film and a tantalum oxide film.

Also, in the method of forming a tantalum oxide film by the reactive sputtering method and reoxidizing the same, the charge storage insulating film is similarly formed of a laminated film of a silicon oxide film and a tantalum oxide.

As described above, when a tantalum oxide film is formed on silicon by a CVD method, an electron beam evaporation method, or a sputtering method, the charge storage insulating film is formed of a laminated film of a silicon oxide film and a tantalum oxide film. Therefore, there is a problem that the dielectric constant of the charge storage insulating film is lower than the dielectric constant of the single-layered tantalum oxide film.

An object of the present invention is to provide a technique capable of achieving high integration in a method of manufacturing a semiconductor device having a capacitor.

Another object of the present invention is to provide a technique capable of improving reliability in the method of manufacturing a semiconductor device.

It is another object of the present invention to provide a technique capable of forming a high dielectric constant charge storage insulating film in the method of manufacturing a semiconductor device.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0018]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) In a method of manufacturing a semiconductor device having a capacitive element having an upper electrode provided on a lower electrode provided on a substrate via a charge storage insulating film, a step of forming a silicon film and the silicon film Forming a metal film made of at least two kinds of metals having different oxidation conditions, selectively oxidizing a first metal of the at least two kinds of metals, and forming a surface of a second metal that is not oxidized; Or forming an oxide film of the first metal on the surface of the metal film to form an insulating film for charge storage, and forming a lower electrode of the silicon film and the second metal film or the metal film; Forming an upper electrode on the insulating film.

(2) After the formation of the metal film, a step of depositing an oxide film of the first metal on the metal film to form a charge storage insulating film; Oxidizing.

(3) After forming an oxidation resistant film on the silicon film, the metal film is formed.

(4) In a method of manufacturing a semiconductor device having a capacitor in which a second electrode is provided on a first electrode via a charge storage insulating film, at least two kinds of metals having different oxidation conditions are used. Forming a first electrode with a metal film, forming an oxide film of a first metal on the metal film to form a charge storage insulating film, and oxidizing the first metal oxide film. And a second step on the charge storage insulating film.
Forming an electrode.

(5) The atmosphere for selectively oxidizing the first metal is a mixed gas of hydrogen and water vapor.

(6) The first metal is a group IVa or Va
Any one or a combination of two or more group elements;
The second metal is Mo or W or Mo and W.

(7) The oxidation resistant film is made of TiN, Ti-W
Alloy, TiSi ₂ , NiSi, or CoSi ₂ .

[0026]

According to the above-mentioned means (1), (5) or (6), the first metal (one or a combination of two or more elements of the group IVa or Va) and the second metal (Mo or Mo) are used. W or a metal film composed of Mo and W).
Is formed, the second metal underlying the first metal oxide film functions as a barrier layer, so that the silicon constituting the lower electrode and the first metal oxide film No reduction reaction occurs between the two. Therefore, since it is not necessary to form a silicon oxide film on a metal film made of two kinds of metals, the charge storage insulating film can be formed with a single-layer film of the first metal oxide film.

Since silicon does not exist at the interface between the metal film composed of the two kinds of metals and the oxide film of the first metal, silicon oxide is formed at the interface between the oxide film of the first metal and the metal film. No film is formed. Therefore, the charge storage insulating film can be formed of a single-layer film of the first metal oxide film.

When the first metal is selectively oxidized, an oxide of the first metal is deposited on the surface of the metal film composed of two kinds of metals. This deposited first metal oxide film stops growing at a constant film thickness. This phenomenon is considered to be a kind of grain boundary segregation. Therefore, even if the metal film is sufficiently oxidized, only the oxide film of the first metal is selectively formed.

As described above, since the charge storage insulating film can be formed of a single-layer film of the first metal oxide film, the single-layer film of the silicon oxide film or the silicon oxide film and the first metal oxide film can be formed. The dielectric constant is higher than in the case where the charge storage insulating film is formed of a stacked film with an oxide film. Thereby, in the method of manufacturing a semiconductor device, a dielectric film having a high dielectric constant can be formed. Further, since the amount of charge stored per unit area of the charge storage insulating film increases, the size of the capacitor can be reduced, and high integration of the semiconductor device can be achieved.

According to the means (2) described above, even if the thickness of the oxide film of the first metal deposited on the metal film composed of two kinds of metals varies, the oxidation can be performed by performing the oxidation. In a region (weak spot) where the thickness of the first metal oxide film is small, the first metal oxide film in the underlying metal film is deposited on the surface of the metal film. Due to the first metal oxide film formed by the oxidation, the thickness of the first metal oxide film in the thin region is increased. Further, the growth of the first metal oxide film deposited on the surface of the metal film stops at a constant film thickness. Therefore, the oxide film of the first metal formed on the metal film can be sufficiently oxidized, and variation in the thickness of the oxide film of the first metal can be reduced. Accordingly, the withstand voltage of the charge storage insulating film is improved, so that the reliability of the semiconductor device can be improved.

According to the above means (3) or (7), the lower electrode is formed in the step of oxidizing the metal film made of two kinds of metals or in the step of oxidizing the oxide film of the first metal. The oxidation of silicon can be prevented, and the reaction between the metal film and silicon can be prevented.

According to the means (4) described above, similarly to the means (1), the charge storage insulating film can be formed of a single-layer film of the first metal oxide film. The dielectric constant is higher than when a charge storage insulating film is formed of a single-layer film of a film or a stacked film of a silicon oxide film and a first metal oxide film. Thereby, in the method of manufacturing a semiconductor device, a dielectric film having a high dielectric constant can be formed. Further, since the amount of charge stored per unit area of the charge storage insulating film increases, the size of the capacitor can be reduced, and high integration of the semiconductor device can be achieved.

As in the case of the above-mentioned means (2), even if the thickness of the first metal oxide film deposited on the metal film composed of two kinds of metals varies, the oxidation is performed by performing the oxidation. In the region where the thickness of the first metal oxide film is small,
The first metal in the underlying metal film is selectively oxidized to form the first metal.
Is formed. The thickness of the first metal oxide film in the thin region is increased by the first metal oxide film formed by the oxidation, so that the variation in the thickness of the first metal oxide film is reduced. can do. Accordingly, the withstand voltage of the charge storage insulating film is improved, so that the reliability of the semiconductor device can be improved.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be specifically described below with reference to the drawings.

In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.

Embodiment 1 A semiconductor device according to Embodiment 1 of the present invention will be described with reference to FIG.

As shown in FIG. 1, the semiconductor device according to the first embodiment is a DRAM having a memory cell in which a selection MISFET Qs and a capacitive element C having a stacked structure are connected in series.

The semiconductor device comprises a p-type semiconductor substrate 1. This p − type semiconductor substrate 1 is, for example,
It is made of single crystal silicon. This p-type semiconductor substrate 1
Is provided with ap − type well region 2.
An element isolation insulating film 4 is provided on the main surface of the non-active region of the p − -type well region 2. A p + type semiconductor region 3 constituting a channel stopper region is provided below the element isolation insulating film 4. Between each element,
Mainly, the isolation is performed by the isolation region composed of the element isolation insulating film 4 and the p + type semiconductor region 3.

The selection MISFET Qs is connected to the p-
It is provided on the main surface of the active region of the mold well region 2.
The selection MISFET Qs mainly includes a gate insulating film 5, a gate electrode 6, and a pair of n-type semiconductor regions 7.

The gate insulating film 5 is provided on the main surface of the p − type well region 2. This gate insulating film 5
Is composed of, for example, a silicon oxide film.

The gate electrode 6 is formed on the gate insulating film 5
It is provided above. This gate electrode 6 is made of, for example, a polycrystalline silicon film. An insulating film 9 is provided on the gate electrode 6. This insulating film 9 is made of, for example, a silicon oxide film. A sidewall spacer 10 is provided on the side wall of the gate electrode 6. The sidewall spacer 10 is made of, for example, a silicon oxide film.

The pair of n-type semiconductor regions 7 is formed by
The main surface of the mold well region 2 is provided on the side of the gate electrode 6. This pair of n-type semiconductor regions 7
Constitute a source region and a drain region.

The capacitive element C comprises a lower electrode 13, a charge storage insulating film 14 on the lower electrode 13, and an upper electrode 15 provided thereon. The capacitance element C is provided in a region including the portion above the gate electrode 6 of the selection MISFET Qs.

The lower electrode 13 is provided with the selection MISF.
It is connected to one of a pair of n-type semiconductor regions 7 of ETQs. The lower electrode 13 is composed of, for example, a laminated film in which a polycrystalline silicon film 11 and a tungsten film containing tantalum (hereinafter, referred to as a tantalum-tungsten film) 12 are laminated from the lower layer side. In the present invention, this metal film
Any metal film made of a group IVa element and a Va group element may be used. In the first embodiment, a metal film made of tantalum and tungsten will be described as an example. The tantalum content of the tantalum-tungsten film 12 is, for example, about 50 atm%. This tantalum-tungsten film 12 is formed by, for example, a sputtering method using an alloy target.
The thickness of the tantalum / tungsten film 12 is, for example,
It is about 500 nm. Note that tantalum and tungsten constituting the tantalum-tungsten film 12 are not compounds but mixtures, and the composition ratio is not particularly limited.

The charge storage insulating film 14 is made of, for example, a tantalum oxide film. The dielectric constant of the tantalum oxide film is about six times that of the silicon oxide film, and is larger than that of the silicon oxide film, the silicon nitride film, or a stacked film thereof. For example, the thickness of the silicon oxide film forming the conventional charge storage insulating film is 2
In the case of about 3 nm, the charge storage insulating film 14 of this embodiment is used.
May have a thickness of about 18 to 24 nm. Further, by reducing the thickness of the charge storage insulating film 14, the amount of stored charge per unit area of the capacitor C is increased. Therefore, the size of the capacitor for securing the same charge accumulation amount can be reduced, so that high integration of the semiconductor device can be achieved.

The upper electrode 15 is made of, for example, a tungsten film. The thickness of this tungsten film is
For example, it is about 100 nm.

On the upper electrode 15, an interlayer insulating film 17
Is provided. The interlayer insulating film 17 is, for example, BPSG on the silicon oxide film (B oron P hospho S ilicate
(G lass) film.

The data line 18 is formed on the interlayer insulating film 17.
Is provided. The data line 18 is made of, for example, a tungsten film. The data line 18 is connected to the other of the pair of n-type semiconductor regions 7 of the selection MISFET Qs through a connection hole provided in the interlayer insulating film 17. Further, a surface protective film (not shown) is provided on the data line 18.

Next, a method of manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS.

First, p-type semiconductor substrate 1 is provided with p-type semiconductor substrate 1.
Type well region 2 and p + forming channel stopper region
The mold semiconductor region 3 and the element isolation insulating film 4 are formed.

Next, the main surface of the p − -type well region 2 is thermally oxidized to form the gate insulating film 5 of the selection MISFET Qs. Thereafter, a polycrystalline silicon film is formed on gate insulating film 5.

Next, the polycrystalline silicon film is patterned by a photolithography technique and an etching technique.
As shown in the figure, the gate electrode 6 of the selection MISFET Qs
To form Thereafter, a silicon oxide film is formed and patterned by photolithography and etching to form an insulating film 9 on the gate electrode 6. Also,
The patterning of the gate electrode 6 and the insulating film 9 may be performed in one step.

Next, using the gate electrode 6 as a mask for impurity introduction, an n-type impurity is implanted into the main surface of the p − -type well region 2 by ion implantation to form a pair of n-type semiconductor regions 7. To form

Next, a silicon oxide film is deposited. Thereafter, the silicon oxide film is anisotropically etched by an amount corresponding to the thickness of the deposited silicon oxide film.
A sidewall spacer 10 is formed on the side wall portion of.

Next, a polycrystalline silicon film 11 is deposited by, for example, a CVD method. Thereafter, the polycrystalline silicon film 11 is patterned by a photolithography technique and an etching technique.

Next, a tantalum-tungsten film 12 containing about 50 atm% of tantalum is formed by, for example, a sputtering method using an alloy target. The tantalum / tungsten film 12 is formed, for example, with a thickness of about 500 nm. Thereafter, the tantalum-tungsten film 12 is patterned by photolithography and etching as shown in FIG. By performing this step, lower electrode 13 composed of a laminated film of polycrystalline silicon film 11 and tantalum / tungsten film 12 is formed.

Next, a heat treatment is performed at a temperature of about 700 ° C. for about 30 minutes. The atmosphere during this heat treatment is, for example,
It is a gas mixture of about 30% steam and hydrogen, and the pressure is 1
It is about atmospheric pressure. In this heat treatment step, the partial pressure between the water vapor and the hydrogen gas is important, and it is not particularly necessary to define the total pressure. By performing this heat treatment, the tantalum contained in the tantalum-tungsten film 12 is oxidized, and the surface of the tantalum-tungsten film 12
As shown in FIG. 4, a tantalum oxide film 14 is formed.
That is, the tungsten in the tantalum-tungsten film 12 is not oxidized, and only the tantalum is oxidized. By selectively oxidizing the tantalum in the tantalum-tungsten film 12, a part of the tantalum oxide is deposited on the surface of the tantalum-tungsten film 12, and the remaining tantalum oxide remains in the tantalum-tungsten film 12. Since it remains, the tantalum-tungsten film 12 is composed of tungsten and tantalum oxide. The tantalum oxide film 14 formed by this heat treatment constitutes the charge storage insulating film 14 of the capacitor C. This tantalum oxide film 1
In the formation of 4, steam becomes an oxidizing agent and hydrogen gas becomes a reducing agent. Here, in the selective oxidation, the partial pressure ratio between water vapor and hydrogen is surrounded by curves A and B shown in FIG. 5 (a diagram showing the partial pressure ratio between water vapor and hydrogen when the charge storage insulating film is formed). It is possible within the area. In the region where the partial pressure ratio is larger than the curve A, both tantalum and tungsten are oxidized, and tantalum oxide and tungsten oxide are simultaneously formed. In a region where the partial pressure ratio is smaller than the curve B, neither tantalum nor tungsten is oxidized. In other words, in the region surrounded by the curves A and B, only tantalum is selectively oxidized, and tungsten is not oxidized, and tantalum oxide and tungsten are formed. Further, in the shaded region of FIG. 5, selective oxidation of the tantalum oxide film can be performed more effectively. The condition shown in FIG. 5 is a case where the total pressure is 1 atm. However, as described above, the total pressure does not need to be particularly defined. In FIG. 5, the heat treatment temperature of the hatched portion is 450
° C to 850 ° C. This range is specified by the controllability of the oxidation rate. That is, if the temperature is too high, the oxidation rate is high and it is difficult to control the film thickness. In addition, if the temperature is low, the oxidation rate is low, and the throughput is poor. Further, the lower limit of the partial pressure ratio was set to -3 as a range in which the flow rates of steam and hydrogen could be easily controlled.

The tantalum / tungsten film 12 and n
The polycrystalline silicon film 11 is provided between main surfaces of the type semiconductor region 7.
In the oxidation step for forming the tantalum oxide film 14, the tantalum-tungsten film 12
Thus, it is possible to reduce the occurrence of dislocation of tungsten or tantalum through the polycrystalline silicon film 11 and the occurrence of dislocation in the main surface of the n-type semiconductor region 7.

Next, a tungsten film having a thickness of about 100 nm is formed on the charge storage insulating film 14 by, for example, a sputtering method. Thereafter, the tungsten film is patterned by photolithography and etching to form the upper electrode 15 of the capacitor C.

Next, a silicon oxide film and a BPSG film are sequentially formed on the upper electrode 15, and an interlayer insulating film 17 is formed. Thereafter, the BP constituting the interlayer insulating film 17 is formed.
The SG film is subjected to a reflow process.

Next, a data line (1) is formed on the interlayer insulating film 17.
8) Forming a connection hole for connection. Thereafter, a tungsten film is formed, and the tungsten film is patterned by a photolithography technique and an etching technique to form a data line 18 as shown in FIG. Thereafter, by forming a surface protection film (not shown), the first embodiment is formed.
Is completed.

As described above, according to the manufacturing method of the first embodiment, the tantalum oxide film forming the charge storage insulating film 14 is selectively formed from the tantalum-tungsten film 12 made of tantalum and tungsten. As a result, the tantalum-tungsten film 12 functions as a barrier layer, so that a reduction reaction occurs between the polycrystalline silicon film 11 forming the lower electrode 13 and the tantalum oxide film forming the charge storage insulating film 14. Absent. Therefore, since it is not necessary to form a silicon oxide film on the polycrystalline silicon film 11, the charge storage insulating film 14 can be formed of a single layer of a tantalum oxide film.

The tantalum / tungsten film 12
Since silicon does not exist at the interface between the tantalum oxide film and the tantalum oxide film, no silicon oxide film is formed at the interface between the tantalum / tungsten film 12 and the tantalum oxide film. Therefore,
The charge storage insulating film 14 can be formed of a single-layer tantalum oxide film.

When the tantalum in the tantalum / tungsten film 12 is selectively oxidized, the tantalum oxide film is deposited on the surface of the tantalum / tungsten film 12. This deposited tantalum oxide film stops growing at a certain thickness.
This phenomenon is considered to be a kind of grain boundary segregation. Therefore, even if the tantalum-tungsten film 12 is sufficiently oxidized, only the tantalum oxide film is selectively formed.

As described above, since the charge storage insulating film 14 can be constituted by a single layer film of a tantalum oxide film, a single layer film of a silicon oxide film, a laminated film of a silicon oxide film and a silicon nitride film, or a silicon oxide film The dielectric constant of the charge storage insulating film 14 is higher than that in the case where the charge storage insulating film 14 is formed of a laminated film of a film and a tantalum oxide film. Thereby, in the method of manufacturing a semiconductor device, a dielectric film having a high dielectric constant can be formed.
Accordingly, the amount of charge stored per unit area of the charge storage insulating film 14 increases, so that the size of the capacitive element C is reduced.
High integration of the semiconductor device can be achieved.

In the first embodiment, the example in which the tantalum oxide film is formed from the tantalum / tungsten film 12 is shown, but the tantalum oxide film may be formed from a molybdenum film containing tantalum (tantalum / molybdenum film). . In this case, in the selective oxidation for forming the tantalum oxide film, the partial pressure ratio between water vapor and hydrogen is a curve shown in FIG. 6 (a diagram showing the partial pressure ratio between water vapor and hydrogen when forming the charge storage insulating film). This is possible within a region surrounded by C and D. In the region where the partial pressure ratio is larger than the curve C, both tantalum and molybdenum are oxidized, and tantalum oxide and molybdenum oxide are simultaneously formed. In the region where the partial pressure ratio is smaller than the curve D, neither tantalum nor molybdenum is oxidized. That is, in the region surrounded by the curves C and D, only tantalum is selectively oxidized, and molybdenum is not oxidized, and tantalum oxide and molybdenum are formed. Further, in the shaded region in FIG. 6, the selective oxidation of the tantalum oxide film can be performed more effectively. The condition shown in FIG. 6 is a case where the total pressure is 1 atm. However, as described above, the total pressure does not need to be particularly defined. In FIG. 6, the heat treatment temperature of the hatched portion is 4
50 ° C to 850 ° C. This range is specified by the controllability of the oxidation rate. In other words, if it gets too hot,
Oxidation rate is fast and it is difficult to control film thickness. In addition, if the temperature is low, the oxidation rate is low, and the throughput is poor. Further, the upper limit of the partial pressure ratio was set to 3 and the lower limit was set to -3 so that the flow rates of steam and hydrogen could be easily controlled.

The tantalum / tungsten film 12
The tantalum inside functions as a stopper for the oxidizing agent. Therefore, it is possible to reduce the possibility that the oxidizing agent reaches the polycrystalline silicon film 11 and the silicon oxide film is formed at the interface between the tantalum / tungsten film 12 and the polycrystalline silicon film 11 to cause poor conduction.

Further, the content of tantalum in the tantalum-tungsten film 12 may be such that the thickness of the tantalum oxide film formed by oxidation can be secured and the tantalum oxide film functions as a stopper for the oxidizing agent.

Embodiment 2 Next, a method of manufacturing a semiconductor device according to Embodiment 2 of the present invention will be described.

The method of manufacturing a semiconductor device according to the second embodiment is different from the method of manufacturing a semiconductor device according to the first embodiment in that a tantalum oxide film 14 is formed on the tantalum-tungsten film 12 by, for example, a CVD method. The tantalum oxide film 14 is oxidized under the conditions described in the first embodiment.

When a tantalum film is formed in place of the tantalum / tungsten film 12 and a tantalum oxide film 14 is formed on the tantalum film, the thickness of the tantalum oxide film formed in the oxidation step is controlled. difficult. When a tungsten film is formed in place of the tantalum / tungsten film 12 and a tantalum oxide film 14 is formed on the tungsten film and then oxidized, a metal interface is formed between the tantalum oxide film 14 and the tungsten film. No oxide is formed. Thus, in the manufacturing method of the second embodiment, as described above, the tantalum-tungsten film 12 containing tantalum, which is a metal oxidized in the oxidation step, is formed, and the tantalum oxide film 14 is formed on the tantalum-tungsten film 12. Is formed and oxidation is performed.

The tantalum oxide film 14 is made of, for example, 42
At a temperature of about 0 ° C. and a pressure of about 79.99 Pa, 500 sc
cm (S tandard C ubic C entimeter per M inute:
Oxygen of about gas flow rate and nitrogen of about 500 sccm are used as carrier gas, and pentaethoxy tantalum (T
It is formed by bubbling a (OC ₂ H ₅ ) ₅ ). This tantalum oxide film 14 is formed to a thickness of, for example, about 18 to 24 nm or less, similarly to the first embodiment.

As described above, according to the method of manufacturing the semiconductor device of the second embodiment, even if the thickness of the tantalum oxide film 14 deposited on the Is performed, in the region (weak spot) where the thickness of the tantalum oxide film 14 is small, the tantalum in the underlying tantalum / tungsten film 12 is oxidized and the tantalum oxide film is deposited on the surface of the tantalum / tungsten film 12. At this time, the amount of tantalum consumed at the interface between the tantalum-tungsten film 12 and the tantalum oxide film 14 diffuses from the tantalum-tungsten film 12 to the interface between the tantalum-tungsten film 12 and the tantalum oxide film 14. Therefore, the thickness of the formed tungsten oxide film 14 can be easily controlled. Due to the tantalum oxide film formed by this oxidation, the thickness of the tantalum oxide film 14 in the region where the film thickness is small is increased. Further, the tantalum oxide film deposited on the surface of the tantalum / tungsten film 12 stops growing at a constant thickness. Accordingly, the tantalum oxide film 14 formed on the tantalum / tungsten film 12 can be sufficiently oxidized, and the thickness variation of the tantalum oxide film 14 can be reduced. Accordingly, the withstand voltage of the charge storage insulating film is improved, so that the reliability of the semiconductor device can be improved.

The tantalum-tungsten film 12 described in the first embodiment can be used instead of the tantalum-tungsten film 12 in the second embodiment. The oxidation conditions in that case are the same as those described in the first embodiment.

Third Embodiment Next, the structure of a semiconductor device according to a third embodiment of the present invention will be described with reference to FIG. As shown in FIG. 7, the semiconductor device of the third embodiment is a DRAM having a memory cell in which a selection MISFET Qs and a capacitor C having a stacked structure are connected in series, as in the first embodiment. This memory cell stores 1-bit information. In FIG. 7, peripheral circuits are not shown, and description thereof is omitted.

The semiconductor device comprises a p-type semiconductor substrate 50
It is composed of The p − type semiconductor substrate 50 is made of, for example, single crystal silicon.

As shown in FIG. 7, the selection MISFET Qs is formed on the main surface of the p-type semiconductor region 55 in the active region defined and surrounded by the element isolation region. The selection MISFET Qs mainly includes a channel formation region (p-type semiconductor region 55), a gate insulating film 57, a gate electrode 58, and a pair of n-type semiconductor regions 61 used as a source region and a drain region.

The element isolation region includes an element isolation insulating film (field insulating film) 54 and an element isolation insulating film 5.
The semiconductor device is mainly constituted by a p + -type semiconductor region 53 (corresponding to a p-type channel stopper region) 53 below the semiconductor device.

The p + -type semiconductor region 53 used as the element isolation region and the p-type semiconductor region 55 used as the channel formation region of the selection MISFET Qs are provided on the main surface of the p − -type well region 51. Have been.
This p − type well region 51 is formed by the p − type semiconductor substrate 50.
Is provided on the main surface of the main body. The p-type semiconductor region 55
Constitutes a potential barrier for minority carriers generated by α-rays incident on either the p − -type well region 51 or the p − -type semiconductor substrate 50, particularly in a region where the memory cell is arranged.

The gate insulating film 57 of the selection MISFET Qs is provided on the main surface of the p-type semiconductor region 55. The gate insulating film 57 is made of, for example, a silicon oxide film.

The gate electrode 58 is provided on the gate insulating film 57. This gate electrode 58 is made of, for example, a polycrystalline silicon film. This polycrystalline silicon film is formed in a gate material forming step of a first layer in a manufacturing process. This polycrystalline silicon film is deposited by a CVD method. Further, an impurity for reducing the resistance value, for example, an n-type impurity is introduced into the polycrystalline silicon film during or after the deposition. The gate electrode 58 is formed integrally with and electrically connected to the word line (WL) 58 in the gate width direction (that is, formed of the same conductive layer). Further, in order to increase the operation speed of the selection MISFET Qs, the gate electrode 58 is formed by forming a single-layer film of a refractory metal film or a refractory metal silicide film, or a refractory metal film on a polycrystalline silicon film; It may be formed of a laminated film in which any one of the refractory metal silicide films is laminated.

On the upper surface of the gate electrode 58, an insulating film 59 is provided. In addition, an insulating sidewall spacer (sidewall insulating film) 62 is provided on a side surface (sidewall) of the gate electrode 58. Similarly, word line 58
An insulating film 59 is provided on the upper surface, and a sidewall spacer 62 is provided on the side surface. These insulating films 5
9. Each of the side wall spacers 62 is provided as an insulating film covering the surface of a part of the gate electrode 58 or a part of the word line 58. The insulating film 59 and the sidewall spacers 62 form an insulating film that covers the entire gate electrode 58 (upper surface and side surface) or the entire surface of the word line 58. Both the insulating film 59 and the sidewall spacer 62 are formed in self-alignment with the gate electrode 58 or the word line 58. Each of the insulating film 59 and the sidewall spacers 62 is composed of, for example, a silicon oxide film deposited by a CVD method.

The n-type semiconductor region 61 used as either the source region or the drain region is provided on the main surface of the p-type semiconductor region 55. The n-type semiconductor region 61 is formed in a self-alignment with the side of the gate electrode 58. The n-type semiconductor region 61 is formed in the same manufacturing process as the low impurity concentration n-type semiconductor region constituting the source or drain region of the n-channel MISFET Qn of the peripheral circuit (not shown) (corresponding to the same conductive layer). Do). The n-channel MISFE
TQn employs an LDD structure and has a low impurity concentration of n.
Semiconductor region is the LDD of the n-channel MISFET Qn.
Used as a part. Therefore, the selection MISFET Qs
Since at least the drain region is composed of the n-type semiconductor region 61 having a low impurity concentration, the semiconductor device substantially has an LDD structure.

Although not shown in FIG. 7, the selection MI
Either the source region or the drain region of the SFET Qs is provided with a polycrystalline silicon film 66 constituting a lower electrode of the capacitive element C.
Diffuses n-type impurities. As a result, an n-type semiconductor region 61 having a low impurity concentration and a diffused n + -type semiconductor region having a high impurity concentration are formed.

As shown in FIG. 7, the capacitive element C
Above the selection MISFET Qs, a so-called stacked structure is formed in which a lower electrode, a charge storage insulating film 69 and an upper electrode 70 are sequentially stacked.

The lower electrode is composed of a laminated film in which a polycrystalline silicon film 66, a titanium nitride film 67, and a tungsten film containing tantalum (tantalum / tungsten film) 68 are laminated from the lower layer side.

The lower electrode thus configured has a central portion at the other n-type semiconductor region 6 of the selection MISFET Qs.
1 and the peripheral portion is a MISFE for selection.
Another word line 5 extending over the TQs gate electrode 58 and adjacent to the word line 58 connected to the gate electrode 58
Stretched on 8. This lower electrode is formed of an interlayer insulating film 6.
In a region defined between the gate electrode 58 and the other word line 58, the connection hole is formed in the region 4 and is connected to the other n-type semiconductor region 61. The lower electrode and the gate electrode 58 are insulated through an insulating film 59 covering at least the surface of the gate electrode 58 and a sidewall spacer 62. The lower electrode is connected to the other n-type semiconductor region 61 along the surface of the insulating film 59 and the side wall spacer 62 in self-alignment with the gate electrode 58.

The thickness of the polycrystalline silicon film 66 is, for example,
It is about 200 nm. This polycrystalline silicon film is deposited by a CVD method. During the deposition or after the deposition, an impurity such as an n-type impurity that reduces the resistance value is introduced into the polycrystalline silicon film 66.

The titanium nitride film 67 is provided so as to cover the surface of the polycrystalline silicon film 66. The thickness of the titanium nitride film 67 is, for example, about 100 to 200 nm. This titanium nitride film 67 is formed by, for example, a sputtering method. The titanium nitride film 67 functions as an oxidation resistant film for reducing the oxidation of the polycrystalline silicon film 66, as described later.

The tantalum content of the tantalum-tungsten film 68 is, for example, about 50 atm%. The tantalum / tungsten film 68 is formed by, for example, a sputtering method using an alloy target. The thickness of the tantalum / tungsten film 68 is, for example, about 500 nm.

The lower electrode is formed to have a large thickness of about 900 nm, for example, as a total thickness of the laminated film, for the purpose of increasing the amount of charge storage, with the periphery of the side surface serving as a charge storage region. The lower electrode is a gate electrode 58
And a step shape corresponding to each of the total film thickness of the insulating film 59 and the total film thickness of the word line 58 and the insulating film 59 is formed in the center portion. The charge storage amount can be increased.

The lower electrode thus configured corresponds to a storage node region for storing information stored in a memory cell, is arranged for each memory cell, and is formed independently of another adjacent memory cell. You.

The charge storage insulating film 69 is provided along the top and side surfaces of the tantalum / tungsten film 68. The charge storage insulating film 69 is made of, for example, a tantalum oxide film. The dielectric constant of a tantalum oxide film is about six times that of a silicon oxide film, and is higher than that of a silicon oxide film, a silicon nitride film, or a stacked film thereof. The thickness of this tantalum oxide film is, for example, about 18 to 24 nm or less. Accordingly, the size of the capacitor C for securing the same amount of accumulated charge can be reduced, so that high integration of the semiconductor device can be achieved.

The upper electrode 70 is provided on the upper and side surfaces of the lower electrode with a charge storage insulating film 69 interposed therebetween. The upper electrode 70 is connected to the capacitive element C of the memory cell.
And a plate electrode formed integrally with and electrically connected to the upper electrode 70 of the capacitive element C of another memory cell arranged adjacent to the periphery thereof and common to a plurality of memory cells arranged in the memory cell array. Is configured as The upper electrode 70 is made of, for example, a tungsten film. This tungsten film is formed, for example, by a sputtering method. Since at least three conductive layers are used in the memory cell, the step shape becomes large. Therefore,
In order to alleviate the step shape, the tungsten film has a small thickness of, for example, about 100 nm.

In the memory cell thus configured, as shown in FIG. 7, a complementary bit line (BL) 75 is connected to one n-type semiconductor region 61 of the selection MISFET Qs.
Are electrically connected. This complementary bit line 75
Extends over the surface of the interlayer insulating film 72 and has a connection hole (bit line contact hole) formed in the interlayer insulating film 72.
To one of the n-type semiconductor regions 61.

The interlayer insulating film 72 is composed of a silicon oxide film and a BPSG film laminated thereon. The silicon oxide film is formed by, for example, a CVD method. Said B
The PSG film is formed by, for example, a CVD method.

The complementary bit line 75 is formed, for example, of a polycrystalline silicon film 73 and a refractory metal silicide film 74 laminated thereon.
Are formed. This polycrystalline silicon film 73
For example, it is deposited by a CVD method. During the deposition or after the deposition, an impurity such as an n-type impurity that reduces the resistance value is introduced into the polycrystalline silicon film 73. The refractory metal silicide film 74 is formed, for example, by a sputtering method or a CVD method.
It is composed of a tungsten silicide film deposited by the method.

A data line (DL) 79 is provided on the complementary bit line 75 with an interlayer insulating film 78 interposed.

The interlayer insulating film 78 is composed of a lower silicon oxide film 76 and a BPSG film 77 laminated thereon. The silicon oxide film 76 is deposited by, for example, a CVD method. The BPSG film 77 is deposited by, for example, a CVD method.

The data lines 79 are formed in a first-layer wiring material forming step in the manufacturing process. The data line 79 is formed of, for example, a laminated film of a high melting point metal film. The lower refractory metal film is made of, for example, a tungsten film. This tungsten film is formed, for example, by a sputtering method. The upper refractory metal film is, for example, a tungsten film deposited by a CVD method.

A shunt word line (WL) 84 is provided on the data line 79 with an interlayer insulating film 80 interposed.

The interlayer insulating film 80 is composed of three silicon oxide films. The lower silicon oxide film constituting the interlayer insulating film 80 is, for example, TEOS (T etra E thoxyl
O rtho S ilane: tetraethoxy Le ortho silane)
It is formed by a plasma CVD method using gas as a raw material.
Silicon oxide film middle constituting the interlayer insulating film 80 is, for example, is composed of SOG (S pin O n G lass ) film. The upper silicon oxide film constituting the interlayer insulating film 80 is formed by a plasma CVD method using TEOS gas as a raw material, similarly to the lower silicon oxide film.

The shunt word line 84 is formed in the wiring material forming step of the second layer in the manufacturing process.
The shunt word line 84 has, for example, a three-layer structure in which a titanium tungsten film 81, an aluminum alloy film 82, and a titanium tungsten film 83 are sequentially stacked. The titanium tungsten films 81 and 83 are deposited by, for example, a sputtering method. The aluminum alloy film 82 contains silicon and copper. This aluminum alloy film 82 is deposited by, for example, a sputtering method.

The shunt word line 84 is connected to the lower word line 58 at an end of the memory cell array (memory cell mat) or at any region between the memory cell arrays. This shunt word line 84 and word line 5
8 are connected via an intermediate conductive layer formed of the same conductive layer as the data line 79 and an intermediate conductive layer formed of the same conductive layer as the complementary bit line 75, respectively.

On the shunt word line 84, a final protective film 87 is provided. This final protective film 22
For example, it has a three-layer structure in which a silicon oxide film 85, a silicon nitride film 86, and a resin film (not shown) are sequentially laminated. The silicon oxide film 85 is deposited by a plasma CVD method using a TEOS gas that can be formed at a low temperature as a raw material. The silicon nitride film 86 is deposited by, for example, a plasma CVD method. The resin film (not shown) is made of, for example, a polyimide resin film applied and cured by a spin coating method.

Next, a method of manufacturing the semiconductor device will be described with reference to FIG.
7 to FIG. 14 (enlarged main portions in FIG. 7 and cross-sectional views of main portions shown for each process). The illustration and description of the peripheral circuit are omitted.

First, a p − type semiconductor substrate 50 made of single crystal silicon is prepared. Thereafter, the p-type semiconductor substrate 50
A p-type well region 51 is formed in the main surface portion of FIG.

Next, an element isolation insulating film 54 is formed on the main surface of the non-active region (element isolation region) of the p − -type well region 51 by using a well-known selective thermal oxidation technique.

In substantially the same manufacturing process as the step of forming the inter-element isolation insulating film 54, the p + -type semiconductor region 53 Is formed. This p + type semiconductor region 5
Reference numeral 3 denotes a channel stopper region, and the impurity concentration is set slightly higher than that of the p − type well region 51.

Next, a p-type semiconductor region 55 is formed inside the p − -type well region 51. The p-type semiconductor region 55 has a slightly higher impurity concentration than the p − -type well region 51. This p-type semiconductor region 55
It is formed at a position deeper than the main surface of the p − -type well region 51 as compared with the p-type semiconductor region 55 below the element isolation insulating film 54 and is formed as a potential barrier.

Next, an impurity for adjusting the threshold voltage of the MISFET is introduced into the active region on the main surface of the p − -type well region 51. Thereafter, the main surface of the active region of the p − -type well region 51 is thermally oxidized to form a gate insulating film 57.
To form

Next, polycrystalline silicon is deposited on the gate insulating film 57 by, for example, a CVD method. This polycrystalline silicon film is formed in the first-layer gate material forming step. An n-type impurity, for example, P is introduced into this polycrystalline silicon film and a polycrystalline silicon film formed in a subsequent step. Thereafter, an insulating film 59 such as a silicon oxide film is formed on the polycrystalline silicon film.
It is deposited by a CVD method.

Next, the gate electrode 58 is formed by patterning the laminated film of the polycrystalline silicon film and the insulating film 59 by photolithography and etching. In the same manufacturing process as the process of forming the gate electrode 58,
A word line 58 is formed on the inactive region (on the element isolation insulating film 54).
Is formed, and an insulating film 59 covering the upper surface of the word line 58 is formed in the same manufacturing process as the process of forming the insulating film 59.

Next, an n-type impurity, for example, P is introduced into the main surface of the p-type semiconductor region 55 by ion implantation.
An n-type semiconductor region 61 forming the source region and the drain region of the selection MISFET Qs is formed. When introducing the n-type impurity, the gate electrode 58 and the insulating film 59 (or a photoresist film for patterning them) are used as a main body of an impurity introducing mask. By forming the n-type semiconductor region 61, the selection MISFET Qs is substantially completed.

Next, as shown in FIG. 8, sidewall spacers 62 are formed on the side surfaces of the gate electrode 58 (including the word line 58) and the insulating film 59 of the selection MISFET Qs. The sidewall spacer 62 is formed by depositing a silicon oxide film by, for example, a CVD method, and performing anisotropic etching such as RIE on the silicon oxide film by an amount corresponding to the deposited film thickness. This sidewall spacer 62 is formed in a self-alignment manner with respect to the gate electrode 58 (and the word line 58). In addition, by the process of forming the sidewall spacer 62 , the insulating film 59 (which covers the upper surfaces of the gate electrode 58 and the word line 58) formed in advance and the gate electrode 58 and the word line 58 are formed.
The insulating film that covers the entire surface (upper surface and side surface) is completed.

Next, an interlayer insulating film 64 is formed. The interlayer insulating film 64 is formed of, for example, a silicon oxide film deposited by a CVD method, and has a thickness of about 150 to 250 nm. This interlayer insulating film 64 is formed of the selection MISFET Q
It is formed for the purpose of forming a connection hole connecting between the other n-type semiconductor region 61 of s and the lower electrode of the capacitor C.
The interlayer insulating film 64 is formed for the purpose of insulating between the gate electrode 58 (and the word line 58) of the selection MISFET Qs and the lower electrode of the capacitor C. Further, the interlayer insulating film 64 is a charge storage insulating film 69 of the capacitor C,
It is also used as an etching stopper layer when patterning each of the upper electrodes 70.

Next, the interlayer insulating film 64 on the other n-type semiconductor region 61 of the selection MISFET Qs is removed, and a connection hole exposing the surface of the other n-type semiconductor region 61 is formed. This connection hole is provided in the selection MISFET Q
An opening end is formed on the s gate electrode 58 and on the word line 58 connected to the adjacent memory cell.

Next, for example, the polycrystalline silicon film 6 is formed by the CVD method.
6 is deposited. This polycrystalline silicon film 66 is, for example, 20
It is formed with a thickness of about 0 nm. Thereafter, as shown in FIG. 9, the polycrystalline silicon film 66 is patterned by a photolithography technique and an etching technique. The polycrystalline silicon film 66 is connected to the other n-type semiconductor region 61 of the selection MISFET Qs through a connection hole formed in the interlayer insulating film 64.

Next, a titanium nitride film 67 is deposited by, for example, a sputtering method. This titanium nitride film 67 is formed, for example, with a thickness of about 100 nm. Thereafter, as shown in FIG. 10, the titanium nitride film 67 is patterned by photolithography and etching.

Next, a tantalum / tungsten film 68 is formed
For example, it is formed by a sputtering method using an alloy target. This tantalum / tungsten film 68 has a thickness of 50 atm.
% Of tantalum. This tantalum / tungsten film 68 is formed with a thickness of about 500 nm.
Thereafter, this tantalum / tungsten film 68 is
As shown in (1), patterning is performed by a photolithography technique and an etching technique.

Next, as shown in FIG. 12, a charge storage insulating film 69 is formed. This charge storage insulating film 69 is formed, for example, by bubbling pentaethoxy tantalum at a temperature of about 420 ° C. and a pressure of about 49.99 Pa using oxygen of about 500 sccm and nitrogen of about 500 sccm as a carrier gas to form a tantalum oxide film. Is formed. This tantalum oxide film is formed with a thickness of, for example, about 18 to 24 nm or less as in the first embodiment.

Next, heat treatment is performed at a temperature of about 700 ° C. for about 30 minutes. The atmosphere during this heat treatment is, for example,
It is a mixed gas of water vapor and hydrogen gas at about 1 atm and 30%. The partial pressure at this time may be set as shown in FIG. 5 of the first embodiment. By performing this heat treatment, even if the thickness of the tantalum oxide film 69 varies,
In a region (weak spot) where the thickness of the tantalum oxide film 69 is small, the tantalum in the underlying tantalum / tungsten film 68 is oxidized to form the tantalum / tungsten film 6.
8, a tantalum oxide film is deposited. At this time, the amount of tantalum consumed at the interface between the tantalum / tungsten film 68 and the tantalum oxide film is reduced to the tantalum / tungsten film 6.
8 and diffuses into the interface between the tantalum / tungsten film 68 and the tantalum oxide film, so that the thickness of the formed tantalum oxide film can be easily controlled. That is, the growth of the tantalum oxide film deposited on the surface of the tantalum / tungsten film 68 stops at a constant thickness. As a result, the thickness of the tantalum oxide film in the region with a small thickness is increased by the tantalum oxide formed by this heat treatment, so that variation in the thickness of the tantalum oxide film can be reduced. Thereby, the withstand voltage of the charge storage insulating film 69 is improved, so that the reliability of the semiconductor device can be improved.

The tantalum / tungsten film 68
Nitride film 6 formed between silicon and polycrystalline silicon film 66
Reference numeral 7 functions as an oxidation-resistant film in the heat treatment step after the deposition of the tantalum oxide film. Therefore, in this heat treatment step, the oxidation of the polycrystalline silicon film 66 can be further reduced. Further, the reaction between the tantalum / tungsten film 68 and the polycrystalline silicon film 66 can be reduced.

The tantalum / tungsten film 68 and n
Between the main surfaces of the type semiconductor region 61, the polycrystalline silicon film 6 is formed.
6 and the titanium nitride film 67, in the heat treatment step after the deposition of the tantalum oxide film, tungsten or tantalum penetrates from the tantalum / tungsten film 68 through the polycrystalline silicon film 66 and the main surface of the n-type semiconductor region 61. Generation of dislocations can be reduced.

Next, an upper electrode 70 is formed. The upper electrode 70 is formed, for example, by depositing a tungsten film by a sputtering method. This tungsten film is formed, for example, with a thickness of about 100 nm. Thereafter, the tungsten film is patterned by a photolithography technique and an etching technique to form the upper electrode 17 of the capacitor C as shown in FIG. Through the step of forming the upper electrode 70, the capacitive element C having a stacked structure is completed. With the completion of the capacitive element C, a memory cell is completed.

Next, an interlayer insulating film 72 is formed. The interlayer insulating film 72 is formed by depositing a silicon oxide film by a CVD method and then forming a CV
It is formed by depositing a BPSG film by the D method. Upper BPS
After deposition, the G film is subjected to a reflow treatment to flatten the surface.

Next, a connection hole is formed in the interlayer insulating film 72. This connection hole is formed so as to expose the surface of one n-type semiconductor region 61 of the selection MISFET Qs. In this step, the charge storage insulating film 6 in the connection hole forming region is formed.
9 is removed.

Next, a complementary bit line 75 is formed on the interlayer insulating film 72, as shown in FIG. The complementary bit line 75 is connected to a memory cell through a connection hole of the interlayer insulating film 72. This complementary bit line 75
Are formed in a fourth-layer gate material forming step. This complementary bit line 75 is formed by depositing a polycrystalline silicon film 73 by a CVD method, depositing a tungsten film 74 by a sputtering method or a CVD method, and patterning this laminated film by a photolithography technique and an etching technique. You.

Next, an interlayer insulating film 78 is formed. After the silicon oxide film 76 is deposited by the CVD method,
It is formed by depositing a BPSG film 77 by a CVD method. The BPSG film 77 is subjected to a reflow process after the film is deposited.

Next, a data line 79 is formed on the interlayer insulating film 78. The data lines 79 are formed in the first-layer wiring material forming step. The data lines 79 are formed by patterning a laminated film of a high melting point metal film by a photolithography technique and an etching technique. The laminated film of the refractory metal is formed, for example, by depositing a tungsten film by a sputtering method and then depositing a tungsten film by a CVD method.

Next, an interlayer insulating film 80 is formed. This interlayer insulating film 80 is formed of a three-layer silicon oxide film. The lower and upper silicon oxide films are formed, for example, by a plasma CVD method using TEOS gas as a raw material. The middle silicon oxide film is formed of, for example, an SOG film.

Next, a shunt word line 84 is formed. The shunt word line 84 is formed in the second-layer wiring material forming step. The shunt word line 84 is formed by, for example, a titanium tungsten film 81 by sputtering.
After depositing each of the aluminum alloy film 82 and the titanium tungsten film 83, the laminated film is patterned by photolithography and etching.

Next, by forming a final protective film 87, the semiconductor device of the third embodiment shown in FIG. 7 is completed. The final protective film 87 is formed, for example, by depositing a silicon oxide film 85 by a plasma CVD method using TEOS gas as a raw material,
A silicon nitride film 85 is deposited by a plasma CVD method, and a polyimide resin film (not shown) is applied and cured to form the film.

As described above, according to the method of manufacturing the semiconductor device of the third embodiment, similarly to the first embodiment, the charge storage insulating film 69 is formed of a single layer of a tantalum oxide film. Therefore, the dielectric constant of the charge storage insulating film increases. Thereby, in the method of manufacturing a semiconductor device,
A dielectric film having a high dielectric constant can be formed. In addition, the size of the capacitor can be reduced, and high integration of the semiconductor device can be achieved.

As in the case of the second embodiment, even when the thickness of the tantalum oxide film deposited by the CVD method varies, by performing oxidation, the region where the thickness of the tantalum oxide film is thin is reduced. Tantalum and tungsten film 6
8 is oxidized, and a tantalum oxide film is deposited on the surface of the tantalum tungsten film 68. Furthermore, the growth of the deposited tantalum oxide film stops at a constant film thickness. Therefore, the tantalum oxide film deposited on the tantalum / tungsten film 68 can be sufficiently oxidized, and the variation in the thickness of the tantalum oxide film can be reduced by the deposited tantalum oxide film. Thereby, the withstand voltage of the charge storage insulating film 69 is improved, so that the reliability of the semiconductor device can be improved.

In the oxidation step after depositing the tantalum oxide film, the oxidation of the polycrystalline silicon film 66 constituting the lower electrode can be reduced. Also, a tantalum / tungsten film 6
8 and the polycrystalline silicon film 66 can be reduced.

In the third embodiment, the example in which the oxidation-resistant film is formed of the titanium nitride film 67 is shown. However, for example, the oxidation-resistant film may be formed of an alloy film of titanium and tungsten. When the oxidation-resistant film is formed by the titanium nitride film 67, the oxidation of the polycrystalline silicon film 66 or the
The reaction between the tungsten film 68 and the polycrystalline silicon film 66 is reduced to about 1
It can be reduced to a temperature of about 000 ° C. When the oxidation-resistant film is formed of an alloy film of titanium and tungsten, the oxidation of the polycrystalline silicon film 66 or the reaction between the tantalum / tungsten film 68 and the polycrystalline silicon film 66 is performed at about 700 ° C.
The temperature can be reduced to a certain degree.

[Embodiment 4] A method of manufacturing a semiconductor device according to Embodiment 4 of the present invention is the same as the method of manufacturing a semiconductor device of Embodiment 3, except that the oxidation resistant film is formed of a high melting point metal silicide film. is there. Hereinafter, a part of the manufacturing method will be described with reference to FIG. 15 to FIG.

First, as shown in FIG. 9, the steps up to the step of patterning the polycrystalline silicon film 66 are performed in the same manner as in the third embodiment.

Next, as shown in FIG. 15, a high melting point metal film 90 is formed. The refractory metal film 90 is formed by, for example, depositing a titanium film to a thickness of about 85 nm by a sputtering method. Thereafter, heat treatment is performed at a temperature of about 600 ° C. to cause the refractory metal film 90 to react with the underlying polycrystalline silicon film 66 (silicidation).
Thereafter, by removing the unreacted refractory metal film 90, a refractory metal silicide film (titanium silicide film) 91 is formed on the surface of the polycrystalline silicon film 66 as shown in FIG. When the thickness of the titanium film 90 is about 85 nm, the titanium silicide film 91 is formed with a thickness of about 200 nm. As described above, the refractory metal silicide film 91 is formed by forming the refractory metal silicide film 91 by silicidation of the refractory metal film 90.
6 is formed in a self-aligned manner. As a result, the planar layout area of the capacitor C can be further reduced, so that the semiconductor device can be further integrated.

Thereafter, the tantalum / tungsten film 6
The semiconductor device of the fourth embodiment is completed by performing the steps subsequent to the step of forming 8 in the same manner as in the third embodiment.

In the fourth embodiment, the example in which the oxidation resistant film is formed of a titanium silicide film has been described. However, for example, the oxidation resistant film may be formed of a nickel silicide film or a cobalt silicide film. . In order to form these refractory metal silicide films to a thickness of about 200 nm, a nickel film may be formed to a thickness of about 114 nm and a cobalt film may be formed to a thickness of about 56 nm.

Embodiment 5 Next, the structure of a semiconductor device according to Embodiment 5 of the present invention will be described with reference to FIG. In FIG. 17, the illustration of the peripheral circuit is omitted, and the description is also omitted.

As shown in FIG. 17, the semiconductor device of the fifth embodiment is a DRAM having a memory cell in which a stacked capacitive element C formed in a pore (trench) and a MISFET Qs for selection are connected in series. .

The semiconductor device is a p-type semiconductor substrate 10
0. This p− type semiconductor substrate 100
For example, it is made of single crystal silicon.

The MISFET Qs for selection mainly includes a gate insulating film 112, a gate electrode 113 provided on the gate insulating film 112, and an n-type semiconductor region 116 forming a source region and a drain region.

The gate insulating film 112 is provided on the main surface of the p − type semiconductor substrate 100. The gate insulating film 112 is made of, for example, a silicon oxide film.

The gate electrode 113 is made of, for example, a polycrystalline silicon film. The gate electrode 113 is formed integrally with the word line 113. On the gate electrode 113, an insulating film 114 is provided. The insulating film 114 is composed of, for example, a silicon oxide film deposited by a CVD method. Further, a sidewall spacer 118 is provided on a side wall of the gate electrode 113. The side wall spacer 118 is made of, for example, C
It is composed of a silicon oxide film deposited by the VD method.

The n-type semiconductor region 116 is formed on the main surface of the p − -type semiconductor substrate 100 by the gate electrode 1.
13 is provided in a self-aligned manner. The n-type semiconductor region 116 is a source region of the selection MISFET Qs,
It has one of the functions of a drain region. A data line 128 is connected to one side of the n-type semiconductor region 116 via a second connection electrode 125.

The capacitive element C is a p ^- type semiconductor substrate 10
It is provided on 0 the formed pore 10 3. The capacitance element C mainly includes a plate electrode 105 and a node electrode 107 provided on the plate electrode 105 via a charge storage insulating film 106.

The plate electrode 105 is connected to the pore 10
3, it is provided via an insulating film 104.
The plate electrode 105 is made of, for example, a tungsten film containing tantalum (tantalum / tungsten film). This tantalum tungsten film is 50 at
Contains about m% tantalum. The thickness of the tantalum / tungsten film is, for example, about 100 nm.
The insulating film 104 is made of, for example, a silicon oxide film. The thickness of the silicon oxide film is, for example, 40 to 60.
It is about nm.

The charge storage insulating film 106 is formed, for example, by
It is composed of a tantalum oxide film. The dielectric constant of a tantalum oxide film is about six times that of a silicon oxide film, and is higher than that of a silicon oxide film, a silicon nitride film, or a stacked film thereof.
The thickness of this tantalum oxide film is, for example, 18 to 24 nm.
Degree or less. Therefore, the size of the capacitor C for securing the same charge amount can be reduced, so that the semiconductor device can be highly integrated.

The node electrode 107 is made of, for example, a tungsten film. The thickness of the tungsten film is such that the inside of the pore 103 can be embedded. This tungsten film is composed of a laminated film of a tungsten film deposited by a sputtering method and a tungsten film deposited by a CVD method. The film thickness of these tungsten films is, for example, a film thickness deposited by a sputtering method or a CVD method.
Each is about 200 nm. The node electrode 107 is connected to one of the source region and the drain region of the selection MISFET Qs via the first connection electrode 121. The first connection electrode 121 is made of, for example, a polycrystalline silicon film.

The pore 10 in which the capacitance element C is provided
The cross-sectional shape of 3 is configured in a square shape. Further, at positions corresponding to the side wall and the bottom of the pore 103, the surface of the p − type semiconductor substrate 100 is not used as an electrode of the capacitive element C.

As described above, in the memory cell of the fourth embodiment, since the surface of the p − -type semiconductor substrate 100 having the pores 103 is not used as a capacitor electrode, the memory cell is resistant to alpha-ray soft errors, and , A low power consumption DRAM can be realized.

In the lower part of the memory cell, inside the p − type semiconductor substrate 100, the p − type semiconductor substrate 1
A p + -type semiconductor region 102 having an impurity concentration higher than 00 is provided. The p + type semiconductor region 102 is formed around the memory cell and in contact with the element isolation insulating film 101.

The first connection electrode 121 is provided in self-alignment with the gate electrode (word line) 113 via the sidewall spacer 118. Also,
The first connection electrode 125 is connected to the n-type semiconductor region 116 and the node electrode 107 through an opening in the interlayer insulating film 119. The interlayer insulating film 119 is made of, for example, a silicon oxide film.

The second connection electrode 125 is provided in self-alignment with the gate electrode (word line) 113 via the sidewall spacer 118. The second connection electrode 125 is made of, for example, a polycrystalline silicon film. The second connection electrode 125 is connected to the n-type semiconductor region 116 through an opening in the interlayer insulating film 124. This interlayer insulating film 124 is made of, for example, a silicon oxide film.

The data line 128 is made of, for example, a tungsten film. This data line 128 is connected to the first
Is connected to the second connection electrode 125 through a connection hole of the interlayer insulating film 127. The first interlayer insulating film 127 is composed of, for example, a laminated film of a silicon oxide film and a BPSG film.

In the upper layer of the data line 128, a second interlayer insulating film (not shown) and a wiring serving as a column select signal line are provided. The second interlayer insulating film is composed of, for example, three silicon oxide films. The upper and lower silicon oxide films are formed, for example, by a plasma CVD method using TEOS gas as a source gas. The silicon oxide film of the intermediate layer is composed of an SOG film. The wiring is made of, for example, a tungsten film or an aluminum alloy film to which silicon and copper are added. The tungsten film includes, for example, a stacked film of a tungsten film deposited by a sputtering method and a tungsten film deposited by a CVD method.

A third interlayer insulating film 130 is provided above the wiring (not shown). The third interlayer insulating film 130 is formed of, for example, three silicon oxide films. The upper and lower silicon oxide films are formed, for example, by a plasma CVD method using TEOS gas as a source gas.
The silicon oxide film of the intermediate layer is composed of an SOG film.

A shunt word line (WL) 131 is provided on the third interlayer insulating film 130. The shunt word line 131 is made of, for example, an aluminum alloy film or a laminated film mainly composed of an aluminum alloy film. The shunt word line 131 is connected to the word line 113 at the end of the memory mat.

On the shunt word line 131, a surface protective film 132 is provided. This surface protective film 13
Numeral 2 is a laminated film of, for example, a PSG film, a silicon nitride film deposited by a plasma CVD method, and a polyimide resin film.

Next, a method of manufacturing the semiconductor device according to the fifth embodiment will be described with reference to FIGS. 18 to 25 (a cross-sectional view of a main portion showing the region shown in FIG. 17 for each step). The illustration and description of the peripheral circuit are omitted.

First, a p − type semiconductor substrate 100 made of single crystal silicon is prepared. Thereafter, the p-type semiconductor substrate 1
00 is selectively thermally oxidized to form an element isolation insulating film 1.
01 is formed.

Next, B ions are implanted into the p − type semiconductor substrate 100 through the inter-element isolation insulating film 101 to form ap + type semiconductor region 102. The p + type semiconductor region 102 is formed at a position deeper than the region where the element isolation insulating film 101 is located in a region where the element isolation insulating film 101 is not located.

Next, the silicon nitride film having an opening formed at the position where the pore 103 is formed, or the silicon nitride film and a resist film for patterning the silicon nitride film are used as a mask to form a p-type film.
The mold semiconductor substrate 100 is etched to form pores 103. The pores 103 have a depth of 3 to 5 from the surface.
μm. The pore 103 is formed so as to remove an end portion of the inter-element isolation insulating film 101, that is, a bird's beak portion of the inter-element isolation insulating film 101. The pore 103 is formed by a dry etching technique and has a side surface substantially perpendicular to the main surface of the p − type semiconductor substrate 100.

Next, the silicon nitride film is removed and the insulating film 1 is removed.
04 is formed. The insulating film 104 is formed, for example, by depositing a silicon oxide film to a thickness of about 50 nm by a CVD method.

Next, a tantalum-containing tungsten film (tantalum-tungsten film) to be the first electrode of the capacitor C, that is, the plate electrode 105 is formed. This tantalum-tungsten film contains about 50 atm% of tantalum. This tantalum-tungsten film is formed, for example, by a sputtering method using an alloy target. This tantalum-tungsten film is, for example, 10
It is formed with a thickness of about 0 nm. After this, this tantalum
The tungsten film is patterned by a photolithography technique and an etching technique, and a plate electrode 105 is formed as shown in FIG.

Next, as shown in FIG. 19, a tantalum oxide film serving as the charge storage insulating film 106 of the capacitive element C is
It is formed to a thickness of about 24 nm or less. This tantalum oxide film is heated at, for example, a temperature of about 420 ° C.,
At a pressure of about 9.99 Pa, oxygen of about 500 sccm and 5
It is formed by bubbling pentaethoxy tantalum using nitrogen of about 00 sccm as a carrier gas.

Next, heat treatment is performed at a temperature of about 700 ° C. for about 30 minutes. The atmosphere during this heat treatment is, for example,
It is a mixed gas of water vapor and hydrogen gas at about 1 atm and 30%. The partial pressure at this time may be set as shown in FIG. 5 of the first embodiment. By performing this heat treatment, even in the case where the thickness of the tantalum oxide film varies, the tantalum in the underlying tantalum / tungsten film film is oxidized in a region (weak spot) where the thickness of the tantalum oxide film is small. As a result, a tantalum oxide film is deposited on the surface of the tantalum-tungsten film. Due to the tantalum oxide film formed by this heat treatment, the thickness of the tantalum oxide film in a thin region is increased. Further, the tantalum oxide film deposited on the surface of the tantalum / tungsten film stops growing at a certain thickness. Therefore, the tantalum oxide film formed on the tantalum / tungsten film can be sufficiently oxidized, and variation in the thickness of the tantalum oxide film can be reduced. Thus, the withstand voltage of the charge storage insulating film 106 can be improved.

Next, as shown in FIG. 20, a tungsten film serving as the second electrode of the capacitor C, that is, the node electrode 107, is formed with a thickness of about 400 nm. At this time, the inside of the pore 103 is filled with the tungsten film. This tungsten film is, for example, 200
After depositing a tungsten film of about 200 nm, a tungsten film of about 200 nm is further deposited by a CVD method.

Next, the tungsten film 107 is patterned by a photolithography technique and an etching technique so that its surface is substantially flush with the surface of the p − type semiconductor substrate 100 as shown in FIG. . Through this step, the capacitive element C is completed.

Next, an insulating film 110, for example, a silicon oxide film is deposited by the CVD method. Thereafter, this insulating film 110 is
Patterning is performed by a photolithography technique and an etching technique, and as shown in FIG. This insulating film 110
Node electrode 107 and word line 113 formed thereon
It is formed in order to insulate it. When patterning the insulating film 110, the silicon oxide film 104 and the tantalum oxide film 105 on the main surface of the p − type semiconductor substrate 100 are removed in a region other than the region where the pores 103 are formed.

Next, the surface of p − type semiconductor substrate 100 is thermally oxidized to form a silicon oxide film serving as gate insulating film 112. Thereafter, a third-layer polycrystalline silicon film serving as the gate electrode 113 and the word line 113 is deposited, and the insulating film 1 is formed thereon.
14 For example, a silicon oxide film is deposited. Then, both of them are processed into a pattern of the word line 113 by a photolithography technique and an etching technique.

Next, phosphorus or arsenic is ion-implanted to form a gate electrode (word line) 11 as shown in FIG.
An n-type semiconductor region 116 is formed by self-alignment with the semiconductor device 3.

Next, after depositing an insulating film, for example, a silicon oxide film by the CVD method, anisotropic etching corresponding to the deposited film thickness is performed, and the gate electrode (word line) 113 is formed.
A sidewall spacer 118 is formed on the side wall of.
Thereafter, as shown in FIG. 24, an interlayer insulating film 119 is formed. This interlayer insulating film 119 is formed, for example, by depositing a silicon oxide film by a CVD method.

Next, an opening is formed in the interlayer insulating film 119 to connect the node electrode 107 of the capacitor C with the source region or the drain region of the selection MISFET Qt. Thereafter, a polycrystalline silicon film is deposited by, for example, a CVD method.

Next, the polycrystalline silicon film is patterned by a photolithography technique and an etching technique, so that the node electrode 107 of the capacitive element C and the selection MISFET Qt
A first connection electrode 121 for connecting to either the source region or the drain region 116 is formed. The first connection electrode 121 includes a gate electrode 113 and a word line 113.
Are formed in a self-aligned manner with respect to each of.

Next, for example, a silicon oxide film is deposited by a CVD method, and an interlayer insulating film 124 is formed. Thereafter, an opening for exposing the surface of n-type semiconductor region 116 on the side connected to data line 128 is formed in interlayer insulating film 124.

Next, for example, a polycrystalline silicon film is deposited by the CVD method. Thereafter, the polycrystalline silicon film is patterned by photolithography and etching techniques,
As shown in FIG. 5, a second connection electrode 125 is formed.
The second connection electrode 125 is formed by self-alignment with both the gate electrode 113 and the word line 113.

Next, a first interlayer insulating film 127 is formed. The first interlayer insulating film 127 is formed by, for example, sequentially depositing a silicon oxide film and a BPSG film by a CVD method. After the film is deposited, the BPSG film is subjected to a reflow treatment, and the surface thereof is planarized.

Next, an opening is formed in the first interlayer insulating film 127. This opening connects the data line 128 to the selection MIS.
This is for connecting to the FET Qt. By forming this opening, the surface of the second connection electrode 125 is exposed.

Next, a first wiring to be the data line 128 is formed. This first wiring is formed of a tungsten film or an aluminum alloy film layer containing silicon and copper. In the case of a tungsten film, it is formed by a stacked film of a tungsten film formed by a sputtering method and a tungsten film formed by a CVD method.

Next, a second interlayer insulating film (not shown) is formed. This second interlayer insulating film is formed of three stacked silicon oxide films. Each of the lower and upper silicon oxide films is formed by a plasma CVD method using TEOS gas as a source gas. The silicon oxide film of the intermediate layer is formed of an SOG film.

Next, an opening is formed in the second interlayer insulating film (not shown), and thereafter, a column select signal line (YS) is formed.
L) is formed as a second wiring (not shown). This second
Is formed of a tungsten film or an aluminum alloy film containing silicon and copper. In the case of a tungsten film, it is formed by a stacked film of a tungsten film formed by a sputtering method and a tungsten film formed by a CVD method.

Next, a third interlayer insulating film 130 is formed. This third interlayer insulating film 130 is formed of three stacked silicon oxide films. Each of the lower and upper silicon oxide films is a plasma CV using TEOS gas as a source gas.
It is formed by method D. The silicon oxide film of the intermediate layer is formed of an SOG film.

Next, an opening (not shown) is provided in the third interlayer insulating film 130, and then the shunt word line 131 is formed.
Is formed. This third wiring 1
Reference numeral 31 is formed of an aluminum alloy film containing silicon and copper, or a tungsten film. When a tungsten film is used, for example, a stacked film of a tungsten film formed by a sputtering method and a tungsten film formed by a CVD method is used.

Next, a surface protection film 132 is formed. The surface protective film 132 is, for example, a PSG film, a plasma CVD
It is formed of a laminated film of a silicon nitride film formed by a method and a polyimide resin film. Through the above steps, the semiconductor device of the fifth embodiment shown in FIG. 17 is completed.

As described above, in the fifth embodiment,
A step of forming the plate electrode 105 with a tantalum-tungsten film, a step of depositing a tantalum oxide film on the tantalum-tungsten film 105 to form a charge storage insulating film 106, and a step of oxidizing the tantalum oxide film ,
Forming a second electrode 107 on the tantalum oxide film. According to this configuration, the charge storage insulating film 106 is formed of a single-layer tantalum oxide film, as in the first embodiment. Thereby, in the method of manufacturing a semiconductor device, a dielectric film having a high dielectric constant can be formed. Also,
Since the amount of stored charge per unit area can be increased, the planar layout area of the capacitor C can be reduced, and high integration of the semiconductor device can be achieved.

After the tantalum oxide film is deposited by the CVD method, an oxidation step is performed, so that in the region (weak spot) where the thickness of the tantalum oxide film is small, the tantalum / tungsten film underlying the tantalum oxide film is removed. Is selectively oxidized, and a tantalum oxide film is deposited on the surface of the tantalum-tungsten film. Due to the tantalum oxide formed in this oxidation step, the thickness of the region where the thickness of the tantalum oxide film formed by the CVD method is small is increased. Further, the growth of the tantalum oxide film deposited on the surface of the tantalum / tungsten film stops at a certain thickness. Therefore,
Variations in the thickness of the tantalum oxide film formed on the tantalum / tungsten film can be reduced. Accordingly, the withstand voltage of the charge storage insulating film 106 is improved, so that the reliability of the capacitor C can be improved.

Furthermore, by providing a capacitor C having a stacked structure in the pore 103 and forming the plate electrode 105 as the lowermost layer, the plate electrode 105 can be formed of a single layer film of a tantalum-tungsten film. Therefore, the number of steps can be reduced by an amount corresponding to the step of forming the oxidation resistant film.

As described above, the present invention has been specifically described based on the embodiments. However, it is needless to say that the present invention is not limited to the above-described embodiments and can be variously modified without departing from the gist thereof. .

For example, in the first to fifth embodiments,
Although a semiconductor device having a DRAM memory cell is shown,
The present invention can be applied to a semiconductor device having another capacitor.

In the second to fifth embodiments, a tantalum oxide film can be formed by forming a tantalum film on a tantalum / tungsten film by, for example, a sputtering method and then oxidizing the tantalum film. .

Instead of the tantalum-tungsten film, a laminated film is formed by laminating a tungsten film and a tantalum film from the lower layer side, and a tantalum oxide film is formed on the laminated film by, for example, a sputtering method. Can also be oxidized.

In the first to fourth embodiments, the example in which the lower electrode is formed of a laminated film of a polycrystalline silicon film and a tantalum-tungsten film has been described. However, in the present invention, the lower electrode is formed of a tantalum-tungsten film. It can also be formed as a single-layer film.

In the first to fifth embodiments, the charge storage insulating film is formed of a tantalum oxide film. However, according to the present invention, the charge storage insulating film 14 is formed by, for example,
It can also be formed of a metal oxide film made of any one of IVa or Va group elements or a combination of two or more elements. Since the oxide film of these metals has a higher dielectric constant than a single-layer film of a silicon oxide film or a stacked film of a silicon oxide film and a silicon nitride film, the amount of accumulated charges per unit area increases.
Therefore, the size of the capacitor C can be reduced, and high integration of the semiconductor device can be achieved.

In the first to fifth embodiments, an example is described in which the alloy containing the tantalum (a metal of either the IVa group or the Va group) is made of tungsten or molybdenum. Alternatively, tantalum can be contained in a metal film made of molybdenum and tungsten.

In the third to fifth embodiments, another metal film may be used instead of the tantalum / tungsten film. Furthermore, the method of Embodiment 1 may be applied to the method of forming the tantalum oxide film.

Also, an example in which a mixed gas of water vapor and hydrogen is used as an atmosphere for selectively oxidizing a metal film made of two kinds of metals (wet oxidation) has been described. An alloy film is selectively oxidized (dry oxidized) using an atmosphere for oxidizing a first metal constituting a metal film made of and reducing the second metal, for example, a mixed gas of carbon dioxide and carbon monoxide. You can also. Also, under conditions where the oxidation rate depends on the type of metal, oxygen or a mixed gas of oxygen and an inert gas can be used as the atmosphere. Alternatively, after oxidizing a metal oxide film deposited on a metal film made of two kinds of metals, only the second metal can be reduced by hydrogen annealing.

[0202]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

In the method for manufacturing a semiconductor device having a capacitor, high integration can be achieved.

In the method for manufacturing a semiconductor device, reliability can be improved.

In the method of manufacturing a semiconductor device, a dielectric film having a high dielectric constant can be formed.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is an essential part cross sectional view showing the semiconductor device in each manufacturing step.

FIG. 3 is an essential part cross sectional view showing the semiconductor device in each manufacturing step.

FIG. 4 is an essential part cross sectional view showing the semiconductor device in each manufacturing step.

FIG. 5 is a diagram showing a partial pressure ratio between water vapor and hydrogen when a charge storage insulating film is formed.

FIG. 6 is a diagram showing a partial pressure ratio between water vapor and hydrogen when a charge storage insulating film is formed.

FIG. 7 is a sectional view of a main part of a semiconductor device according to a third embodiment of the present invention.

FIG. 8 is an enlarged cross-sectional view of a main part of FIG.

FIG. 9 is an enlarged cross-sectional view of a main part of FIG. 7, showing the main part in each step.

FIG. 10 is an enlarged cross-sectional view of a main part of FIG. 7, showing the main part in each step.

FIG. 11 is an enlarged cross-sectional view of a main part of FIG. 7, showing the main part in each step.

FIG. 12 is an enlarged cross-sectional view of a main part of FIG.

13 is an enlarged cross-sectional view of a main part of FIG. 7, showing the main part in each step.

FIG. 14 is an enlarged cross-sectional view of a main part of FIG. 7, showing the main part in each step.

FIG. 15 is a cross-sectional view of a main part of a semiconductor device according to a fourth embodiment of the present invention, showing a part of a process by enlarging a region corresponding to the main part of FIG. 7;

FIG. 16 is an essential part cross sectional view showing a part of a step of the region shown in FIG. 15;

FIG. 17 is a sectional view of a principal part of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 18 is a cross-sectional view of a principal part showing the region shown in FIG. 17 in each step.

FIG. 19 is an essential part cross sectional view showing the region shown in FIG. 17 for each step;

FIG. 20 is an essential part cross sectional view showing the region shown in FIG. 17 for each step;

FIG. 21 is an essential part cross sectional view showing the region shown in FIG. 17 for each step;

FIG. 22 is an essential part cross sectional view showing the region shown in FIG. 17 for each step;

FIG. 23 is an essential part cross sectional view showing the region shown in FIG. 17 for each step;

24 is an essential part cross sectional view showing the region shown in FIG. 17 for each step;

FIG. 25 is an essential part cross sectional view showing the region shown in FIG. 17 for each step;

[Description of Signs] 1 ... p- type semiconductor substrate, 2 ... p-type well region, 3 ... p +
Type semiconductor region, 4 ... element isolation insulating film, 5 ... gate insulating film, 6 ... gate electrode, 7 ... n-type semiconductor region, 9 ... insulating film, 10 ... sidewall spacer, 11 ... polycrystalline silicon film, 12 ... Tantalum / tungsten film, 13 ... lower electrode, 14 ... charge storage insulating film, 15 ... upper electrode, 17 ...
Interlayer insulating film, 18 data lines.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Masayuki Nakata 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Central Research Laboratory, Hitachi, Ltd. (56) References JP-A-4-242970 (JP, A) JP-A Sho56 -161674 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/04 H01L 21/822 H01L 21/8242 H01L 27/108

Claims (24)

(57) [Claims] A first metal and a second gold are provided on a semiconductor substrate.
Forming a first electrode formed of a first film containing a metal
If, comprising the on the first electrode, the first metal oxide film induced
A step of depositing an electric conductor film and an atmosphere in which the first metal is oxidized and the second metal is not oxidized.
A step of oxidizing the first electrode in an atmosphere and a step of forming a second electrode on the dielectric film.
And a method of manufacturing a semiconductor device. Wherein said first metal is a metal belonging to IV a or V a, of the semiconductor device according to claim 1, wherein the second metal is characterized in that either Mo or W Production method. 3. An atmosphere in which the oxidation contains H ₂ O and H _2.
3. The semiconductor device according to claim 2, wherein the process is performed.
Manufacturing method of the device. 4. The method according to claim 1, wherein the first metal is Ta, and the second metal is Ta.
4. The half of claim 3, wherein the metal is W.
A method for manufacturing a conductor device. 5. The method according to claim 1, wherein the content of the first metal in the first film is
5. The method according to claim 4, wherein the amount is 50 atom%.
Of manufacturing a semiconductor device. 6. The method according to claim 6, wherein the first metal is Ta, and the second metal is Ta.
4. The metal according to claim 3, wherein the metal is Mo.
A method for manufacturing a semiconductor device. 7. A first metal and a second gold on a semiconductor substrate.
Forming a first electrode formed of a first film containing a metal
And oxidizing the first electrode in an atmosphere containing H ₂ O and H ₂ ,
The first metal without oxidizing the second metal
Forming a dielectric film by oxidizing; and forming a second electrode on the dielectric film.
And a method of manufacturing a semiconductor device. Wherein said first metal is a metal belonging to IV a or V a, of the semiconductor device according to claim 7, wherein the second metal is characterized in that either Mo or W Production method. 9. The first metal is Ta, and the second metal is Ta.
9. The half of claim 8, wherein the metal is W.
A method for manufacturing a conductor device. 10. The first metal is Ta;
9. The method according to claim 8, wherein the second metal is Mo.
Of manufacturing a semiconductor device. 11. A gate electrode and a soft
Of forming MISFET having source and drain
When, Electrically connected to one of the source and the drain;
A first film formed of a first film containing a first metal and a second metal
Forming one electrode; An insulating film made of the first metal oxide film is formed on the first electrode.
Depositing an electrical conductor film; An atmosphere in which the first metal is oxidized and the second metal is not oxidized.
Oxidizing the first electrode in an atmosphere; Forming a second electrode on the dielectric film.
And a method of manufacturing a semiconductor device. Wherein said first metal is a metal belonging to IV a or V a, of the semiconductor device according to claim 11, wherein the second metal is characterized in that either Mo or W Production method. Claim 13 The oxidation is H _Two O and H _Two Atmosphere including
13. The semiconductor according to claim 12, wherein:
Manufacturing method of body device. 14. The first metal is Ta;
14. The method of claim 13, wherein the second metal is W.
Of manufacturing a semiconductor device. 15. Content of a first metal in the first film
Is 50 atom%.
The manufacturing method of the semiconductor device described in the above. 16. The first metal is Ta;
14. The method according to claim 13, wherein the second metal is Mo.
Manufacturing method of the semiconductor device described above. 17. The first electrode and the source and drain
Having a step of forming an underlayer between any of the above.
The method of manufacturing a semiconductor device according to claim 13, wherein: 18. Resistance between the underlayer and the first electrode
Characterized by having a step of forming an oxidizing barrier layer.
The method of manufacturing a semiconductor device according to claim 17. (19) The barrier layer is made of TiN, Ti-W, T
iSi _Two , NiSi, CoSi _Two To be one of
The method for manufacturing a semiconductor device according to claim 18, wherein: 20. The first metal and the second metal are
It is a metal that oxidizes under various oxidation conditions
The method for manufacturing a semiconductor device according to claim 1. 21. Between the semiconductor substrate and the first film
Forming a polysilicon film on the substrate.
The method for manufacturing a semiconductor device according to claim 1. 22. The polysilicon film and the first film;
A barrier layer for reducing oxidation of the polysilicon film
22. The method according to claim 21, further comprising:
The manufacturing method of the semiconductor device described in the above. 23. A high melting point metal film is formed on the polysilicon film.
A step of forming a reside film.
A method for manufacturing a semiconductor device according to claim 21. 24. The high melting point metal is Ti, Ni, Co.
24. The half according to claim 23, which is any one of them.
A method for manufacturing a conductor device.