JP3149920B2 - MOS transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor and a method of manufacturing the same, and more particularly, to a MOS transistor having high single event upset resistance and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a semiconductor device having a MOS transistor, when used in a radiation environment such as outer space, the occurrence of a single event upset becomes a problem. Hereinafter, referring to the drawings, MOS transistors and
The occurrence of a single event upset in a MOS transistor will be described. FIG. 11 is a cross-sectional view of a substrate showing a configuration of a conventional ordinary n-channel MOS transistor (hereinafter, also referred to as an nMOS transistor; pMOS has the same meaning), and also shows a state when charged particles are incident. I draw. A conventional nMOS transistor 101A includes a semiconductor substrate 101 and a semiconductor substrate 101.
A p-type well region 102, an element isolation insulating film 103, a gate insulating film 104, a gate electrode 105,
n ⁺⁺ type source region 106, n ⁺⁺ type drain region 10
7 and an interlayer insulating film 108. In this specification, n
⁺⁺ means that the n-type impurity concentration is high, and p ⁺⁺ also means that the p-type impurity concentration is high. Source area 1
06 is connected to the wiring 110 via the contact wiring 109,
The drain region 107 is connected to a wiring 112 via a contact wiring 111. Note that FIG.
Then, the wiring 110 is set to a low potential (GND),
2 shows a case in which High potential (V _DD ) is set to 2. When charged particles enter a general nMOS transistor as shown in FIG. 11, electron-hole pairs are generated along the track 134. Here, at the bottom of the drain region 107 in the reverse bias state, the inside of the depletion layer becomes conductive due to the generated charges, and the electric field applied to the depletion layer extends in a columnar direction toward the p-type well region with a low impurity concentration. Applied. This extended electric field region (funneling region 135)
Are collected by the electric field of the drain region 107 and flow to the wiring 112 through a path 137 passing through the drain region 107 and the contact wiring 111. Accordingly, the potential of the node connected to the wiring 112 changes, and a soft error such as bit inversion, that is, a single event upset occurs.

In order to suppress the occurrence of the single event upset, various structures using impurity profile engineering have been described. For example, JP-A-1-130561 and JP-A-4-3920 attempt to suppress the extension of a depletion layer by forming a high-concentration impurity layer having a conductivity type opposite to that of a source / drain region in a well region or a bottom portion. Is described. In addition, Japanese Unexamined Patent Publication
19361 also describes a method in which a high-concentration impurity layer having a conductivity type opposite to that of the source / drain region is formed immediately below the source / drain region to suppress the extension of the depletion layer. Further, Japanese Patent Application Laid-Open No. 2-208965 describes a technique in which a high-concentration impurity layer of the same conductivity type as a source / drain region is formed in a relatively deep region. In Japanese Patent Application Laid-Open Nos. 2-72663 and 4-147676, an electron-hole pair causing a single event upset is prevented from flowing into the source / drain region.
A dummy drain region is provided below the source / drain region.

[0004]

SUMMARY OF THE INVENTION However, Japanese Patent Laid-Open Publication No. 1-1
30561, JP-A-4-3920, and JP-A-3-19
In the MOS transistor denoted by reference numeral 361, the high-concentration impurity layer has a conductivity type opposite to that of the source / drain regions. Therefore, when the impurity concentration is sufficiently high and formed immediately below the source / drain regions, the capacitance of the pn junction is reduced. And adversely affect the processing speed. On the other hand, if it is formed away from the source / drain regions, the charge collection by funneling directly below the source / drain regions cannot be prevented. Also, the MOS transistor disclosed in Japanese Patent Application Laid-Open No. 2-208965 is formed separately from the source / drain region,
The charge collection by funneling just below the source / drain regions cannot be prevented. Even if it is formed immediately below the source / drain regions, the electric charge cannot be so-called “pulled out” because the potential is not fixed, and the effect is produced when electron-hole pairs are generated at a concentration higher than the impurity concentration. Will be gone. Also, JP-A-2-72663 and JP-A-4-14.
In the MOS transistor shown by 7676, it is desired that the position where the dummy drain region is formed is closer to the source / drain region in order to achieve a more effective effect.

[0005] In view of the circumstances described above, an object of the present invention is to provide an M-type communication system in which the occurrence of a single event upset is suppressed.
An object of the present invention is to provide an OS transistor and a manufacturing method thereof.

[0006]

In order to achieve the above object, a MOS transistor according to the present invention is provided in a well region of a first conductivity type formed in a semiconductor substrate.
Source / drain regions are formed below the channel region.
In a MOS transistor having a dummy drain region of the same conductivity type as the source / drain region formed only below the source / drain region except for one of the two, the upper interface of the dummy drain region is more predetermined than the lower interface of the source / drain region. Is located at least below the gap and within 1.5 μm from the top surface of the semiconductor substrate, and a predetermined gap is
Empty around drain region when reverse bias voltage is applied
The depletion layer contacts the depletion layer around the dummy drain region,
Depletion layer around the source region and around the dummy drain region
This is the interval that does not contact the depletion layer of the dummy drain region.
Is electrically connected to the dummy drain region and the well region.
Dummy drain so that the pn junction between
The same as the dummy drain region, which fixes the potential of the drain region.
It is characterized by having a two-conductivity-type connection . The predetermined interval is, for example, 0.6 μm.

A dummy drain region of an impurity semiconductor of the same conductivity type as a source / drain region is a p-type dummy drain region when the source / drain region is a p-type, and a dummy drain region when the source / drain region is an n-type. This indicates that the region is an n-type dummy drain region. When the MOS transistor is an n-channel type, the dummy drain region is fixed at the VDD potential (High potential). When the MOS transistor is a p-channel type, the dummy drain region
It is fixed at D potential (Low potential, ground potential). A MOS transistor according to the present invention is formed on a semiconductor substrate.
In the first conductivity type well region and the second conductivity type well region, n
Channel MOS transistor and p-channel MOS transistor
Transistors are formed respectively, and the first conductivity type and
A source / drain region is formed in the well region of the second conductivity type.
Source drain except below the channel region
Formed only below the source and drain regions, and
Flip case of having a CMOS structure twin wells with dummy drain region of the conductivity type, the upper dummy drain region
The interface is longer than the lower interface of the source / drain region by a predetermined distance.
At least 1.5 m below the top of the semiconductor substrate.
Within a predetermined interval, a reverse bias voltage is applied to the drain region.
Depletion layer and dummy around drain region when pressure is applied
The depletion layer around the drain region is in contact with the source region
The depletion layer around and the depletion layer around the dummy drain region
Not electrically connected to the dummy drain region
And a pn junction between the dummy drain region and the well region
Voltage of the dummy drain region so that
Connection of the same second conductivity type as the dummy drain region to be fixed
And a dummy drain region may be electrically connected to a well region of the same conductivity type in the twin well.

In an ordinary MOS transistor, the electric charge in the drain depletion layer and the electric charge in the funneling cylinder are collected by drift during several tens ps to several hundreds ps after the injection of charged particles. Even after the charge collection by the drift ends, the charge collection by the diffusion continues for several ns to several tens ns. Among these charge collecting mechanisms, the funneling component contributes most to the change in the potential of the node. According to the present invention, most of the charge collected by this funneling is applied to the V drain via the dummy drain region.
Since the current flows to the _DD terminal or the GND terminal, it is possible to prevent the potential of the drain region from fluctuating to cause the bit inversion, thereby suppressing the occurrence of the single event upset.

A dummy drain region of a MOS transistor according to the present invention is formed immediately below a drain junction.
In addition, the configuration is different from that of a conventional so-called deep n-well for noise suppression in that it is not formed under the channel. That is, the deep n-well is formed at the “bottom” of the p-type well region, while the dummy drain region is formed at a depth where the depletion layer of the drain region and the depletion layer of the dummy drain region contact each other at the time of reverse bias. And is formed “inside” the p-type well region. While the deep n-well is formed so as to cover the entire p-type well region, the dummy drain region is formed only below the source / drain region. The reason why the dummy drain region is not formed under the channel is as follows. First, when the dummy drain region is formed over the entire element region, the potential of the channel region becomes floating, and various problems occur as seen in the substrate floating effect of the thin film SOI device. Second, since the dummy drain region is formed in a very shallow region of the substrate, if formed below the channel, it may affect the sub-threshold characteristics of the transistor, the short channel effect, and the like.

A first method of manufacturing a MOS transistor according to the present invention is a method of manufacturing a MOS transistor according to the present invention, wherein the step of forming a p-type well on a semiconductor substrate is followed by a step of forming a p-type well. Forming a dummy drain region by covering a channel formation region on the well with a photoresist film mask and implanting n-type impurity ions, and then forming a dummy drain region
After the region formation step, the p-type well is formed on the semiconductor substrate.
Photoresist exposing predetermined area of isolated element isolation region
A step of forming a film mask, and further, n-type impurity ions
Implanted and electrically connected to the dummy drain region
And a connecting portion forming step of forming

After the step of forming the dummy drain region, a step of forming a photoresist film mask exposing a predetermined region of the element isolation region formed in the semiconductor substrate in the p-type well, and further implanting n-type impurity ions. Forming a connection portion that is electrically connected to the dummy drain region. In this case, the shape of the photoresist film mask covers the source, drain, and channel regions of the MOS transistor and the periphery of each region, and the predetermined region is a region for forming a connection portion. Furthermore, after the connecting portion forming step, a gate insulating film and a gate electrode are formed, and further,
implanting n-type impurity ions to form a source / drain region and a high-concentration impurity region formed on the connection portion and having a high-concentration impurity, and then forming an interlayer insulating film; Forming a contact wiring connected to the high-concentration impurity region, and further forming a wiring connected to the contact wiring on the interlayer insulating film.
In the first invention method, preferably, the n-type impurity ion is an arsenic ion.

Further, a second invention method of a method of manufacturing a MOS transistor according to the present invention is a method of manufacturing a MOS transistor according to the present invention, which comprises the step of forming an n-type well on a semiconductor substrate, forming a dummy drain region by covering a channel formation region on the n-type well with a photoresist film mask and implanting p-type impurity ions, and then forming a dummy drain region;
After the in-region formation process, the semiconductor substrate
A photoresist layer exposing a predetermined region of the formed element isolation region.
Forming a resist film mask, further, p-type impurity Lee
Inject ON and electrically connect to dummy drain region
And a connecting part forming step of forming a connecting part .

In this case, the shape of the photoresist film mask covers the source, drain and channel regions of the MOS transistor and the periphery of each region, and the predetermined region is a region for forming a connection portion. Further, after the connecting portion forming step, a gate insulating film and a gate electrode are formed, and p-type impurity ions are further implanted to form a source / drain region and a high-concentration impurity formed on the connecting portion and having a high concentration of impurities. Forming an impurity region, then forming an interlayer insulating film, further forming a contact wire connected to the high-concentration impurity region, and further forming a wire connected to the contact wire on the interlayer insulating film. And a step.

A third aspect of the method of manufacturing a MOS transistor according to the present invention is a method of manufacturing a MOS transistor having a twin-well CMOS structure as described above, wherein the p-type well formed on a semiconductor substrate is provided. And n
Forming a p-type well, covering the channel formation region on the p-type well and the n-type well with a photoresist film mask, and further implanting n-type impurity ions,
Forming a dummy drain region in the p-type well connected to the type well, then-channel on n-type well
Covering the active region and the p-type well with a photoresist film mask
Further, by implanting p-type impurity ions,
Dummy drain region connected to the n-type well in the n-type well
And a step of forming the same.

Regarding the setting of the energy of each ion implantation in the first to third invention methods, usually, a depletion layer formed around the dummy drain region is in contact with a depletion layer formed around the drain region. It is set in consideration of the impurity distribution in the depth direction so that a state is obtained and the depletion layer around the dummy drain region does not contact the depletion layer in the source region.

[0016]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Embodiment 1 Embodiment 1 is an embodiment of the present invention. FIG.
FIG. 2 is a plan view showing the configuration of the MOS transistor of the present embodiment, FIG. 2 is a side sectional view taken along line AA ′ in FIG. 1, FIG. 3 is a side sectional view taken along line BB ′ in FIG. FIG. 4 shows the line C in FIG.
It is side sectional drawing of -C '. The MOS transistor 1A of the present embodiment has a semiconductor substrate 1 and a p-type well region 2, an element isolation insulating film 3, a gate insulating film 4, Gate electrode 5, n ⁺⁺ type source region 6, also n
^++- type drain region 7 and interlayer insulating film 8. The source region 6 is connected to the wiring 1 via the contact wiring 9.
0, and the drain region 7 is connected to a wiring 12 via a contact wiring 11. The p-type well region 2 is connected to a well 17 for supplying a well potential through the p ⁺⁺ -type impurity regions 13 and 14 and the contact wires 15 and 16.
It is connected to the. This embodiment is an n-channel type MOS
It is a transistor, and the potential of the wiring 17 is always the GND potential. Further, the MOS transistor of this embodiment is
N ⁺ -type dummy drain regions 18 and 19 are provided below the source region 6 and the drain region 7, and this point is greatly different from the conventional MOS transistor 101A. The upper interfaces of the dummy drain regions 18 and 19 are located at predetermined intervals, for example, 0.6 μm or more below the lower interfaces of the source region 6 and the drain region 7 and within 1.5 μm from the upper surface of the semiconductor substrate. Dummy drain region 18
^Are n ⁺⁺ -type impurity regions 20 and contact wires 21
Through the wiring 22 and the dummy drain region 19
It is connected to a wiring 25 via an n ⁺⁺ -type impurity region 23 and a contact wiring 24, respectively. The wiring 22 and the wiring 25 are always connected to a High potential (V _DD ). The pn junction between the dummy drain regions 18 and 19 and the p-type well region 2 is reverse biased, and the depletion layers 26 and 27
It always extends in all directions.

In FIGS. 2 to 4 shown in this embodiment, the wiring 10 is set to a low potential (GND), and the wiring 12 is set to a high potential.
The case where the potential (V _DD ) is set is shown. At this time, the pn junction of the drain region 7 is reverse-biased, and the depletion layer around the drain region 7 is extended, so that the dummy drain region 19
Is in contact with the depletion layer 27 around. On the other hand, since the depletion layer of the source region 6 does not extend, it does not come into contact with the depletion layer 26 around the dummy drain region 18. That is, the depletion layer formed around the dummy drain region is Hi
There is no contact with the depletion layer of the source / drain region at the time of the gh potential and with the depletion layer of the source / drain region at the time of the low potential. Note that the impurity concentration of each region is about 10 ¹⁶ to 10 ¹⁷ cm ^{−3 in} the p-type well
⁺ Type dummy drain regions 18 and 19 are 10 ¹⁸ to 10 ¹⁹
cm ⁻³ , n ⁺⁺ -type drain regions 7, 8, p ⁺⁺ -type impurity regions 13, 14, and n ⁺⁺ -type impurity regions 20, 2
3 is about 10 ²⁰ to 10 ²¹ cm ⁻³ .

Next, a method of manufacturing the MOS transistor 1A will be described with reference to FIGS. 5 to 7 are cross-sectional views of the substrate in each manufacturing process of the MOS transistor 1A, and are cross-sectional views taken along line CC 'in FIG. First,
An element isolation insulating film 3 is formed on a semiconductor substrate 1, and boron ions are implanted to form a p-type well 2. Next, MOS
A region for forming a channel of the transistor is covered with a photoresist film 28 (FIG. 5), and first arsenic ion implantation is performed to form dummy drain regions 18 and 19. The energy of the first arsenic ion implantation may be about 80 to 150 keV, and the dose may be about 5 × 10 ¹³ cm ^{−2 to} 5 × 10 ¹⁴ cm ⁻² . Subsequently, as shown in FIG. 6, the entire element formation region (channel, source, and drain regions) of the MOS transistor is covered with a photoresist film, and a contact wiring for supplying a potential to the dummy drain regions 18 and 19 is formed. A second arsenic ion implantation is performed exposing only the region. The energy of the second arsenic ion implantation is 50 to 10
At 0 keV, the dose is about the same as that of the first arsenic ion implantation. The arsenic ion-implanted regions 30 and 31 extend the dummy drain regions 18 and 19 toward the substrate surface,
It serves to connect to n ⁺⁺ -type impurity regions 20 and 23 formed in a later step. Next, the gate insulating film 4 and the gate electrode 5 are formed in the same manner as in the related art. Furthermore,
The photoresist film 29 is formed to form the photoresist film 3
2 and 33 are formed (FIG. 7), and a third arsenic ion implantation is performed to form a source region 6, a drain region 7, and n ⁺⁺ -type impurity regions 20 and 23. The energy of the third arsenic ion implantation is 30 to 70 keV and the dose is 2 × 10
¹⁵ cm ^{-2 to} 3 × 10 ¹⁵ cm ^-2 After this, FIG.
As shown in FIG.
4. When the wirings 22 and 25 are formed, the MOS transistor 1A is obtained. Regarding the setting of the energy of each arsenic ion implantation in the above manufacturing method, when a voltage is applied to the source / drain regions, the depletion layer 27 around the dummy drain region 19 comes into contact with the depletion layer of the drain region 7, The impurity distribution in the depth direction due to the implantation is set so as to form a dummy drain region in which the depletion layer 26 around the dummy drain region 18 does not contact the depletion layer of the source region 6.

The other parts such as the p ⁺⁺ -type impurity regions 13 and 14 are formed by a normal manufacturing method, that is, a conventional manufacturing method. Although omitted in this embodiment, channel ion implantation, formation of an LDD structure, silicidation of source / drain regions, and the like are also performed by a normal manufacturing method. In this embodiment, the case of an n-channel MOS transistor has been described as an example. However, even in the case of a p-type MOS transistor, exactly the same structure and manufacturing method can be achieved by exchanging the conductivity type of each region. Obtainable. p-type MO
In the case of the S transistor, the dummy drain region is of p ⁺ type and is always connected to the GND terminal.

The operation of the MOS transistor 1A of this embodiment will be described below. When a normal MOS transistor is used in a radiation environment such as outer space, a malfunction occurs due to the incidence of charged particles. This malfunction occurs when charges generated by the incidence of charged particles are collected by a mechanism such as a funneling phenomenon, and the potential of a node connected to the drain is changed. On the other hand, in the MOS transistor of this embodiment, such a change in the potential of the node can be suppressed. This will be described below with reference to FIG. FIG. 8 is a cross-sectional view of a substrate showing an operation when charged particles enter the line CC ′ shown in FIG. 1 (see FIG. 4 as a cross-sectional view of the substrate). When charged particles are incident, electron-hole pairs are generated along the tracks 34. Here, at the bottom of the dummy drain region 19 in the reverse bias state, the inside of the depletion layer becomes conductive due to the generated charges, and the electric field applied to the depletion layer extends in a columnar direction toward the p-type well region having a low impurity concentration. Applied.
This extended electric field region, that is, the funneling region 35
Are collected by the electric field of the dummy drain region, and the dummy drain region 19 and the n ⁺⁺ type impurity region 2
3, flows into the _VDD terminal through a path 36 passing through the contact wiring 24 and the wiring 25. In the conventional n-channel MOS transistor, a funneling region is generated at the bottom of the drain region 7 due to the incidence of charged particles, and electrons are collected in the drain region 7. Soft errors such as inversion (single event upset) occur. on the other hand,
In the MOS transistor of the present embodiment, although a part of the generated charge is collected in the drain region 7, most of the charge collected by the funneling phenomenon passes through the dummy drain region 19 and has a stable potential V _DD terminal. , The potential of the node connected to the drain region 7 does not change. In addition, when electric charge is incident on the source region 6,
Even if electrons are collected, the potential of the node does not change, so that malfunction does not occur. Therefore, when the source / drain of the MOS transistor is fixed, the source region 6
The dummy drain region 18 below is not required. Source·
When the drain is not fixed, for example, when forming a transfer gate or forming the base of a gate array, it is necessary to form a dummy drain region below both the source and drain regions as in the present embodiment. There is.

Embodiment 2 This embodiment is an example of a MOS transistor having a twin-well CMOS structure. FIG. 9 is a plan view showing the configuration of the MOS transistor according to the present embodiment.
0 is a cross-sectional view of the substrate taken along line DD ′ in FIG. In FIG. 10, a depletion layer at the pn junction is omitted for easy understanding of the configuration. The MOS transistor of the present embodiment is different from the MOS transistor 1A of the embodiment in that the potential of the dummy drain region is fixed by connecting to a well of the same conductivity type instead of a dedicated contact wiring. . In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

According to the present embodiment, since the wiring for fixing the potential of the dummy drain region and the contact wiring are not required, it is not necessary to secure an extra wiring region, and the integration degree can be improved. . In the MOS transistor of the present embodiment, as shown in FIGS. 9 and 10, an n-channel MOS transistor is formed on the p-type well region 2, and the p-type well region 2 is
It is adjacent to an n-type well region 37 for forming an S transistor (not shown). The n-type well region 37 is
It is connected to the V _DD terminal via a contact wiring (not shown). Under the source region 6 and the drain region 7, n ⁺ -type dummy drain regions 18 and 19 (the dummy drain region 18 is not shown in FIG. 10) are formed as in the embodiment. Dummy drain regions 18 and 19 are dummy drain-well connection regions 38 formed by partially opening the element isolation insulating film 3,
The end extends to 39 (FIG. 9), where it is connected to the n-type well region 37. The n-type well region is always connected to the V _DD terminal, and the dummy drain regions 18 and 19 are always fixed at the V _DD potential.

The operation of the MOS transistor of the present embodiment is substantially the same as that of the MOS transistor of the first embodiment. Electrons generated by the incidence of charged particles are collected in the dummy drain region 19 and the n-type well region 37 is formed. Flows to the V _DD terminal via According to the present embodiment, the same effects as those of the first embodiment can be obtained.

[0024]

According to the present invention, a dummy drain region, which is an impurity semiconductor of the same conductivity type as the source / drain region, is provided below the source / drain region at a predetermined depth. The predetermined depth position is such that the upper surface of the dummy drain region is slightly below the bottom surface of the depletion layer formed when a reverse bias voltage is applied to the drain region, and within 1.5 μm from the upper surface of the source / drain region. Position. As a result, most of the charge collected by the funneling flows to the _VDD terminal or the GND terminal via the dummy drain region, thereby preventing the potential of the drain region from changing and causing bit inversion. The occurrence of a single event upset is suppressed.

[Brief description of the drawings]

FIG. 1 is a plan view showing a configuration of a MOS transistor according to a first embodiment.

FIG. 2 is a side sectional view taken along line A-A 'of FIG.

FIG. 3 is a side sectional view taken along line B-B 'of FIG. 1;

FIG. 4 is a side sectional view taken along line C-C ′ of FIG. 1;

FIG. 5 is a cross-sectional view of the substrate showing a manufacturing step of the MOS transistor according to the first embodiment, which is a cross-sectional view taken along the line CC ′ of FIG. 1;

FIG. 6 is a cross-sectional view of the substrate, showing a manufacturing step of the MOS transistor according to the first embodiment, taken along line CC ′ of FIG. 1;

FIG. 7 is a cross-sectional view of the substrate showing a manufacturing step of the MOS transistor according to the first embodiment, which is a cross-sectional view taken along line CC ′ of FIG. 1;

FIG. 8 is a cross-sectional view of a substrate showing an operation when a charged particle is incident on line CC ′ shown in FIG. 1;

FIG. 9 is a plan view illustrating a configuration of a MOS transistor according to a second embodiment.

10 is a cross-sectional view of the substrate taken along line D-D 'in FIG.

FIG. 11 is a cross-sectional view of a substrate illustrating a configuration of a conventional n-channel MOS transistor, and also illustrates a state when charged particles are incident.

[Explanation of symbols]

101A nMOS transistor 101 semiconductor substrate 102 p-type well region 103 element isolation insulating film 104 gate insulating film 105 gate electrode 106 n ⁺⁺ type source region 107 n ⁺⁺ type drain region 108 interlayer insulating film 109 contact wiring 110 wiring 111 contact Wiring 112 Wiring 134 Trace 135 Funneling region 137 Path 1A MOS transistor 1 Semiconductor substrate 2 P-type well region 3 Element isolation insulating film 4 Gate insulating film 5 Gate electrode 6 n ⁺⁺ source region 7 n ⁺⁺ drain region 8 interlayer insulating film 9 contact wiring 10 wiring 11 contact wiring 12 wiring 13, 14 p ⁺⁺ type impurity regions 15 and 16 contact wiring 17 wiring 18 and 19 dummy drain region 20 n ++ type impurity region 21 of the contact wires 23 n + -Type impurity regions 24 contact the wiring 25 wiring 26, 27 the depletion layer 28 a photoresist film 29 a photoresist film 32 a photoresist film 34 track 35 funneling region 36 path 37 n-type well region 38 and 39 dummy drain of - well connection region

Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/78

Claims (9)

(57) [Claims] A first conductive type formed on a semiconductor substrate;
Source / drain regions of second conductivity type are formed in the well region
In a MOS transistor formed only under the source / drain region except under the channel region and having a dummy drain region of the same conductivity type as the source / drain region, the upper interface of the dummy drain region is A reverse bias voltage was applied to the drain region at a predetermined interval below the lower interface by a predetermined interval or more and within 1.5 μm from the upper surface of the semiconductor substrate .
Depletion layer around drain region and dummy drain region
Depletion layer in contact with the surrounding depletion layer and around the source region
And the depletion layer around the dummy drain region
Yes, connected to dummy drain region and the electrical, dummy drain
Pn junction between region and well region is reverse biased
Fix the potential of the dummy drain region
A MOS transistor having a connection portion of the same second conductivity type as a rain region . 2. The MOS transistor according to claim 1, wherein the predetermined interval is 0.6 μm. 3. A first conductivity type wafer formed on a semiconductor substrate.
The n-channel type MO is provided in the
S transistor and p-channel MOS transistor
Each of which has a first conductivity type and a second conductivity type.
Source / drain regions are formed in the well region,
Except below the source / drain region except below the channel region
Formed with the same conductivity type as the source / drain regions.
A MOS transistor having a twin-well CMOS structure having a drain region, wherein the upper interface of the dummy drain region is
Lower than the lower interface by more than a predetermined distance and the semiconductor
A reverse bias voltage was applied to the drain region at a predetermined interval within 1.5 μm from the upper surface of the substrate .
Depletion layer around drain region and dummy drain region
Depletion layer in contact with the surrounding depletion layer and around the source region
And the depletion layer around the dummy drain region
Yes, connected to dummy drain region and the electrical, dummy drain
Pn junction between region and well region is reverse biased
Fix the potential of the dummy drain region
It has a connection portion of the same second conductivity type as the rain region, and the dummy drain region is electrically connected to a well region of the same conductivity type in the twin well.
M OS transistor that. 4. The method for manufacturing a MOS transistor according to claim 1, wherein a step of forming a p-type well on a semiconductor substrate is followed by a step of forming a p-type well.
Forming a dummy drain region by covering the channel formation region on the mold well with a photoresist film mask and implanting n-type impurity ions, and then, after the dummy drain region formation step, the p-type well
Of the device isolation regions formed on the semiconductor substrate,
Forming a photoresist film mask exposing the region
And further implant n-type impurity ions to form a dummy drain region.
Forming a connection portion for forming a connection portion electrically connected to the MOS transistor. 5. After the connecting portion forming step, a gate insulating film and a gate electrode are formed, and further, n-type impurity ions are implanted to form a source / drain region and a high concentration impurity formed on the connecting portion. Forming a high-concentration impurity region having, and then forming an interlayer insulating film, further forming a contact wiring connected to the high-concentration impurity region, and further forming a wiring connected to the contact wiring on the interlayer insulating film. 5. The method for manufacturing a MOS transistor according to claim 4 , further comprising the step of: 6. The method according to claim 4, wherein the n-type impurity ions are arsenic ions. 7. The method for manufacturing a MOS transistor according to claim 1, wherein the step of forming an n-type well on a semiconductor substrate is followed by a step of forming an n-type well.
Forming a dummy drain region by covering the channel formation region on the mold well with a photoresist film mask and implanting p-type impurity ions, and then, after the dummy drain region formation step, the n-type well
Of the device isolation regions formed on the semiconductor substrate,
Forming a photoresist film mask exposing the region
And further implant p-type impurity ions to form a dummy drain region.
Forming a connection portion for forming a connection portion electrically connected to the MOS transistor. 8. After the connecting portion forming step, a gate insulating film and a gate electrode are formed, and further, p-type impurity ions are implanted to form a source / drain region and a high-concentration impurity formed on the connecting portion. Forming a high-concentration impurity region having, and then forming an interlayer insulating film, further forming a contact wiring connected to the high-concentration impurity region, and further forming a wiring connected to the contact wiring on the interlayer insulating film. 8. The method of manufacturing a MOS transistor according to claim 7 , further comprising a step of forming the MOS transistor. 9. The method for manufacturing a MOS transistor according to claim 3, wherein a p-type well and an n-type well formed on a semiconductor substrate are formed, and a channel formation region and n on the p-type well are formed. covering the mold wells in the photoresist film mask, further, by implanting n-type impurity ions, forming a dummy drain region connected to the n-type well in a p-type well, then the channel on n-type well Forming region and p-type wafer
Mask with a photoresist film mask, and further add a p-type impurity.
By implanting ions, a connection to the p-type well is made.
Forming a me-drain region in the n-type well .