JP3153294B2 - Address counter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address counter for controlling an address of a buffer memory or the like.

[0002]

2. Description of the Related Art In a communication path connecting computer systems or peripheral devices thereof, in order to absorb a data transfer speed difference between conventional devices and a data transfer speed difference due to a difference in transmission mode for each communication line, a general method is used. The buffer memory is used in the interface circuit. The buffer memory only needs to transmit information transparently, and generally has only to have a serial read / write function. That is, the input data is temporarily held in the same form and data order, and read again in the same form. If data processing is necessary, the processing is performed in a device connected to the transmission destination of the buffer memory.

[0003]

SUMMARY OF THE INVENTION In a conventional device,
When trying to convert the data structure, it was necessary to add hardware for this after the input data buffer of the interface circuit. For example, when orthogonally transforming a secondary image of raster data by spatially dividing the image into blocks, a line memory and an address conversion mechanism for converting the raster data into block data are required.

FIG. 10 is a schematic diagram showing a process of spatially dividing a secondary image into blocks and performing orthogonal transformation. Each block is composed of Y pixels in the main scanning direction and X pixels in the sub scanning direction. The entire image data is composed of N blocks in the main scanning direction and M blocks in the sub-scanning direction.

[0005] In the figure, (a) shows the scan direction of normal raster data, and the dashed arrow shows the scan direction. The sub-scanning direction is from top to bottom in the figure.
(B), (c) show the scanning order at the time of blocking.
Which of the scan orders shown in (b) and (c) will depend on the data processing after blocking. In any of the cases shown in (b) and (c), the memory is once stored for X lines and then divided into blocks. Therefore, a line memory and an addressing mechanism for this purpose are required in addition to the buffer mechanism of the interface circuit, and there has been a problem that the circuit becomes complicated and the cost increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to calculate the count output output from each counter and convert the count output into a one-dimensional address to store the count output. An object of the present invention is to provide an address counter which can easily perform common processing from data storage processing to data structure conversion processing for the means with the same hardware. In addition, by outputting the address obtained by adding the address converted and output after the mode signal switching and the retained address to the address bus, data modification and the like accompanying the mode switching can be prevented beforehand, and the correct access address is always output. Is to provide an address counter that can do this.

[0007]

According to a first aspect of the present invention, there is provided a counter means in which a plurality of counters respectively counting a plurality of addresses set in a storage means are cascaded, and a connection between the plurality of counters. It has a changing means for changing the order based on a mode signal inputted from the outside, and an address converting means for converting a combination of outputs of the respective counters of the counter means into a one-dimensional address.

According to a second aspect of the present invention, there is provided a holding means for holding an address output from the address conversion means immediately before switching of a mode signal, an address output from the address conversion means after the mode signal is switched, and the holding. Means for outputting an address obtained by adding the address held by the means to the address bus.

[0009]

[0010]

[0011]

[0012]

[0013]

FIG. 1 is a block diagram for explaining a configuration of an address counter according to an embodiment of the present invention.

In FIG. 1, reference numeral 301 denotes a data latch / selector, which is input from a data bus 306, and performs a latch of a base number of a counter group described below and a bus select at the time of directly loading data. 307 is a write signal. 302
a to 302d are counters 101a to 101d shown in FIG.
This is a counter in M, X, N, and Y corresponding to 101d. 303 is a counter (counter module) 302a
A conversion circuit (encoder) for scalarizing the output of 〜302d, and this output 323 is a buffer (not shown)
Address bus. 304 is an address decoder,
The chip select 309 and the address bus 308 are decoded, and the select signal line groups 310a to 310d and 313a to 313d are used when accessing each counter group and data latch.
Assert the corresponding one of A toggle flip-flop 305 is a mode change signal (MODE)
CHG) 315 in response to the pulse, and outputs a counter mode signal (CNT MODE) 316. This counter mechanism operates a counter mode signal (CNT).
MODE) 316, the mode is switched between the raster scan mode and the block scan mode.

Reference numeral 311 denotes a buffer end signal (B) for performing a clear operation when the counter reaches the buffer end.
UF END). 312a to 312d are input data buses to the respective counters 302a to 302d. 31
4 is a clock signal for counting, and 315 is a mode change signal, which switches between a raster scan mode and a block scan mode for each pulse. Reference numerals 317 to 320 denote carry outputs to the respective counters. When they are active, they carry out counting and carry outputs of their own. 319 is output as a block end signal (BLK END), which indicates that the address is the end point for each X line. When performing blocking, this detection is performed because raster data must be buffered in units of X lines. Each counter 302a
To 302d have two carry inputs and a counter enable input, and correspond to the count mode in FIG.
The connection state of the counter is switched as shown in FIG.

321a to 321d are the outputs of the respective counters,
Reference numerals 322b to 322d indicate base number information of the counters 302b to 302d. The conversion circuit (encoder) 303 maps this value to the buffer address space of each counter output.

In the address counter configured as described above, each counter (30) is controlled in accordance with an input clock.
2a to 302d), the address conversion means (conversion circuit (encoder)) 303 starts the address counting of the desired radix, and outputs the output of each counter of the counter means to a desired one-dimensional signal based on a mode signal externally input. The address is converted to an address and the access address is output to the address bus.

The base of each counter is configured to be independently settable, and generates access addresses corresponding to various data processing.

Further, the address output from each counter immediately before the mode signal switching is held in the holding means (address register 703 described later), and the adding means (adder 705 described later) is operated by each counter immediately after the mode signal switching. And the address held in the holding means is added to output the access address to the address bus, thereby generating a correct access address.

FIG. 2 shows the counters 302a to 302a shown in FIG.
It is a state transition diagram which shows the address translation processing by 302d. The entire image is composed of blocks in the main scanning direction (horizontal) N and sub-scanning direction (vertical) M, and each block is composed of horizontal Y pixels and vertical X pixels. Assuming that each pixel corresponds to one location (one word) in the buffer memory, a buffer capacity of M × N × X × Y words is required as a whole.
Expanding each pixel into the address space is (M, X,
It can be considered that a four-dimensional vector (N, Y) is expanded into a scalar value. This is realized by cascade-connecting four counters of M, X, N, and Y bases, encoding each counter output by the following configuration, and mapping it to a continuous memory address.

In the drawing, reference numerals 101a to 101d denote M, X, N, and Y-based counters, respectively, which operate in response to a clock 102. Each of the counters 101a to 101d generates a carry for the upper counter, and the upper counter enables the count operation only when the carry from the lower stage is enabled.
And generate your own carry. (L1) is a counter connection corresponding to the scan (raster scan) shown in (a) shown in FIG. That is, the number of blocks is counted for each Y pixel count, and the number of lines (X) is counted for each N block count. Then, the vertical blocks (M) are counted every X line count. (L2) shown in FIG. 2 corresponds to (B) shown in FIG. 10 and (L2) shown in FIG.
3) is a counter connection corresponding to the scan of (c) shown in FIG. (L2) increments the line direction (X) in the horizontal direction for every Y pixel count, and increments the number of horizontal blocks (N) when reaching the vertical block boundary (the boundary between block 00 and block 01). ,
Move to the adjacent block in the horizontal direction. Blocks 00,01,0
When the scanning of 2,..., 0 (n-1) is completed, the number of blocks in the vertical direction is incremented, and the process proceeds to block 01.

The line L3 is a case where the scanning direction in each block is reversed with respect to the line L2, and the counter 101b
This is the case where the connection between (X) and the counter 101d (Y) is reversed. As described above, the raster-to-block scan conversion on the buffer address map can be realized by changing the carry connection pattern of the four counters. The mapping of each counter output onto the memory address may be performed by converting each counter output and converting it into a scalar.

FIG. 3 shows the counters 302a to 302a shown in FIG.
It is a detailed block diagram explaining the structure of 302d.

In the figure, reference numeral 401 denotes a counter main body, which performs counting in accordance with a clock signal 314. This counter has a synchronous load terminal SYNC LD, an asynchronous load terminal ASYNC LD, and a synchronous load terminal SYNC L.
D is connected to the gate 402, and when a carry occurs, when the data buffer end is reached (buffer end signal (BUF END) 311 is asserted), or when data is set (select signal line groups 313a to 313a).
13d is asserted). The synchronous load terminal SYNC LD loads data from the data buses 312a to 312d when the clock signal 314 is input at the time of assertion.

On the other hand, the asynchronous load terminal ASYNC LD
Is connected to the gate 403 and the clock signal 31
4 regardless of the input data buses 312a-31.
Load from 2d. The gate 403 outputs the mode change signal (MOD) when the counter mode signal (CNT MODE) 316 is at L level, that is, in the raster scan mode.
E CHG) 315 is applied to change to the block scan mode, a pulse is output to the asynchronous load terminal ASYNC.
In addition to the LD, the counter is forcibly loaded with the value in the latch in the data latch / selector 301 to clear the entire counter. The gates 404 to 406 select two types of carry inputs, and select one of them according to a counter mode signal (CNT MODE) 316. This output is input to the count enable terminal of the counter body 401, and carries out only when this is asserted.

FIG. 4 is a detailed block diagram showing the configuration of data latch / selector 301 shown in FIG.

In the figure, reference numerals 501a to 501d denote data latches.
Latch 302d base data. This operation is performed by selecting the select signal 310a output from the address decoder 304.
In steps 310 to 310, the write signal line 307 is gated.
Reference numerals 502a to 502d denote data bus selectors corresponding to the counters 302a to 302d. When the value of the data bus 306 is directly loaded to the counters 302a to 302d, the corresponding select signal line group 313 of the address decoder 304 is used.
The data buses 312a to 312d are connected to the data bus 306 according to a to 313d. Otherwise, input data buses 312a-312d are connected to data latches 501a.
To the 501d side. Reference numerals 322b to 322d denote outputs of the data latches 501b to 501d.
The base numbers b to 302d are connected to a conversion circuit 303 described later.

FIG. 5 is a detailed block diagram illustrating the configuration of conversion circuit 303 shown in FIG. The conversion circuit 3
Reference numeral 03 denotes scalarizing the values of the counters 302a to 302d for address mapping, and there are various methods. The counter shown in FIG.
When the output of to 302d is m, x, n, y, mXNY
+ XNY + nY + y. As a result, the raster data shown in FIG. 10A is continuously loaded on the address.

In the figure, a multiplier 601 outputs an XNY value 608, an NY value 609, and a Y value 610. 60
2 to 604 are multipliers, and 605 to 607 are adders, which add the above values. However, in the configuration described above, when switching between the raster scan mode and the block scan mode, the block end of the raster data, that is, FIG.
If it is not performed in the block 0 (n-1) shown in FIG. 0, the block scan or the raster scan will be started halfway when switching. For example, in consideration of addressing of a general-purpose data buffer, data and a code are generally input in addition to image data, and there is a case where image data is block-scanned and read from an arbitrary address. In such a case, when switching between the raster scan mode and the block scan mode, it is necessary to operate the counter so as to regard it as a block end.
For this reason, in this embodiment, the buffer end is detected by a circuit as shown in FIG.

FIG. 6 is a circuit block diagram showing an example of a buffer end detecting mechanism applied to the embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals.

In the figure, reference numeral 701 denotes a counter body (counter) having the same configuration as the counter shown in FIG.
Reference numeral 702 denotes a buffer end detector.
To detect the buffer end. 703 is an address register for holding an address value, 704 is a gate,
705 is an adder.

First, it is assumed that the counter 701 starts from the raster mode. The address register 7
03 is cleared and the address bus output 707 is “0”. In this state, the address bus 706
Is equal to the output 323 of the counter 701. In the raster scan mode, the counter mode signal (CNT MO)
DE) 316 is set to “L”. At this time, the input gate of the address register 703 is active. When the mode change signal (MODE CHG) 315 is input, the address register 703 holds the address value and the counter mode signal (CNT MODE) 316
Is set to “H”, and the input of the address register 703 becomes inactive. This also allows the counter 302a
Asynchronous loading of the counter body 401 inside to 302d operates, the initial value is loaded, and the counter output 323 becomes "0", that is, the block end. Reference numeral 707 denotes an address bus output held immediately before the change to the block scan mode, which is held in the address register 703. The sum of the output and the output 322 of the counter 701 becomes the address bus 706 in the block mode. In this state, the counter 701 counts in the block scan mode. When changing from the block scan mode to the raster scan mode, the mode change signal (MODE CHG) 315
Is performed by applying a pulse. At this time, the counter mode signal (CNT MODE) 316 changes from “H” to “L” level. However, the mode change signal (MOD
When a pulse is applied to the (ECHG) 315, the address register 703 is inactive, and thus retains the previous value. Also, the counters 302a to 302a-3
02d output is the mode change signal (MODE
CHG) 315 does not change. Therefore, the raster scan is started as it is from the time when the mode change signal (MODE CHG) 315 is added.
However, since the purpose of the block scan mode is generally to block data, the block end signal (BLK END) 319 is monitored, and the block scan mode is changed from the block scan mode to the raster scan mode at the block end point. Should be done.

The gate 704 is connected to the address register 703
Is cleared in synchronization with the clock signal 314. The buffer end detector 702 is connected to the address bus 706
Detects that the buffer end has been reached. When the buffer end signal (BUFEND) 311 is asserted, the gate 704 becomes active, and the address register 703 is cleared by the clock pulse immediately after that. Also, a buffer end signal (BUF END) 3
Numeral 11 asserts the synchronous load terminal SYNC LD of the counter body 401 shown in FIG. 3, the same clock pulse loads the initial value to the counter body 401, and returns the entire counter to the starting point.

The counter 302 shown in the above embodiment
The base numbers a to 302d, that is, the number of blocks and the block size are arbitrary. However, in general use, the block sizes X and Y are fixed. Therefore,
Input data bus 312 for counters 302b and 302d
b and 312d may be configured to have fixed values except when input from the data bus 306. In this case, the data latches 501b and 501d and the select signal line groups 310b and 310d and the outputs 322b and 322 shown in FIG.
d becomes unnecessary.

In the above embodiment, the base M of the counter 302a has been described as the number of vertical blocks of the entire image. However, if the entire image cannot be stored in the buffer, M is used.
May be a value that fits in the buffer. in this case,
The whole image is divided and handled in units that fit in the buffer. This division must be performed at the block end, that is, in units of NXY pixels.

In the above embodiment, the case where a multiplier is used as the conversion circuit 303 has been described. However, the hardware operation time becomes a problem when the counter is operated at high speed. If M = 2 ^a , N = 2
^{If c} , X = 2 ^b , Y = 2 ^d , the counters 302 a to 30 a
The output bit widths of 2d are a, b, c, and d, respectively, and the buffer address bus 323 becomes a bus of a + b + c + d bit width as it is. In general, X = Y = 4,8,1
6,... = 2 ^s , and M is 2 according to the size of the buffer.
^Assuming that ^t and N are 2 ^u -1 at the maximum, the conversion circuit 303 can be configured as shown in FIG.

FIG. 7 is a detailed block diagram for explaining another configuration of the conversion circuit 303 shown in FIG. Note that the address value is mXNY + xNY + nY + y as described above.
The actual multiplication is performed by xx
N, m × N.

In this figure, 801 and 802 are multipliers, 803 is an s-bit shifter, and 804 and 805 are adders. The buffer address bus 323 is (2s + t + u bits).
FIG. 8 shows the bits of this calculation.

FIG. 8 is a schematic diagram showing the assignment of the operation value of the conversion circuit shown in FIG.

In the figure, 901 is an s-bit counter output (y), 902 is a u-bit counter output (n) at a maximum, 903 is a multiplication output (xN) with a maximum of (s + u) bits, and 904 is a maximum. This is a multiplication output (mN) of (t + u) bits. The bit shifter 803 shifts s bits. The adders 804 and 805 add the counter output 902 to the multiplication output 903 and the value obtained by shifting the multiplication output 904 by s bits, and add the conversion address 905 obtained by adding the addition result 806 to the s-bit counter output 901 to the buffer address bus 323. Output.

In the above embodiment, the multiplication output (xN),
The case where the multiplication output (mN) is obtained by multiplication has been described. This is because when N is a maximum U bit = 2 ^U ,
The multiplication output (xN) is, as shown in FIG.
The multiplication output (mN) may be obtained by the u-bit shift of the counter output 321c (m) and the u-bit shift of the output 21b (x).

In this case, the conversion circuit 303 simply performs bit shift addition of each value of the counter outputs 1001 to 1004, and since the bits do not overlap, the output lines of the counters 302a to 302d are simply arranged and the final Output can be used. However, when N is an arbitrary number, a portion used discontinuously occurs in the memory space (2 ^{2s + t + u} ).

[0043]

As described above, according to the present invention, there is provided a counter means in which a plurality of counters respectively counting a plurality of addresses set in a storage means are cascaded,
Since there are changing means for changing the connection order of the plurality of counters based on a mode signal input externally, and address conversion means for converting the output of each counter of the counter means into a one-dimensional address, they are arranged on the data transfer path. The buffer memory and the addressing circuit for the buffer memory and the data scan conversion memory and the addressing circuit for the data scan conversion memory can be shared, and the conventional address mechanism can be greatly simplified.

[0044]

Further, holding means for holding the address output from each counter immediately before the mode signal switching, and adding the address output from each counter immediately after the mode signal switching and the address held in the holding means. And an adder for outputting the access address to the address bus, thereby preventing data modification or the like accompanying the mode switching beforehand and always outputting the correct access address.

Therefore, even when general data, codes, and image data to be blocked are mixedly loaded on the same memory space, only image data can be selected and blocked. Has the effect of

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an address counter according to an embodiment of the present invention.

FIG. 2 is a state transition diagram showing an address conversion process by the counter shown in FIG.

FIG. 3 is a detailed block diagram illustrating a configuration of a counter shown in FIG.

FIG. 4 is a detailed block diagram showing a configuration of a data latch / selector shown in FIG.

FIG. 5 is a detailed block diagram illustrating a configuration of a conversion circuit illustrated in FIG. 1;

FIG. 6 is a circuit block diagram illustrating an example of a buffer end detection mechanism applied to the embodiment of the present invention.

FIG. 7 is a detailed block diagram illustrating another configuration of the conversion circuit shown in FIG.

FIG. 8 is a schematic diagram showing assignment of operation values of the conversion circuit shown in FIG. 7;

FIG. 9 is a schematic diagram showing another assignment of the operation value of the conversion circuit shown in FIG. 7;

FIG. 10 is a schematic diagram showing processing for spatially dividing a secondary image into blocks and performing orthogonal transformation.

[Explanation of symbols]

 301 Data latch / selector 302a Counter module 302b Counter module 302c Counter module 302d Counter module 303 Encoder

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-3-223974 (JP, A) JP-A-1-293479 (JP, A) JP-A-63-234361 (JP, A) JP-A-61- 208173 (JP, A) JP-A-60-196857 (JP, A) JP-A 1-194081 (JP, A) JP-A 5-108464 (JP, A) JP-A 2-136978 (JP, A) JP-A-59-123925 (JP, A) JP-A-3-137743 (JP, A) JP-A-2-13639 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 12/00-12/06 G06T 1/60

Claims (2)

(57) [Claims] 1. A counter means in which a plurality of counters respectively counting a plurality of addresses set in a storage means are cascaded, and a change in which a connection order of the plurality of counters is changed based on a mode signal input externally. And an address conversion means for converting a combination of outputs from the respective counters of the counter means into a one-dimensional address. (2)The address change immediately before the mode signal is switched.
Holding means for holding an address output from the conversion means, After the mode signal is switched, the
Address and the address held by the holding means
Adding means for outputting the added address to the address bus
When, Having 2. The address cow according to claim 1, wherein:
Nta.