JP3156682B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP3156682B2 JP3156682B2 JP30017098A JP30017098A JP3156682B2 JP 3156682 B2 JP3156682 B2 JP 3156682B2 JP 30017098 A JP30017098 A JP 30017098A JP 30017098 A JP30017098 A JP 30017098A JP 3156682 B2 JP3156682 B2 JP 3156682B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- layer
- active region
- substrate
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 75
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000000758 substrate Substances 0.000 claims description 40
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 16
- 238000005253 cladding Methods 0.000 claims description 13
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 10
- 229910052785 arsenic Inorganic materials 0.000 claims description 9
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 claims description 8
- 229910000073 phosphorus hydride Inorganic materials 0.000 claims description 8
- 239000013078 crystal Substances 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- 239000012298 atmosphere Substances 0.000 claims description 4
- 239000001257 hydrogen Substances 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 4
- 230000006798 recombination Effects 0.000 description 11
- 239000000463 material Substances 0.000 description 10
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 8
- 230000000694 effects Effects 0.000 description 8
- 229910052698 phosphorus Inorganic materials 0.000 description 8
- 239000011574 phosphorus Substances 0.000 description 8
- 239000007789 gas Substances 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000005215 recombination Methods 0.000 description 5
- 238000006467 substitution reaction Methods 0.000 description 5
- 229910000673 Indium arsenide Inorganic materials 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 239000000969 carrier Substances 0.000 description 4
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 3
- 125000004429 atom Chemical group 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 240000002329 Inga feuillei Species 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 125000005626 carbonium group Chemical group 0.000 description 1
- 238000003795 desorption Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000000171 gas-source molecular beam epitaxy Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 125000002524 organometallic group Chemical group 0.000 description 1
- 125000004437 phosphorous atom Chemical group 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- QTQRGDBFHFYIBH-UHFFFAOYSA-N tert-butylarsenic Chemical compound CC(C)(C)[As] QTQRGDBFHFYIBH-UHFFFAOYSA-N 0.000 description 1
- ZGNPLWZYVAFUNZ-UHFFFAOYSA-N tert-butylphosphane Chemical compound CC(C)(C)P ZGNPLWZYVAFUNZ-UHFFFAOYSA-N 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Landscapes
- Semiconductor Lasers (AREA)
- Light Receiving Elements (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Description
【0001】[0001]
【発明の属する技術分野】本発明は、本発明はキャリヤ
の閉じ込め効果に優れ、例えば、発光効率の高い半導体
素子およびその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an excellent carrier confinement effect, for example, having a high luminous efficiency, and a method of manufacturing the same.
【0002】[0002]
【従来の技術】加入者系の半導体レーザは低コスト化の
要請から、温度制御装置の不要な、高温でも発光効率の
よいレーザが必要とされる。高温で発光効率を向上させ
るためには、活性領域中の多重量子井戸構造において、
量子井戸層には内部量子効率の大きい材料を選択するこ
とと、障壁層には、電子を井戸層内に閉じこめるため
に、量子井戸層との間の伝導帯エネルギー差の大きい材
料を選択することが効果的である。2. Description of the Related Art In order to reduce the cost of a subscriber semiconductor laser, a laser which does not require a temperature control device and has high luminous efficiency even at a high temperature is required. In order to improve the luminous efficiency at high temperature, in the multiple quantum well structure in the active region,
Select a material with a large internal quantum efficiency for the quantum well layer and a material with a large conduction band energy difference between the quantum well layer and the quantum well layer in order to confine electrons in the well layer. Is effective.
【0003】この様な材料系としてIn(インシ゛ウム)As(ヒ素)P
(リン)を量子井戸層に、InGa(カ゛リウム)Al(アルミニウム)Asを障壁
層に用いた半導体レーザの例が山田らにより第45回応
用物理学関係連合講演会講演予稿集30p―ZH−9に
発表されている。以下に製法に従って構造を説明する。
図3は構造図であり、図4はプロセスフロー図である。
図4に示すように、InP基板11の上へ、1.5μm厚さ
のn−InP下部クラッド層12、1150 のi-In0.52A
l0.48As下部SCH(Separate Confinement Heterostruc
ture)層13、活性領域14として100 のi−InAs0.45
P0.55井戸層15と100 のi-In0.52Al 0.16Ga0.31As障
壁層16、2050 のi−In0.52Al0.48As上部SCH層1
7、1μm厚さのp−InP上部クラッド層18、p−InGaA
s電極コンタクト層19を順に成長し、半導体レーザ基
板20を作製する。ここではV族をガスで供給する、ガ
スソース分子線エピタキシー装置を用いて基板温度52
0℃で作製した。As such a material system, In (indium) As (arsenic) P
(Phosphorus) for the quantum well layer and InGa (carbonium) Al (aluminum) As for the barrier
The example of the semiconductor laser used for the layer is the 45th response by Yamada et al.
Preliminary Lectures for the Alliance for Physical Physics in Japan 30p-ZH-9
It has been announced. The structure will be described below according to the manufacturing method.
FIG. 3 is a structural diagram, and FIG. 4 is a process flow diagram.
As shown in FIG. 4, a 1.5 μm thick
N-InP lower cladding layer 12, 1150 i-In0.52A
l0.48As Lower SCH (Separate Confinement Heterostruc
100) i-InAs layer 13 and active region 140.45
P0.55Well layer 15 and 100 i-In0.52Al 0.16Ga0.31As obstacle
I-In of wall layers 16 and 20500.52Al0.48As upper SCH layer 1
7, p-InP upper cladding layer 18 having a thickness of 1 μm, p-InGaA
The s electrode contact layer 19 is sequentially grown, and
The plate 20 is manufactured. Here, the V-group is supplied by gas.
Substrate temperature 52 using a source molecular beam epitaxy apparatus
Prepared at 0 ° C.
【0004】その後、メサ上部の幅が4μm、メサ下部の
幅が2.5μmの逆メサ型にエッチングしてメサストライプ
21を作製する。その際、エッチングの深さはp−InP
上部クラッド層18までとし、i−In0.52Al0.48As上
部SCH層17は露出しないようにする。その後、半導
体レーザ基板20全面にSiO2からなる絶縁膜22を形成
して、メサ上部にストライプ状の穴23を絶縁膜に形成
して導通を確保した後に、p型オーミック電極24を形
成する。さらに半導体レーザ基板20を100μm程度の厚
さに研磨した後に裏面にn型オーミック電極25を形成
して、適当な長さに劈開して半導体レーザが完成する。[0004] Thereafter, the mesa stripe 21 is formed by etching into an inverted mesa shape in which the upper part of the mesa has a width of 4 µm and the lower part of the mesa has a width of 2.5 µm. At this time, the etching depth is p-InP
The upper SCH layer 17 of the i-In 0.52 Al 0.48 As is not exposed until the upper clad layer 18 is reached. Thereafter, an insulating film 22 made of SiO 2 is formed on the entire surface of the semiconductor laser substrate 20, and a stripe-shaped hole 23 is formed in the insulating film above the mesa to secure conduction, and then a p-type ohmic electrode 24 is formed. Further, after the semiconductor laser substrate 20 is polished to a thickness of about 100 μm, an n-type ohmic electrode 25 is formed on the back surface and cleaved to an appropriate length to complete the semiconductor laser.
【0005】上記半導体レーザ26に電流を注入したと
きの電流経路を図3に示す。活性領域14に流れ込む電
流29以外に横方向に広がる漏れ電流28が存在する。FIG. 3 shows a current path when a current is injected into the semiconductor laser 26. In addition to the current 29 flowing into the active region 14, there is a leakage current 28 spreading in the lateral direction.
【0006】[0006]
【発明が解決しようとする課題】上述したような半導体
レーザは、メサの下部で電流が横方向に広がって漏れ電
流28となるため、発振閾電流が増加し、発光効率が低
下するという問題があった。この様な漏れ電流をなくす
ためには通常メサエッチングした後に、電流ブロック層
を再成長する方法が採られる。しかし、再成長を行う場
合にも以下のような問題があった。本材料系では、基板
半導体材料を構成するV族がリンで活性領域の半導体材
料を構成するV族がヒ素とそれぞれ異なるが、例えば再
成長昇温時に導入するV族ガスをアルシンにした場合、
400度以上の高温時にV族置換が生じ、基板が白濁す
るなど良好な再成長が不可能であった。また、再成長時
前の昇温時に導入するV族ガスをホスフィンにした場
合、活性領域の露出している部分ではヒ素がリンに置換
するが、昇温に要する時間が長いためにヒ素/リン置換
の進行に伴う結晶性の劣化が発生し、発光効率が低下す
るという問題もあった。また、Alを含んだ層が一旦大気
に曝されるため、活性領域の部分でAlの酸化物による非
発光再結合中心が数多く存在し、そのために発光効率が
低下するといった問題もあった。また、活性領域の外側
を、キャリヤと光のとじ込めのためのワイドギャップ半
導体層を再成長したとしても、非発光再結合中心はワイ
ドギャップ半導体層の内側に存在するために、非発光再
結合中心の影響を除去できず、発光効率が低下する要因
となっていた。The semiconductor laser as described above has a problem that the current spreads in the horizontal direction below the mesa and becomes a leakage current 28, so that the oscillation threshold current increases and the luminous efficiency decreases. there were. In order to eliminate such a leakage current, a method of regrowing the current block layer after the mesa etching is usually employed. However, regrowth also has the following problems. In the present material system, the group V constituting the substrate semiconductor material is phosphorus, and the group V constituting the semiconductor material in the active region is different from arsenic. For example, when a group V gas introduced at the time of temperature rise for regrowth is arsine,
At a high temperature of 400 ° C. or higher, V group substitution occurred, and good regrowth such as clouding of the substrate was impossible. When phosphine is used as the group V gas introduced at the time of temperature rise before regrowth, arsenic is replaced by phosphorus in the exposed portion of the active region. There is also a problem that the crystallinity is degraded as the substitution proceeds, and the luminous efficiency is reduced. In addition, since the layer containing Al is once exposed to the atmosphere, there are many non-radiative recombination centers due to Al oxide in the active region, which causes a problem that the luminous efficiency is reduced. Even if the wide gap semiconductor layer for trapping carriers and light is regrown outside the active region, the non-radiative recombination center exists inside the wide gap semiconductor layer, so the non-radiative recombination center exists. The influence of the center could not be removed, and this was a factor in lowering the luminous efficiency.
【0007】本発明は、前述の課題に鑑みてなされたも
ので、発光効率の高い半導体素子およびその製造方法を
提供することを目的とする。The present invention has been made in view of the above-mentioned problems, and has as its object to provide a semiconductor device having high luminous efficiency and a method of manufacturing the same.
【0008】[0008]
【課題を解決するための手段】本発明は、前記課題を解
決するため、以下の構成を採用した。すなわち、請求項
1記載の半導体素子では、ヒ素を含む活性領域を有し、
その側面が露出しているか、又は再成長層に覆われてい
る半導体素子において、前記活性領域の側面にド・ブロ
イ波長以上、かつ歪み臨界膜厚以下の厚さのワイドギャ
ップ半導体層が存在することを特徴とする。The present invention has the following features to attain the object mentioned above. That is, the semiconductor device according to claim 1 has an active region containing arsenic,
In the semiconductor element whose side surface is exposed or covered with the regrown layer, a wide gap semiconductor layer having a thickness equal to or more than the de Broglie wavelength and equal to or less than the critical strain thickness exists on the side surface of the active region. It is characterized by the following.
【0009】請求項2記載の半導体素子では、請求項1
記載の半導体素子において、前記活性領域を含んだメサ
部が形成され、前記ワイドギャップ半導体層が前記活性
領域の側面から前記メサ部の内部にかけて形成されてい
ることを特徴とする。In the semiconductor device according to the second aspect, the first aspect is as follows.
The semiconductor device according to claim 1, wherein a mesa portion including the active region is formed, and the wide gap semiconductor layer is formed from a side surface of the active region to an inside of the mesa portion.
【0010】請求項3記載の半導体素子の製造方法で
は、半導体基板上に結晶成長装置を用いて下部クラッド
層を作製する工程と、該下部クラッド層上にヒ素を含む
活性領域を作製する工程と、該活性領域上に上部クラッ
ド層を作製する工程と、該上部クラッド層上にキャップ
層を作製する工程とにより半導体素子基板を作製した
後、該半導体素子基板をメサ状にエッチングする工程を
有する半導体素子の製造方法において、前記活性領域側
面が露出した状態の前記半導体素子基板を、650℃ま
で昇温した後、ホスフィンを1×10-5mol/cm2導入する
工程を含むことを特徴とする。According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a lower cladding layer on a semiconductor substrate using a crystal growing apparatus; and forming an active region containing arsenic on the lower cladding layer. Forming a semiconductor device substrate by forming an upper cladding layer on the active region, and forming a cap layer on the upper cladding layer, and then etching the semiconductor device substrate in a mesa shape. The method of manufacturing a semiconductor device, further comprising a step of, after raising the temperature of the semiconductor device substrate with the side surfaces of the active region exposed to 650 ° C., introducing 1 × 10 −5 mol / cm 2 of phosphine. I do.
【0011】請求項4記載の半導体素子の製造方法で
は、請求項3記載の半導体素子の製造方法において、前
記半導体素子基板をメサ状にエッチングする工程後の再
成長前に、基板温度が400℃に達するまでアルシン雰
囲気中で昇温する工程と、400℃以上650℃程度ま
では水素又は窒素雰囲気中で昇温する工程とを含むこと
を特徴とする。According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device according to the third aspect, the substrate temperature is set to 400 ° C. before regrowth after the step of etching the semiconductor element substrate into a mesa. , And a step of raising the temperature in a hydrogen or nitrogen atmosphere up to about 400 ° C. to 650 ° C.
【0012】[0012]
【発明の実施の形態】以下、本発明に係る半導体素子お
よびその製造方法の一実施形態を、図1から図4を参照
しながら説明する。図1は本素子の構造図、図2は本素
子のプロセスフロー図である。以下に製法に従って構造
を説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to FIGS. FIG. 1 is a structural view of the present device, and FIG. 2 is a process flow diagram of the present device. The structure will be described below according to the manufacturing method.
【0013】図2の(a)に示すように、InP基板1
1の上へ、1.5μm厚さのn−InP下部クラッド層1
2、1150 のi-In0.52Al0.48As下部SCH層13、活
性領域14として100 のi−InAs0.45P0.55井戸層15
と100 のi-In0.52Al0.16Ga0. 31As障壁層16、2050
のi−In0.52Al0.48As上部SCH層17、1μm厚さの
p−InP上部クラッド層18を順に成長し、半導体レー
ザ基板41を作製した。ここではV族をガスで供給す
る、ガスソース分子線エピタキシー装置を用いて基板温
度520℃で作製した。As shown in FIG. 2A, the InP substrate 1
1, 1.5 μm thick n-InP lower cladding layer 1
2. 1150 i-In 0.52 Al 0.48 As lower SCH layer 13, 100 i-InAs 0.45 P 0.55 well layer 15 as active region 14
When 100 of the i-In 0.52 Al 0.16 Ga 0. 31 As barrier layer 16,2050
The i-In 0.52 Al 0.48 As upper SCH layer 17 and the 1 μm-thick p-InP upper cladding layer 18 were sequentially grown to produce a semiconductor laser substrate 41. Here, the substrate was manufactured at a substrate temperature of 520 ° C. by using a gas source molecular beam epitaxy apparatus that supplies the group V with a gas.
【0014】その後、SiO2膜42をマスクとして、メサ
幅が2μm程度となるようにストライプ状にエッチングし
てメサストライプ43を作製した。その際、エッチング
の深さはInP基板11に達するまでとした。(図2の
(b)) SiO2膜42を除去した後、再度結晶成長装置内に投入し
た。この装置は有機金属気相成長装置とした。結晶成長
前の昇温手順として次の通り行った。Thereafter, using the SiO 2 film 42 as a mask, a mesa stripe 43 was formed by etching in a stripe shape so that the mesa width was about 2 μm. At this time, the etching depth was set to reach the InP substrate 11. ((B) of FIG. 2) After removing the SiO 2 film 42, it was put into the crystal growth apparatus again. This apparatus was an organometallic vapor phase epitaxy apparatus. The procedure for raising the temperature before crystal growth was as follows.
【0015】図2の(b)に示すように、初期状態にお
いては基板底面部51などの様なInP面と比較して、メ
サ側面のAl原子が存在する部分では酸化層54が厚く形
成されている。その状態で、まずアルシンを導入して昇
温し、基板温度が400℃に達した後、その温度を保っ
たまま2時間待機した。この待機過程で酸化層54の9
0%程度が脱離することが、別の実験で観測されてい
る。また、この温度ではV族置換の程度は非常に小さ
く、アルシン導入によるInP基板11部分の荒れは生じ
なかった。As shown in FIG. 2B, in the initial state, the oxide layer 54 is formed thicker in the portion where the Al atoms exist on the side surface of the mesa than in the InP surface such as the bottom surface portion 51 of the substrate. ing. In this state, first, arsine was introduced and the temperature was raised. After the substrate temperature reached 400 ° C., the device was kept on standby for 2 hours while maintaining the temperature. During this waiting process, the oxide layer 54
Desorption of about 0% has been observed in another experiment. Also, at this temperature, the degree of V group substitution was very small, and the introduction of arsine did not cause roughness of the InP substrate 11 portion.
【0016】さらに、アルシンを遮断して650℃に達す
るまで水素又は窒素雰囲気中での昇温を行った。この段
階では基板表面のリン原子、ヒ素原子が脱離して、III
族表面となるが、その状態は安定状態であり、昇温時間
中には基板、メサ側面両方とも表面荒れは生じなかっ
た。さらに基板温度が650℃に達した後100SCCMの流量で
10秒間ホスフィンを導入した。この流量は、本装置で
は基板上に供給されるPH3量として1×10-5mol/cm2程度
である。Further, the temperature was raised in a hydrogen or nitrogen atmosphere until the temperature reached 650 ° C. while blocking arsine. At this stage, phosphorus and arsenic atoms on the substrate surface are desorbed, and III
The surface was a stable state, and the substrate and the mesa side surface were not roughened during the heating time. After the substrate temperature reached 650 ° C., phosphine was introduced at a flow rate of 100 SCCM for 10 seconds. This flow rate is about 1 × 10 −5 mol / cm 2 as the PH 3 amount supplied onto the substrate in the present apparatus.
【0017】このホスフィン導入により、III族面とな
っていた結晶表面にリン原子が供給され、基板は通常の
InP面となるが、活性領域付近のi-In0.52Al0.48As下部
SCH層13、i−In0.52Al0.48As上部SCH層1
7、活性領域14のi−InAs0. 45P0.55井戸層15とi-
In0.52Al0.16Ga0.31As障壁層16などの部分は表面から
4−5モノレイヤー程度の深さまでV族の一部がリンに
置換され、図2の(c)に示すように、ヒ素/リン置換
領域58が形成された。この様なV族置換の状態は、栗
原他により電子情報通信学会信学技報LQE98-24、55頁
に報告されている。By the introduction of the phosphine, phosphorus atoms are supplied to the crystal surface which has been in the group III plane, and the substrate is formed in a normal state.
I-In 0.52 Al 0.48 As lower SCH layer 13 near the active region, i-In 0.52 Al 0.48 As upper SCH layer 1 near the active region
7, an i-InAs 0. 45 P 0.55 well layers 15 of the active region 14 i-
In the portion such as the In 0.52 Al 0.16 Ga 0.31 As barrier layer 16, part of the V group is replaced with phosphorus from the surface to a depth of about 4-5 monolayers, and as shown in FIG. A replacement region 58 was formed. Such a state of group V substitution is reported by Kurihara et al. In IEICE Technical Report LQE 98-24, p. 55.
【0018】InAlAs、InAlGaAs、InAsPなどの材料系で
はV族にリンが混入することにより、禁制帯幅が広がっ
てワイドギャップ半導体層となり、屈折率が低くなる。
このワイドギャップ半導体層は、メサ側面に存在する非
発光再結合中心よりも内側にできるため、活性領域内に
おけるレーザ光のメサの内側へのとじ込めが強くなり、
メサ側面に残留していたAlの酸化物によって生じる非発
光再結合中心59の影響が小さくなる。キャリヤに対し
てもワイドギャップ半導体が存在する場合、そのワイド
ギャップ半導体層の厚さがド・ブロイ波長以上の厚さで
あれば、その外側まではキャリヤの漏れがほとんどない
ため、ワイドギャップ半導体層の外側にある非発光再結
合中心59によって捕獲されるために生じる、無効なキ
ャリヤが減少し、キャリヤの注入が発光に有効に寄与す
るようになる。In a material system such as InAlAs, InAlGaAs, InAsP, etc., when phosphorus is mixed into the group V, the forbidden band width is widened to form a wide gap semiconductor layer, and the refractive index is lowered.
Since this wide gap semiconductor layer can be formed inside the non-radiative recombination center existing on the side surface of the mesa, the laser light in the active region is strongly bound to the inside of the mesa,
The effect of non-radiative recombination centers 59 caused by Al oxide remaining on the mesa side surface is reduced. When a wide-gap semiconductor is present also for a carrier, if the thickness of the wide-gap semiconductor layer is greater than the de Broglie wavelength, there is almost no leakage of the carrier to the outside of the wide-gap semiconductor layer. The non-radiative recombination centers 59 that are trapped outside are reduced in ineffective carriers, and carrier injection effectively contributes to light emission.
【0019】ここで形成される4−5モノレイヤー程度
のヒ素/リン置換領域58は、歪層となっているが、臨
界膜厚以下であるため、欠陥などは生じない。しかも、
歪層であるためにバンドギャップの曲がりが大きく、薄
い層でありながらもキャリヤの閉じ込めに対して、有効
に作用する。The arsenic / phosphorus-substituted region 58 of about 4 to 5 monolayers formed here is a strained layer, but does not have a defect or the like since the thickness is less than the critical thickness. Moreover,
The strained layer has a large bandgap bend, and effectively acts to confine carriers even though it is a thin layer.
【0020】その後、直ちに再成長層としてp型InP埋
め込み層60を2μm、p型InGaAsキャップ層61を100
nm全面に成長した。(図2の(d))結晶成長装置から
取り出した後に、図2の(e)に示すように、上面にp
型オーミック電極62を、半導体レーザ基板を100μm程
度の厚さに研磨した後に裏面にn型オーミック電極63
を形成して、適当な長さに劈開して半導体レーザが完成
した。Thereafter, the p-type InP buried layer 60 and the p-type InGaAs cap layer 61 are immediately
nm. ((D) of FIG. 2) After being taken out from the crystal growing apparatus, as shown in (e) of FIG.
After polishing the semiconductor laser substrate to a thickness of about 100 μm, the n-type ohmic electrode
Was formed and cleaved to an appropriate length to complete a semiconductor laser.
【0021】本実施形態の半導体レーザの発振閾値は、
室温で8mAと従来例の15mAに比較してほぼ半減し
た。この効果は、埋め込み構造として、漏れ電流の低減
を行ったことに加え、メサ側面の非発光再結合中心の影
響を低減できたためと考えられる。また、特性温度は従
来例並の120Kと、高温でも良好な発光特性を示し
た。この様な温度特性が良好である要因は活性領域中の
障壁層、SCH層に伝導帯エネルギー差の大きいAl系材
料を用いたことにある。The oscillation threshold of the semiconductor laser of this embodiment is:
At room temperature, the current was 8 mA, which was almost halved compared to the conventional 15 mA. This effect is considered to be due to the fact that the effect of the non-radiative recombination center on the side surface of the mesa was reduced in addition to the reduction of the leakage current as the buried structure. In addition, the characteristic temperature was 120 K, which is the same as that of the conventional example. The reason why such temperature characteristics are good is that an Al-based material having a large conduction band energy difference is used for the barrier layer and the SCH layer in the active region.
【0022】なお、上記実施形態では、V族材料ガスと
して、アルシン及びホスフィンとしたが、これらは同様
の目的で使用可能なターシャリーブチルアルシンやター
シャリーブチルホスフィンなどの他の原料に変えても同
様の効果が得られる。さらに、本実施形態では半導体レ
ーザとしたが、たとえばInAlAsを用いるアバランシェフ
ォトダイオードや、単1電子トンネルトランジスタなど
の他の半導体素子にも適用が可能である。In the above-described embodiment, arsine and phosphine are used as the group V material gas. However, these gases may be replaced with other raw materials such as tertiary butyl arsine and tertiary butyl phosphine which can be used for the same purpose. Similar effects can be obtained. Further, in this embodiment, the semiconductor laser is used. However, the present invention can be applied to other semiconductor elements such as an avalanche photodiode using InAlAs and a single electron tunnel transistor.
【0023】[0023]
【発明の効果】本発明によれば、以下の効果を奏する。 (1)請求項1記載の半導体素子によれば、活性領域の
側面にド・ブロイ波長以上、かつ歪み臨界膜厚以下の厚
さのワイドギャップ半導体層が存在するので、ワイドギ
ャップ半導体層の厚さがド・ブロイ波長以上の厚さであ
ることから、その外側まではキャリヤの漏れがほとんど
ないため、半導体レーザ等の場合、ワイドギャップ半導
体層の外側にある非発光再結合中心によって捕獲される
ために生じる、無効なキャリヤが減少し、キャリヤの注
入を発光に有効に寄与させることができる。また、前記
ワイドギャップ半導体層が歪層となっているが、臨界膜
厚以下であるため、欠陥等が生じないとともに、歪層で
あるためにバンドギャップの曲がりが大きく、薄い層で
ありながらもキャリヤの閉じ込めに対して、有効に作用
させることができる。According to the present invention, the following effects can be obtained. (1) According to the semiconductor device of the first aspect, since the wide gap semiconductor layer having a thickness not less than the de Broglie wavelength and not more than the critical strain thickness exists on the side surface of the active region, the thickness of the wide gap semiconductor layer is large. Since the thickness is more than the de Broglie wavelength, there is almost no carrier leakage up to the outside, so in the case of a semiconductor laser or the like, it is captured by the non-radiative recombination center outside the wide gap semiconductor layer. As a result, ineffective carriers are reduced, and carrier injection can be effectively contributed to light emission. Further, although the wide gap semiconductor layer is a strained layer, since the thickness is equal to or less than the critical film thickness, defects and the like do not occur, and since the strained layer has a large band gap, it is a thin layer. It can effectively act on the confinement of the carrier.
【0024】(2)請求項2記載の半導体素子によれ
ば、活性領域を含んだメサ部が形成され、ワイドギャッ
プ半導体層が活性領域の側面からメサ部の内部にかけて
形成されているので、半導体レーザ等の場合、ワイドギ
ャップ半導体層がメサ部の側面に存在する非発光再結合
中心よりも内側にできるため、活性領域内におけるレー
ザ光のメサ部内側へのとじ込めが強くなり、メサ部の側
面に残留していた、例えばAlの酸化物によって生じる非
発光再結合中心の影響を小さくすることができる。(2) According to the semiconductor device of the second aspect, the mesa portion including the active region is formed, and the wide gap semiconductor layer is formed from the side surface of the active region to the inside of the mesa portion. In the case of a laser or the like, since the wide gap semiconductor layer can be formed inside the non-radiative recombination center existing on the side surface of the mesa portion, the laser light in the active region is more strongly trapped inside the mesa portion, and the mesa portion It is possible to reduce the influence of non-radiative recombination centers generated by, for example, Al oxide remaining on the side surface.
【0025】(3)請求項3記載の半導体素子の製造方
法によれば、活性領域側面が露出した状態の半導体素子
基板を、650℃まで昇温した後、ホスフィンを1×10
-5mol/cm2導入する工程を含むので、高温でホスフィン
を導入することで、活性層材料を構成するV族原子がリ
ンに置換されて組成がワイドギャップ化するために、メ
サ側面部の非発光再結合中心の影響が大幅に低減でき
る。(3) According to the method of manufacturing a semiconductor device according to the third aspect, after the temperature of the semiconductor device substrate in which the side surface of the active region is exposed is raised to 650 ° C., phosphine is reduced to 1 × 10 5
-5 mol / cm 2 is introduced.By introducing phosphine at a high temperature, the group V atoms constituting the active layer material are replaced by phosphorus and the composition becomes wide-gap. The effect of non-radiative recombination centers can be significantly reduced.
【0026】(4)請求項4記載の半導体素子の製造方
法によれば、半導体素子基板をメサ状にエッチングする
工程後の再成長前に、基板温度が400℃に達するまで
アルシン雰囲気中で昇温する工程を含むので、低温でア
ルシン雰囲気中で酸化膜脱離を行うことにより、効果的
に酸化膜の除去が可能で発光効率が向上し、さらに、4
00℃以上650℃程度までは水素又は窒素雰囲気中で
昇温する工程を含むので、基板の荒れと活性領域部分の
発光効率の低下の両方を抑えることが可能となる。以上
の点から、例えば、長波系の発光効率及び温度特性の良
い半導体レーザが実現可能になる。(4) According to the method of manufacturing a semiconductor device according to the fourth aspect, before regrowth after the step of etching the semiconductor device substrate into a mesa shape, the substrate temperature is increased in an arsine atmosphere until the substrate temperature reaches 400 ° C. Since the oxide film is desorbed at a low temperature in an arsine atmosphere, the oxide film can be effectively removed and the luminous efficiency can be improved.
Since the step of raising the temperature in a hydrogen or nitrogen atmosphere from 00 ° C. to 650 ° C. is included, it is possible to suppress both the roughness of the substrate and the decrease in the luminous efficiency of the active region. From the above points, for example, a semiconductor laser having good long-wavelength luminous efficiency and good temperature characteristics can be realized.
【図1】本発明に係る半導体素子の一実施形態を示す構
造図である。FIG. 1 is a structural diagram showing one embodiment of a semiconductor device according to the present invention.
【図2】本発明に係る半導体素子の一実施形態を示すプ
ロセスフロー図である。FIG. 2 is a process flow chart showing one embodiment of a semiconductor device according to the present invention.
【図3】本発明に係る半導体素子における従来例を示す
構造図である。FIG. 3 is a structural diagram showing a conventional example of a semiconductor device according to the present invention.
【図4】本発明に係る半導体素子における従来例を示す
プロセスフロー図である。FIG. 4 is a process flow chart showing a conventional example of a semiconductor device according to the present invention.
11 InP基板 12 n−InP下部クラッド層 13 i-In0.52Al0.48As下部SCH層 14 活性領域 15 i−InAs0.45P0.55井戸層 16 i-In0.52Al0.16Ga0.31As障壁層 17 i−In0.52Al0.48As上部SCH層 18 p−InP上部クラッド層 19 p−InGaAs電極コンタクト層 20 半導体レーザ基板 21 メサストライプ 22 絶縁膜 23 ストライプ状の穴 24 p型オーミック電極 25 n型オーミック電極 28 漏れ電流 29 活性領域に流れ込む電流 41 半導体レーザ基板 42 SiO2膜 43 メサストライプ 51 基板底面部 54 酸化層 58 ヒ素/リン置換領域 59 非発光中心 60 p型InP埋め込み層 61 p型InGaAsキャップ層 62 p型オーミック電極 63 n型オーミック電極Reference Signs List 11 InP substrate 12 n-InP lower cladding layer 13 i-In 0.52 Al 0.48 As lower SCH layer 14 active region 15 i-InAs 0.45 P 0.55 well layer 16 i-In 0.52 Al 0.16 Ga 0.31 As barrier layer 17 i-In 0.52 Al 0.48 As upper SCH layer 18 p-InP upper cladding layer 19 p-InGaAs electrode contact layer 20 semiconductor laser substrate 21 mesa stripe 22 insulating film 23 striped hole 24 p-type ohmic electrode 25 n-type ohmic electrode 28 leakage current 29 activity Current flowing into region 41 Semiconductor laser substrate 42 SiO 2 film 43 Mesa stripe 51 Substrate bottom surface 54 Oxide layer 58 Arsenic / phosphorus substitution region 59 Non-emission center 60 p-type InP buried layer 61 p-type InGaAs cap layer 62 p-type ohmic electrode 63 n-type ohmic electrode
Claims (4)
露出しているか、又は再成長層に覆われている半導体素
子において、 前記活性領域の側面にド・ブロイ波長以上、かつ歪み臨
界膜厚以下の厚さのワイドギャップ半導体層が存在する
ことを特徴とする半導体素子。1. A semiconductor device having an active region containing arsenic, the side surface of which is exposed or covered with a regrown layer, wherein the side surface of the active region has a de Broglie wavelength or more and a strain critical A semiconductor device comprising a wide gap semiconductor layer having a thickness equal to or less than a film thickness.
前記メサ部の内部にかけて形成されていることを特徴と
する半導体素子。2. The semiconductor device according to claim 1, wherein a mesa portion including the active region is formed, and the wide gap semiconductor layer is formed from a side surface of the active region to an inside of the mesa portion. Characteristic semiconductor element.
部クラッド層を作製する工程と、該下部クラッド層上に
ヒ素を含む活性領域を作製する工程と、該活性領域上に
上部クラッド層を作製する工程と、該上部クラッド層上
にキャップ層を作製する工程とにより半導体素子基板を
作製した後、該半導体素子基板をメサ状にエッチングす
る工程を有する半導体素子の製造方法において、 前記活性領域側面が露出した状態の前記半導体素子基板
を、650℃まで昇温した後、ホスフィンを1×10-5mo
l/cm2導入する工程を含むことを特徴とする半導体素子
の製造方法。3. A step of forming a lower cladding layer on a semiconductor substrate using a crystal growing apparatus, a step of forming an active region containing arsenic on the lower cladding layer, and forming an upper cladding layer on the active region. A method of manufacturing a semiconductor device, comprising: forming a semiconductor device substrate by a manufacturing process and a process of forming a cap layer on the upper clad layer; and then etching the semiconductor device substrate in a mesa shape. After the temperature of the semiconductor element substrate with the side surfaces exposed was raised to 650 ° C., phosphine was added at 1 × 10 −5 mo.
A method for manufacturing a semiconductor device, comprising a step of introducing l / cm 2 .
おいて、 前記半導体素子基板をメサ状にエッチングする工程後の
再成長前に、基板温度が400℃に達するまでアルシン
雰囲気中で昇温する工程と、 400℃以上650℃程度までは水素又は窒素雰囲気中
で昇温する工程とを含むことを特徴とする半導体素子の
製造方法。4. The method of manufacturing a semiconductor device according to claim 3, wherein the temperature is increased in an arsine atmosphere until the substrate temperature reaches 400 ° C. before regrowth after the step of etching the semiconductor device substrate into a mesa. A method for manufacturing a semiconductor device, comprising: a step of raising the temperature in a hydrogen or nitrogen atmosphere from 400 ° C. to about 650 ° C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30017098A JP3156682B2 (en) | 1998-10-21 | 1998-10-21 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30017098A JP3156682B2 (en) | 1998-10-21 | 1998-10-21 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000124550A JP2000124550A (en) | 2000-04-28 |
| JP3156682B2 true JP3156682B2 (en) | 2001-04-16 |
Family
ID=17881597
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30017098A Expired - Fee Related JP3156682B2 (en) | 1998-10-21 | 1998-10-21 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3156682B2 (en) |
-
1998
- 1998-10-21 JP JP30017098A patent/JP3156682B2/en not_active Expired - Fee Related
Non-Patent Citations (1)
| Title |
|---|
| 電子情報通信学会技術研究報告(LQE98−24)Vol.98 No.109(1998)p.55−60 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000124550A (en) | 2000-04-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20030209771A1 (en) | Dopant diffusion blocking for optoelectronic devices using InAlAs or InGaAlAs | |
| US6556605B1 (en) | Method and device for preventing zinc/iron interaction in a semiconductor laser | |
| JP4002422B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP3045115B2 (en) | Method for manufacturing optical semiconductor device | |
| JP2781097B2 (en) | Semiconductor device and manufacturing method thereof | |
| EP0915542A2 (en) | Semiconductor laser having improved current blocking layers and method of forming the same | |
| JPH07101674B2 (en) | Method for manufacturing optical semiconductor element | |
| JP3156682B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2002368342A (en) | Multiplex quantum well semiconductor element | |
| JPH09214045A (en) | Semiconductor laser and manufacturing method thereof | |
| JP3665911B2 (en) | Semiconductor optical device manufacturing method and semiconductor optical device | |
| JP3348015B2 (en) | Method for producing electrode contact layer for non-alloy | |
| JP2780625B2 (en) | Manufacturing method of semiconductor laser | |
| JPWO2005031829A1 (en) | Semiconductor device and semiconductor integrated device | |
| JP2555984B2 (en) | Semiconductor laser and manufacturing method thereof | |
| Otsuka et al. | New structure by selective regrowth in multi-quantum well laser diodes performed by low pressure metalorganic vapor phase epitaxy | |
| JPH10242563A (en) | Method for manufacturing semiconductor light emitting device | |
| JP3298572B2 (en) | Method for manufacturing optical semiconductor device | |
| TWI396351B (en) | Optical semiconductor device and method of manufacturing same | |
| JPH07235725A (en) | Semiconductor laser device and manufacturing method thereof | |
| JPH04260386A (en) | Manufacture of optical semiconductor device | |
| JPH10261831A (en) | Semiconductor laser | |
| JPH11112075A (en) | Semiconductor laser device and method of manufacturing the same | |
| Kimura et al. | Undoped Al0. 48In0. 52As grown by metalorganic chemical vapor deposition as the current-blocking layer of laser diodes | |
| JPH09283846A (en) | Manufacturing method of semiconductor laser |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20010109 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080209 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090209 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100209 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100209 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110209 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110209 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120209 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120209 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130209 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130209 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140209 Year of fee payment: 13 |
|
| LAPS | Cancellation because of no payment of annual fees |