JP3157088B2 - Video signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-standard video signal generated by a special reproduction of a video and the like, wherein a video signal in which the cycle of a vertical synchronizing signal changes is output to a television receiver (hereinafter referred to as TV). And a video signal processing apparatus for securing a stable video.

[0002]

2. Description of the Related Art In recent years, video applications have been proposed not only for simple TV time shift and software viewing, but also for a new way of enjoying by special reproduction. What is reproducible is required.

[0003] A conventional video signal processing apparatus will be described below. Conventionally, as this type of video signal processing apparatus, for example, an apparatus disclosed in Japanese Patent Application Laid-Open No. 4-326272 has been proposed. Hereinafter, the configuration will be described with reference to FIGS. 7 and 8. FIG. 7 is a block diagram showing the configuration of this conventional video signal processing device, and FIG.
FIG. 3 is a configuration diagram showing a head configuration of FIG. In FIG. 7, the rotary cylinder 8 is provided with two sets of reproducing heads for standard reproduction and triple mode reproduction. Standard playback head SP1,
SP2 and triple-mode playback heads EP1 and EP2 are:
The two heads SP1, SP2 and EP1, EP2 of each set are attached to the positive and negative azimuth angles with respect to each other. Further head EP
1 and EP2 are arranged at a distance corresponding to twice the horizontal period (hereinafter, referred to as H) with respect to the heads SP2 and SP1, respectively.

[0004] The operation of the conventional video signal processing device configured as described above will be described below with reference to FIGS. 7 and 8. In FIG. 7, the conventional video signal processing apparatus has a reproducing head SP1, SP2 and EP1,
The reproduction signal from EP2 is output to switch circuit 2 via reproduction amplifiers 1S and 1E, respectively. These reproduced signals are switched by the switch circuit 2 and supplied to the video signal demodulation circuit 4, and the demodulated video signal is supplied to the field memory 6 through the A / D converter 5. As a result, the video signals are respectively stored at predetermined addresses, and the stored video signals are sequentially read out and taken out to the output terminal 10 through the D / A converter 9. Further, the above-described head switching signal and address reset signal are supplied to the memory control circuit 11, and a write control signal for the field memory 6 is formed.

When a reproduction signal is output in combination with a head having a slightly shifted mounting position and a different azimuth angle at the time of still image reproduction or variable speed reproduction, a slight mounting position deviation (2H) between the heads causes A time lag of the generated video signal occurs. This deviation can be eliminated by controlling the write address of the field memory 6, and a good reproduction signal can be obtained.

[0006]

However, in the above-described conventional configuration, as shown in FIG.
However, there is a problem that the cost is so large that it cannot be introduced into a product of a popular machine class.

Further, there is a TV for discriminating between a standard signal and a non-standard signal based on the number of Hs between the vertical synchronizing signals.

SUMMARY OF THE INVENTION The present invention has been made to solve such a conventional problem, and it is possible to reduce the cost of a stable image in variable speed reproduction by changing the periodic fluctuation of the vertical synchronizing signal in units of two fields. It is intended to be able to be realized by. It is another object of the present invention to provide a video signal processing apparatus which can discriminate between a standard signal and a non-standard signal based on the H number between vertical synchronization signals without error.

[0009]

According to the first aspect of the present invention, there is provided a signal reproducing means for outputting a non-standard video signal in which the period of a vertical synchronizing signal repeatedly varies with three or more fields as one pattern; Delay amount control means for controlling the delay amount for each field of the non-standard video signal in accordance with the position of the vertical synchronization signal so that the period variation is repeated two field periods; Delay means for delaying the standard video signal by an integral multiple of the horizontal synchronizing signal period in field units.

According to a twelfth aspect of the present invention, there is provided a signal reproducing means for outputting a non-standard video signal in which the period of a vertical synchronizing signal repeatedly varies with three or more fields as one pattern, and an average equal to the average period of the non-standard video signal. A pseudo vertical synchronizing signal generating means having a period and generating a pseudo vertical synchronizing signal at a predetermined timing; a signal synthesizing means synthesizing a pseudo vertical synchronizing signal generated by the pseudo vertical synchronizing signal generating means with a non-standard video signal; A non-standard video signal is delayed for each field according to the position of the vertical synchronizing signal in units of fields so that the periodic fluctuation of the synchronizing signal is repeated in a two-field cycle according to the position of the vertical synchronizing signal or the pseudo vertical synchronizing signal. Delay amount control means for controlling the amount, and a non-standard video signal corresponding to the output of the delay amount control means, which is an integral multiple of the horizontal synchronization signal period in field units. It is characterized in that it comprises a delay means for delaying only while.

According to a twenty-third aspect of the present invention, there is provided a signal reproducing means for outputting a non-standard video signal in which a period of a vertical synchronizing signal repeatedly fluctuates with three or more fields as one pattern, and a position of the vertical synchronizing signal of the non-standard video signal. Delay amount setting means for setting a predetermined delay amount for each field according to the delay, and a delay for delaying the non-standard video signal by an integral multiple of the horizontal synchronization signal period in field units according to the output of the delay amount setting means Means, a signal generating means for generating a pseudo vertical synchronizing signal whose periodic fluctuation is repeated at a predetermined timing of a video signal outputted by the delay means at a two-field cycle, and a pseudo vertical synchronizing signal to a video signal outputted by the delay means. And a signal synthesizing means for synthesizing.

[0012]

According to the present invention having the above features, the vertical synchronizing signal is periodically delayed by a predetermined amount with respect to each field of the video signal in which the period of the vertical synchronizing signal fluctuates repeatedly with three or more fields as one pattern. The periodic fluctuation of the signal is repeated with two fields as one pattern.
Therefore, the number of Hs between the vertical synchronization signals can be kept away from the number of Hs in the case of the standard signal. However, the unstable movement of the TV screen image can be minimized with a very small increase in cost.
In addition, since the periodic fluctuation pattern of the vertical synchronizing signal is the same as that of the still image reproduction, it is possible to use a video signal having an extremely low possibility of an unstable operation of the TV video.

Further, according to the present invention, a pseudo vertical synchronizing signal is synthesized at a predetermined position of a video signal in which the period of the vertical synchronizing signal repeatedly fluctuates with three or more fields as one pattern. By performing the delay, the periodic variation of the vertical synchronization signal is repeated with two fields as one pattern. Therefore, the number of Hs between the vertical synchronization signals can be kept away from the number of Hs in the case of the standard signal. However, unstable movement of the TV screen image can be suppressed with a very small increase in cost. In addition, since the periodic fluctuation pattern of the vertical synchronizing signal is the same as that of the still image reproduction, it is possible to use a video signal having an extremely low possibility of an unstable operation of the TV video.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the video signal processing device according to the first embodiment of the present invention. In the figure, the description of the same components as the conventional example is omitted. In FIG. 1, a capstan 13 contacts and feeds a tape 12 recorded in a standard mode. The FG 14 outputs an FG signal having a frequency proportional to the rotation speed of the capstan 13. The capstan drive circuit 15 causes the capstan 13 to generate torque according to a torque command from the control circuit 20. The CTL head 16 detects a control signal recorded at equal intervals on the tape 12 and outputs a CTL signal. The PFG 18 outputs a PFG signal in which a signal indicating the rotation phase of the cylinder 8 is superimposed on a signal having a frequency proportional to the rotation speed of the cylinder 8. The cylinder drive circuit 17 generates torque in the cylinder 8 according to a torque command from the control circuit 20. The control circuit 20 outputs a torque command for controlling the rotation of the cylinder 8 based on the PFG signal to the cylinder drive circuit 17, and outputs the FG signal and the CT signal.
A torque command is output to the capstan drive circuit 15 so that the tape 12 is fed at a predetermined speed and phase using the L signal. Further, the control circuit 20 controls the HS for switching the head according to the tape feeding phase and the rotation phase of the cylinder at that time.
It outputs a W signal and a delay command d. The delay circuit 23 delays the video signal up to 3H at the maximum in accordance with the delay command d output from the control circuit 20. The TV 19 is a display device that displays the delayed signal e on the screen.

The operation when the magnetic tape recorded in the triple mode in the video signal processing apparatus of the present embodiment configured as described above is reproduced at 3/2 times speed will be described with reference to FIGS. . The tape 12 is fed by the capstan 13 at a speed of 3/2 times the speed of the triple mode while maintaining the relationship between the HSW signal and the CTL signal in the phase relationship shown in FIG. At this time, the outputs of the four heads SP1, SP2, EP1, EP2 attached to the cylinder 8 are shown in FIG.
Are selected by the switch circuit 2 by two HSW signals shown in FIG. Since the head having the maximum output is selected as the switch circuit 2, the heads EP1, EP2, SP in FIG.
A signal that repeats a unit of four fields as one pattern, such as 2, SP1, EP1, EP2,.
This signal is input to the video signal demodulation circuit 4 and the video signal a
Is converted to The video signal a is input to the delay circuit 23, delayed by a predetermined time for each field in accordance with the delay command d in FIG.

Here, the reproduced video signal will be described in more detail. The head selected from the four heads at the timing shown in FIG.
FIG. 2 shows a state where 0 is traced. In this figure, when the tape 12 is fed at 3/2 times the speed of the triple mode, the position at which the head traces the lower end of the track is shifted from the center of the track. It turns out that it changes to. In the triple mode recording of the VHS format, the lower end position of each track is shifted by 0.5H as shown in FIG. Here, the average H number (X) between the vertical synchronizing signals when the tape is fed at n times speed can be obtained by equation (1), where K is the deviation of the lower end position between the tracks. However, the unit is [H]
And the video signal is NTSC. X = 262.5−K (n−1) (1) That is, in the case of the 3/2 × speed of the 3 × mode, K = 0.5,
Since n = 1.5, the average H number is 262.25H. In FIG. 3, the time between the broken lines is the average H number. In the case of the standard mode, the tape position deviation K between the tracks is 1.5H.

The deviation of the timing of the generation of the vertical synchronizing signal due to the tracking is compensated for by the standard reproducing heads SP1 and SP2.
Considering 2H, which is the amount of displacement of the mounting positions of the triple-mode reproducing heads EP1 and EP2, the vertical synchronizing signal generation timing is shifted by a maximum of 2.25H as shown in FIG. Here, in FIG. 3A, α indicates the delay of the synchronization signal of the demodulated video signal a with respect to the control signal CTL of the first field having six fields as one pattern. Due to the difference between the average H number and the vertical synchronizing signal, the H number between the vertical synchronizing signals changes between 260H and 264H as shown in FIG. 3, and the change width becomes 4H. Therefore, the H number of the vertical synchronizing signal for each field of the video signal a is the H number shown in FIG.
The delay of 3H, 0H, and 1H is performed. By doing so, the H number between the vertical synchronization signals is 263.5H, 26 as shown in FIG.
This is a repetition of a two-field cycle like 1.5H.

As described above, according to the embodiment of the present invention, 3
By delaying each field of the video signal a output at the time of 3/2 × speed reproduction in the double mode by 2H, 3H, 0H, and 1H, the variation of the H number between the vertical synchronization signals is repeated in a two-field cycle. Can be. Then, the H number between the vertical synchronization signals can be sufficiently separated from the H number (262.5H) of the standard signal, and the TV signal which discriminates between the standard signal and the non-standard signal based on the H number between the vertical synchronization signals. However, erroneous determination can be eliminated, and unstable movement of the TV screen image can be suppressed.

Further, by making the change of the H number between the vertical synchronizing outputs a repetition of a two-field cycle,
Since the repetition period is the same as that of the video signal at the time of still image reproduction performed by the TR, the possibility of the TV operating abnormally is extremely reduced.

In this embodiment, the fluctuation range of the H number between the vertical synchronizing signals output from the delay circuit is 2.5H, which is smaller than 4H which is a value at the time of reproducing a still image, and the vertical fluctuation of the image is reduced. The roll at the corner of the screen can be kept sufficiently small.

In this embodiment, the tape speed is 3/3 of the triple speed mode.
Although the double speed is described, the fluctuation of H between the vertical synchronization signals can be reduced in units of two fields by appropriately selecting the delay time at other speeds. That is, as shown in Tables 1 and 2, 2/3 speed, 3/4 speed, 5
Also in the case of / 4 × speed and 4/3 × speed, by selecting the delay time as shown in the table, the change of the H number between the vertical synchronizing signals can be changed in the period of two fields.

[Table 1]

[Table 2]

The control circuit 20 stores a pattern of such a delay amount corresponding to the reproduction speed, reads out this signal in synchronization with the HSW signal, and supplies the readout signal to the delay circuit 23 to thereby suppress the fluctuation of the vertical synchronization signal. Shall be suppressed. In this way, it is possible to greatly reduce the vertical swing of the TV image and the horizontal swing of the screen corner with an extremely simple configuration.

Also, when a tape reproduced in the standard mode is reproduced at 2/3 times speed, 3/4 times speed, 5/4 times speed, 4/3 times speed, and 3/2 times speed, the delay time is as follows. By selecting as shown in the table, the H number of the vertical synchronizing signal can be changed in a cycle of two fields.

[Table 3]

[Table 4]

[Table 5]

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a block diagram showing the configuration of the video signal processing device according to the second embodiment of the present invention.
In the figure, the same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description is omitted. In FIG.
2 is recorded in the triple mode and sent by the capstan 13. The control circuit 20A basically controls the rotation of the cylinder 8 and the capstan 13 and outputs the HSW signal and the delay command d as in the control circuit 20 of the first embodiment, but outputs a pseudo vertical synchronization signal generation command. . The pseudo vertical synchronizing signal generation circuit 21 generates a pseudo vertical synchronizing signal based on the timing of a command for generation from the control circuit 20A.

The operation of the video signal processing apparatus according to the embodiment of the present invention configured as described above will now be described with reference to FIG.
This will be described with reference to FIG. The basic overall movement is the same as in the first embodiment except that the feed speed of the tape 12 is 4/3 times that of the triple mode, and the flow of the video signal is also the same as in the first embodiment. .

Next, the video signal to be reproduced will be described in detail. FIG. 5 shows a state where a head selected from the four heads traces the track 120 on the tape 12 at the timing shown in FIG. In this figure, the tape 12 recorded in the triple mode is
It can be seen that the reproduction timing of the vertical synchronizing signal also changes when the transmission is performed at / 3 times speed. The deviation of the timing of generation of the vertical synchronizing signal due to this tracking is caused by the standard reproducing heads SP1 and SP2 and the triple mode reproducing heads EP1 and EP.
In consideration of 2H, which is the amount of displacement of the mounting position 2, the maximum displacement is 2.33H as shown in FIG. The H number between the vertical synchronizing signals is 2 due to the difference between the average H number calculated by the above equation (1) and the vertical synchronizing signal.
It turns out that it changes between 60H-264H. This change is repeated with six fields as one pattern.
Control signal C of the first field of this pattern
The delay of the synchronization signal of the demodulated video signal a with respect to the TL is represented by α. The pseudo vertical synchronizing signal generating circuit 21 generates a pseudo vertical synchronizing signal substantially synchronized with the pseudo vertical synchronizing signal under the control of the control circuit 20A. Here, β indicates the time difference between the pseudo-vertical synchronization signal generated by the pseudo-vertical synchronization generation circuit 21 and the demodulated synchronization signal of the first field having six fields as one pattern. As shown in FIG. 3B, the pseudo vertical synchronizing signal changes its period with six fields as one pattern. Assuming that the phase difference between the video signal and the vertical synchronization signal in the first field of this pattern is β,
The phase difference for each field is β, β + 0.1 as shown.
7H, β + 0.33H, β, β + 0.17H, β + 0.
33H, and the average period of the pseudo vertical synchronization signal is equal to the average H number of the vertical synchronization signal, that is, 262.33H. Then, a delay is performed for each field of the video signal a by the number H shown in FIG. In this way, as shown in FIG. 3E, the H number between the delayed vertical synchronizing signals can be set to be a repetition of two field periods.

As described above, according to the embodiment of the present invention, 3
By delaying each field of the video signal a output at the time of 4/3 speed reproduction in the double mode by 3H, 2H, 3H, 0H, 1H, 0H, the variation of the H number between the vertical synchronizing signals can be changed in a two-field cycle. It can be repeated. Then, all the H numbers between the vertical synchronizing signals are changed to the H number (26
2.5H), and eliminates erroneous discrimination even in a TV in which a standard signal and a non-standard signal are discriminated based on the H number between vertical synchronization signals, thereby suppressing unstable movement of a TV screen image. be able to.

Further, by making the change of the H number between the vertical synchronizing signals a repetition of a two-field cycle, the repetition cycle becomes the same as the H number of the video signal at the time of still picture reproduction currently performed in most VTRs. Therefore, the possibility that the TV operates abnormally is extremely reduced.

Further, in this embodiment, the fluctuation range of the H number between the vertical synchronizing signals is 2H, which is a half of 4H which is a value at the time of reproducing a still image, and the vertical fluctuation of the image and the horizontal fluctuation of the screen corner are sufficiently achieved. Can be kept small.

Although the second embodiment describes the case where the tape speed is 4/3 times the triple speed mode, the fluctuation of H between the vertical synchronizing signals can be reduced by appropriately selecting the delay time even at other speeds. be able to. That is, as shown in Tables 6 and 7, 2/3 speed, 3/4 speed, 5/4 speed, 4 /
Also in the case of the triple speed and the 3/2 speed, the variation of the H number between the vertical synchronization signals can be made in units of two fields by selecting the delay time as shown in the table.

[Table 6]

[Table 7]

[Table 8]

The delay time and the reproduced image of the tape reproduced in the standard mode are also obtained when the tape is reproduced at 2/3, 3/4, 5/4, 4/3, and 3/2 speed. By selecting the time difference between the signal and the pseudo vertical synchronizing signal as shown in the table, the H number of the vertical synchronizing signal can be changed every two fields.

[Table 9]

[Table 10]

[Table 11]

The control circuit 20B stores a pattern of such a delay amount according to the reproduction speed, reads out this signal in synchronization with the HSW signal, and supplies the readout signal to the delay circuit 23 to thereby suppress the fluctuation of the vertical synchronization signal. Shall be suppressed. In this way, it is possible to greatly reduce the vertical swing of the TV image and the horizontal swing of the screen corner with an extremely simple configuration.

Although the video signals reproduced in these embodiments are described for the NTSC system, the same can be realized in the PAL system or the SECAM system, and the present invention is not limited to this embodiment. Absent.

In the first and second embodiments, the delay circuit 23 is provided with the standard reproducing heads SP1 and SP2 and the triple mode reproducing heads EP1 and EP at the time of reproducing the still image or at the double speed.
It can also be used to correct the amount of displacement of the mounting position of P2,
The performance of the VTR can be significantly improved with a slight increase in cost.

Further, in the first and second embodiments, the control circuits 20 and 20A can be realized by software in a microcomputer or a digital signal processor. In that case, the cost of the control circuit unit is increased. It can be realized without it.

The pseudo vertical synchronizing signal generating circuit 21 and the signal synthesizing circuit 22 used in the second embodiment are used at the time of reproducing a still picture in the current VTR. .

Further, in the second embodiment, the video signal a demodulated by the video signal demodulation circuit 4 is the pseudo vertical synchronization signal b
Is synthesized and then delayed by the delay circuit 23. A method of synthesizing the pseudo-vertical synchronization signal at a predetermined position after performing the delay may be considered, and the method is limited to the present embodiment. is not.

In addition, in the above-described second embodiment, the position where the pseudo vertical synchronizing signal is input is fixed for each field. However, the position can be shifted back and forth by fine adjustment as in the case of reproducing a still image. , It is also possible to secure more stable images on more TVs,
The method is not limited to the present embodiment.

[0039]

As described above, according to the present invention, the H number between the vertical synchronizing signals of the non-standard video signal is all changed to the H number (26) of the standard signal.
2.5H). In addition, a stable image can be ensured even in a TV that discriminates between a standard signal and a non-standard signal. By setting the change of the H number between the vertical synchronizing signals to the same repetition period as the H number of the video signal at the time of reproducing the still image, the possibility that the TV operates abnormally can be extremely reduced. large.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a video signal processing device according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a head trace in the embodiment.

FIG. 3 is a timing chart showing video signal processing contents of the embodiment.

FIG. 4 is a block diagram illustrating a configuration of a video signal processing device according to a second embodiment of the present invention.

FIG. 5 is an explanatory diagram showing a head trace in the embodiment.

FIG. 6 is a timing chart showing video signal processing contents of the embodiment.

FIG. 7 is a block diagram illustrating a configuration of a conventional video signal processing device.

FIG. 8 is an explanatory view showing a head configuration of a cylinder.

[Explanation of symbols]

 2 switch circuit 4 video signal demodulation circuit 8 cylinder 12 tape 13 capstan 16 CTL head 19 TV 20, 20A control circuit 23 delay circuit a, e video signal d delay command

──────────────────────────────────────────────────の Continued on the front page (72) Yoshitomi Nagaoka 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (56) References JP-A-63-169190 (JP, A) JP-A-4-326272 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5 / 91-5 / 956 G11B 5/027 501 G11B 20/02

Claims (24)

(57) [Claims] 1. A signal reproducing means for outputting a non-standard video signal in which a period of a vertical synchronization signal repeatedly fluctuates with three or more fields as one pattern, and a method wherein the period fluctuation of the vertical synchronization signal is a repetition of two field periods. Delay amount control means for controlling a delay amount for each field of the non-standard video signal according to a position of a vertical synchronization signal; and horizontally synchronizing the non-standard video signal in field units according to an output of the delay amount control means. A video signal processing device comprising: delay means for delaying by a time that is an integral multiple of the signal period. 2. The delay amount control means according to claim 1, wherein the non-standard video signal reproduced at 3/2 × speed in the 3 × speed mode has 2H, 3H, 0 for each field in units of 4 fields.
2. The video signal processing device according to claim 1, wherein the video signal processing device controls so as to delay H and 1H. 3. The delay amount control means controls the 3H, 2H, 3H for each field in units of 6 fields for a non-standard video signal reproduced at 2/3 times speed of the 3 × speed mode.
2. The video signal processing device according to claim 1, wherein the video signal processing device controls so as to delay H, 2H, 1H, and 0H. 4. The delay amount control means controls the 3H, 2H, 3H for each field in units of 8 fields for a non-standard video signal reproduced at 3/4 speed in a 3 × speed mode.
2. The video signal processing device according to claim 1, wherein the video signal processing device controls so as to delay H, 2H, 3H, 2H, 1H, and 0H. 5. The non-standard video signal reproduced at 5/4 × speed in a 3 × speed mode, wherein the delay amount control means sets 4H, 2H, 4H for each field in units of 8 fields.
2. The video signal processing apparatus according to claim 1, wherein the video signal processing apparatus controls so as to delay H, 2H, 4H, 2H, 2H, and 0H. 6. The delay amount control means controls the 4H, 2H, 4H for each field in units of 6 fields for a non-standard video signal reproduced at 4/3 times speed in a 3 × speed mode.
2. The video signal processing device according to claim 1, wherein the video signal processing device controls so as to delay H, 2H, 2H, and 0H. 7. The delay amount control means according to claim 2, wherein the delay amount control means comprises a
1H, 4H, 2H, 2H,
2. The video signal processing apparatus according to claim 1, wherein the video signal processing apparatus controls so as to delay 1H, 0H, and 2H. 8. The delay mode control means according to claim 3, wherein said delay mode control means comprises:
For non-standard video signals reproduced at / 4x speed, 2H, 4H, 3H,
2. The video signal processing device according to claim 1, wherein the video signal processing device controls so as to delay 5H, 0H, 2H, 1H, and 3H. 9. The delay amount control means according to claim 5, wherein
For non-standard video signals reproduced at / 4x speed, 5H, 3H, 4H,
2. The video signal processing device according to claim 1, wherein the video signal processing device controls to delay 2H, 3H, 1H, 2H, and 0H. 10. The non-standard video signal reproduced at 4/3 times the speed of the standard mode, wherein the delay amount control means sets 2H, 4H, 1 for each field in units of 6 fields.
2. The video signal processing device according to claim 1, wherein the video signal processing device controls so as to delay H, 2H, 0H, and 1H. 11. The non-standard video signal reproduced at 3/2 times the speed of the standard mode, wherein the delay amount control means sets 2H, 3H, 0 for each field in units of 4 fields.
2. The video signal processing device according to claim 1, wherein the video signal processing device controls so as to delay H and 1H. 12. A signal reproducing means for outputting a non-standard video signal in which the period of a vertical synchronizing signal repeatedly fluctuates with three or more fields as one pattern, an average period equal to the average period of the non-standard video signal, Pseudo-vertical synchronization signal generating means for generating a pseudo-vertical synchronization signal at the timing of: signal synthesizing means for synthesizing the pseudo-vertical synchronization signal generated by the pseudo-vertical synchronization signal generation means with the non-standard video signal; Alternatively, the non-standard video signal is delayed for each field according to the position of the vertical synchronizing signal in units of fields so that the periodic fluctuation of the synchronizing signal is repeated in a two-field cycle according to the position of the pseudo vertical synchronizing signal. Delay amount control means for controlling, the non-standard video signal according to an output of the delay amount control means A video signal processing apparatus characterized by comprising a delay means for delaying only several times the time. 13. The non-standard video signal reproduced at 4/3 × speed in the 3 × speed mode, wherein the delay amount control means sets 3H, 2H, 3H for each field in units of 6 fields.
13. The video signal processing device according to claim 12, wherein the video signal processing device controls to delay H, 2H, 1H, and 0H. 14. A delay amount control means for a non-standard video signal reproduced at 2/3 times speed in a 3 × speed mode, wherein 3H, 2H, 3
13. The video signal processing device according to claim 12, wherein the video signal processing device controls to delay H, 2H, 1H, and 0H. 15. The non-standard video signal reproduced at 3/4 speed in the 3 × speed mode, wherein the delay amount control means performs 3H, 2H, 3H operation for each field in units of 8 fields.
13. The video signal processing device according to claim 12, wherein the video signal processing device controls to delay H, 2H, 3H, 2H, 1H, and 0H. 16. The delay amount control means controls the 3H, 2H, 3H for each field in units of 8 fields for a non-standard video signal reproduced at 5/4 times speed in the 3 × speed mode.
13. The video signal processing device according to claim 12, wherein the video signal processing device controls to delay H, 2H, 3H, 1H, 1H, and 0H. 17. The non-standard video signal reproduced at 4/3 × speed in a 3 × speed mode, wherein the delay amount control means uses 3H, 2H, 3H for each field in units of 6 fields.
13. The video signal processing device according to claim 12, wherein the video signal processing device controls to delay H, 2H, 1H, and 0H. 18. The non-standard video signal reproduced at a 3/2 × speed in a 3 × speed mode, wherein the delay amount control means uses 1H, 2H, 1H for each field in units of 4 fields.
13. The video signal processing device according to claim 12, wherein control is performed to delay H and 0H. 19. The delay amount control means controls the 1H, 3H, 2H for each field in units of 6 fields for a non-standard video signal reproduced at 2/3 times the speed of the standard mode.
13. The video signal processing device according to claim 12, wherein the video signal processing device controls to delay H, 0H, 0H, and 1H. 20. The non-standard video signal reproduced at a 3 / 4-times speed of the standard mode, wherein the delay amount control means sets 2H, 2H, 3
13. The video signal processing device according to claim 12, wherein the video signal processing device controls to delay H, 3H, 0H, 0H, 1H, 1H. 21. A non-standard video signal reproduced at 5/4 times the speed of a standard mode, wherein the delay amount control means performs 3H, 4H, 2
13. The video signal processing device according to claim 12, wherein the video signal processing device controls to delay H, 3H, 1H, 2H, 01, and 0H. 22. The non-standard video signal reproduced at 4/3 times the speed of the standard mode, wherein the delay amount control means sets 2H, 3H, 1 for each field in units of 6 fields.
13. The video signal processing device according to claim 12, wherein control is performed such that H, 1H, 0H, and 0H are delayed. 23. The non-standard video signal reproduced by the 3/2 × speed of the standard mode, wherein each of the fields is 2H, 2H, 0 for each field in units of 4 fields.
13. The video signal processing device according to claim 12, wherein control is performed to delay H and 0H. 24. A signal reproducing means for outputting a non-standard video signal in which the period of a vertical synchronizing signal repeatedly fluctuates with three or more fields as one pattern; Delay amount setting means for setting a predetermined delay amount to: delay means for delaying the non-standard video signal by an integral multiple of a horizontal synchronization signal period in field units according to an output of the delay amount setting means; Signal generating means for generating a pseudo vertical synchronizing signal whose periodic fluctuation is repeated at a predetermined timing of the video signal output by the delay means at a two-field cycle; and synthesizing the pseudo vertical synchronizing signal with the video signal output by the delay means A video signal processing apparatus comprising: