JP3159153B2 - Nonvolatile semiconductor memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device, and more particularly, to a stacked gate type memory device.
The present invention relates to a flash memory including cells and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, among electrically rewritable nonvolatile semiconductor memory devices (EEPROMs), a flash memory having a function of electrically and collectively erasing a plurality of memory cells in a required area at the same time. Some are composed of stacked gate type memory cells.

Referring to FIG. 28, which is a schematic plan view of a flash memory, and FIG. 29, which is a schematic cross-sectional view taken along the XX 'line and the YY' line of FIG. An example of a conventional flash memory including the following memory cells is as follows.

It has a (100) plane orientation and has 2 × 10 17 c
P-type silicon substrate 2 having a surface impurity concentration of about m3
A field oxide film 202 having a thickness of about 0.6 μm is provided in an element isolation region on the surface of the device 01, and a stacked gate type memory is provided in an element formation region. Each memory cell is provided on the surface of the P-type silicon substrate 201 via the first gate oxide film 206 having a thickness of about 10 nm provided on the surface of the P-type silicon substrate and the first gate oxide film 206. A floating gate electrode 213 made of an N-type first polycrystalline silicon film 207 having an impurity concentration of about 1 × 10 19 cm 3 and a thickness of about 150 nm, and provided on the surface of the floating gate electrode 213 (film thickness 7 nm
A silicon oxide film having a thickness of about 10 nm, a silicon nitride film having a thickness of about 10 nm, and a silicon oxide film having a thickness of about 3 nm are stacked on the floating gate electrode 213 with the insulating film 209 interposed therebetween. Film thickness 1
A control gate electrode 212 comprising an N + type second polycrystalline silicon film 211 of about 50 nm;
The first source regions 217ab, 21 provided on the surface of
7cd, and a first drain region 218 provided on the surface of the P-type silicon substrate.

The first drain region 218 is formed of, for example, an N + type diffusion layer which is self-aligned with the control gate electrode 212a and the like, the control gate electrode 212a and the like, and the field oxide film 202. One first drain region 218 is shared by two memory cells. Each first drain region 2
Reference numeral 18 is connected to a bit line 216a provided in the interlayer insulating film 215 through a bit contact hole 219a provided in the interlayer insulating film on which the surface of the memory cell is placed. The bit lines 216a and the like are orthogonal to the control gate electrodes 212a and the like via the interlayer insulating film 215.

The first source region 217ab and the like are formed of an N-type diffusion layer provided on the surface of a P-type silicon substrate 201. For example, the first source region 217ab and the like are provided on the surface of the P-type silicon substrate 201 in a self-aligned manner with the control gate electrode 212a and the like, the control gate electrode 212a and the like, the floating gate electrode 213, and the field oxide film 202. A required number of memory cells among the memory cells belonging to the gate electrode 212a and the like and the control gate electrode 212a and the like are shared. Each first source region 217
ab and the like are connected to wiring provided in parallel with the bit lines 216a and the like on the surface of the interlayer insulating film 215 via contact holes (not shown) provided in the interlayer insulating film 215 for every 16 bits, for example. Have been.

The outline of the above-mentioned writing / erasing of the memory cell is as follows. The applied voltage to the first drain region 218, the applied voltage to the first source region 217ab and the like, the control gate electrode 212
Assuming that the voltage applied to a and the like and the voltage applied to the P-type silicon substrate 201 are VDD, VSS, ΔCG, and VSUB, respectively, the following is obtained. For example, VSS = 0V, VSUB = 0V, VDD = 5.2V only for the bit line 216a (other bit lines 21
6b is ΔDD = 0V) and V is applied only to the control gate electrode 212b.
CG = 12V (VCG = 0 for other control gate electrodes 212a, etc.)
By setting V), writing is performed only on the memory cells belonging to the bit line 216a and the control gate electrode 212b. The potential of the floating gate electrode 213 of this memory cell is a value divided by the capacitance ratio between the first gate oxide film 206 and the insulating film 209, and in this memory cell (turned on), A current flows between the first source region 217ab and the first source region 218ab. If the potential of the floating gate electrode 213 of this memory cell is about 5.2 V, the pinch-off point will be near the first drain region 218, and the hot field generated by the increase in the electric field strength near this point will be described. Electrons (first gate oxide film 20)
Electrons having an energy higher than the insulation potential energy of No. 6 are injected into the floating gate electrode 213. Since the potential of the floating gate electrode 213 is pushed down to a negative level as the maximum amount of electrons that enter the floating gate electrode 213 increases, the threshold voltage of the memory cell (as viewed from the control gate electrode 212) becomes positive. To about 7V.

[0008] Erasing (writing data) of a memory cell is to extract electrons injected into the floating gate electrode 213 from the floating gate electrode 213. Erasing in the flash memory is performed, for example, for each individual memory cell array. For example, the first source region 217ab or the like has VSS
= 8V, (all control gate electrodes 212a, 212
b, 212c, etc.) VCG = 0V, VSUB = 0V,
VDD (at all first drain regions 218);

The bit line 216a and the control gate electrode 212
If writing has been performed only on the memory cell belonging to b, this memory cell has
The potential difference applied to the first gate oxide film 206 becomes higher than 8 V, and a strong electric field is applied to the first gate oxide film 206. As a result, Fowler-Noldheim based on the quantum tunnel effect
When a current (hereinafter, referred to as an FN current) flows, electrons are extracted from the floating gate electrode 213 of the memory cell. In a flash memory, even when erasing is performed under certain conditions, the threshold voltage (erasing threshold voltage) of each erased memory cell varies at about 2V.
If there is at least one memory cell having an erase threshold voltage of 0 V or less, writing cannot be performed on a memory cell sharing a bit line with the memory cell.

In order to perform the operation of the memory cell described above, that is, writing, erasing, reading, and the like, a dedicated circuit (hereinafter referred to as a peripheral circuit) is required. Be transposed. Referring to FIG. 30 which is a schematic plan view of the structure of the MOS transistor for the peripheral circuit, and FIG. 31 which is a schematic cross-sectional view taken along line AA ′ and line BB ′ of FIG.
An example of the S transistor is as follows.

In the element isolation region on the surface of the same P-type silicon substrate 201 as that on which the memory cell portion is formed, a film thickness of 0.
A field oxide film 202 of about 6 μm is provided, and a MOS transistor is formed in an element formation region. M
The OS transistor includes a second gate oxide film 210 having a thickness of about 25 nm provided on the surface of a P-type silicon substrate 201.
And a gate electrode 21 made of an N-type second polycrystalline silicon film 211 having a thickness of about 150 nm on the surface of the P-type silicon substrate 201 via the second gate oxide film 210.
3 and the second provided on the surface of the P-type silicon substrate 201.
It comprises a drain region 219 and a second source region 220 provided on the surface of the P-type silicon substrate 201.

As described above, the flash memory requires at least two types of transistors: a memory cell transistor that stores information and a MOS transistor that forms a peripheral circuit portion that controls the information. It is difficult to make the gate oxide film thickness of these two types of transistors the same. This is because the film thickness of the first gate oxide film 206 of the memory cell transistor that stores information has a film thickness that can be erased with an FN current based on the quantum tunnel effect because erasing is performed at a desired time and at a desired voltage. For example, 10
The order of nm is appropriate. In contrast, the MO of the peripheral circuit
The thickness of the second gate oxide film 210 of the S transistor is set, for example, in the second drain region 220 of the MOS transistor.
At the time of writing, a voltage of 12 V applied to the control gate electrode may be applied.
20 requires a junction breakdown voltage that does not cause breakdown, and a sufficient junction breakdown voltage cannot be obtained with a film thickness of about 10 nm of the first gate oxide film 206 of the memory cell transistor described above. The thickness of the gate oxide film 206 needs to be larger than that of the gate oxide film 206, and is set to, for example, about 25 nm. Therefore, in the flash memory, it is necessary to form at least two types of gate oxide films having different thicknesses, such as the first gate oxide film 206 of the memory cell transistor and the second gate oxide film 210 of the transistor in the peripheral circuit portion.

FIG. 30 is a schematic sectional view taken along the line YY ′ of FIG.
Referring to FIG. 32, which also shows a schematic cross-sectional view taken along the line BB ′, the conventional flash memory is manufactured as follows. First, a field oxide film is formed in a device isolation region on the surface of the P-type silicon substrate 201 (FIG. 3).
2). Note that in the drawings, a region where a memory cell is formed and a region where a transistor of a peripheral circuit is formed are illustrated in the same drawing for convenience. Subsequently, an oxide film 203 of about 40 nm is formed by a thermal oxidation method (FIG. 33). After this,
In the destruction area where the peripheral circuit is to be formed, ions are implanted into the diffusion layer region of each transistor according to the required transistor, and the threshold value of each transistor is controlled (not shown). Thereafter, the portion other than the memory cell portion is covered with the photoresist 205. If necessary, at this time, in order to control the threshold value of the memory cell, polon is implanted into the cell (FIG. 34). Subsequently, only the oxide film 203 in the memory cell formation planned region is removed by a wet etching method to expose the surface of the P-type silicon substrate 201 (FIG. 35). Subsequently, after removing the photoresist 205, a first gate oxide film 206 of about 10 nm is formed by, for example, a mature oxidation method (FIG. 36). Subsequently, the above-described first gate oxide film 206 is formed.
A first polycrystalline silicon film having a thickness of about 150 nm
It is formed by the VD method (FIG. 37). Then, the first
The polycrystalline silicon film is patterned by a known photolithography method to form a first polycrystalline silicon film pattern 208 (FIG. 38). Subsequently, an insulating film 209 is formed on the above-described first polycrystalline silicon film pattern 208 and the P-type silicon substrate 201 to be a peripheral transistor portion. The insulating film 209 is, for example, a silicon oxide film having a thickness of about 7 nm, a silicon nitride film having a thickness of about 10 nm, and
A silicon oxide film of about nm is sequentially laminated (FIG.
9). Subsequently, the memory cell portion is
The silicon oxide film, the silicon nitride film, and the silicon oxide film, which are stacked in a region to be a peripheral transistor, are sequentially etched and removed.
The surface is exposed (FIG. 40).

Subsequently, a second gate oxide film 210 is formed for the peripheral transistor. For example, using a thermal oxidation method,
An oxide film of about 5 nm is formed (FIG. 41). At this time, an oxide film is also formed on the insulating film 209 in the memory cell portion. In general, the insulating film 209 often has a three-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film. Since the silicon nitride film is included in the film 209 and the silicon nitride film is less likely to be thermally oxidized when the second gate oxide film 210 is formed, the thickness of the second gate oxide film 210 in the memory cell portion is Hardly change.

Subsequently, a second polycrystalline silicon film 211 is formed on the insulating film 209 in the above-mentioned memory cell portion and on the second gate oxide film 210 in the peripheral transistor later by the CVD method (FIG. 4). 42). continue,
A region to be a control gate electrode 212 of a memory cell and a region for a peripheral circuit later are covered with a photoresist 205, and the above-described second polysilicon film 211, insulating film 209 and polysilicon film pattern 208 are sequentially patterned. The control gate electrode 212 made of the second polysilicon film and the floating gate electrode 213 made of the first polysilicon film
Is formed (FIG. 43).

Subsequently, a region where a memory cell is to be formed and a region which will be a gate electrode of a peripheral transistor later are covered with a photoresist 205 and patterned to form a gate electrode 214 (FIG. 44).

Thereafter, in the memory cell portion, ion implantation and heat treatment are performed to form a first drain region 218 and a first source region 217ab (not shown). Thereafter, in the peripheral transistor portion, ion implantation and heat treatment are performed to form a second drain region 220 and a second source region 221 (not shown). afterwards,
An interlayer insulating film 215 is formed by a CVD method, a necessary portion of the interlayer insulating film 215 is removed, and a bit contact 219a is formed.
Are connected to the bit line 216 which is an aluminum electrode through the like (FIG. 45).

[0018]

However, the conventional manufacturing method has the following problems. In order to form at least two types of gate oxide films, in the step before forming the gate oxide film in the memory cell formation region, the area other than the memory cell formation frame is covered with a photoresist, and the oxide film is etched. In the step of stripping the silicon substrate, the surface of the silicon substrate in the memory cell formation planned area is exposed to a stripping liquid. Thereafter, when a gate oxide film is formed in the memory cell formation planned area, the surface of the P-type silicon substrate is affected by the photoresist stripper, and the quality of the gate oxide film locally deteriorates. There has been a problem that the variation in threshold voltage is large.

Therefore, in the present invention, at least two or more types of oxide films having different film thicknesses, that is, the memory cell portion, are manufactured by a simple and easy-to-control manufacturing method without deteriorating the reliability of the gate oxide film in the memory cell portion. An object of the present invention is to provide a nonvolatile semiconductor memory device capable of forming a gate oxide film and a gate oxide film of a peripheral circuit portion, and a method of manufacturing the same.

[0020]

According to the present invention, in order to achieve the above-mentioned object, a field oxide film is formed in a device isolation region on a surface of a P-type silicon substrate, and a device is formed on a surface of the P-type silicon substrate. After forming an oxide film by thermal oxidation in the region, a nitride film is formed on the entire surface, and the nitride film is removed leaving only the memory cell formation planned region, and then thermally oxidized to form a peripheral circuit planned frame region oxide film. After increasing the film thickness of
The oxide film on the nitride film is removed, and the nitride film is removed. The entire oxide film is etched by a wet etching method to expose the P-type silicon substrate surface only in a memory cell formation planned region. To form a gate oxide film in the memory cell formation planned region, then form an N-type polycrystalline silicon film having a required impurity concentration on the entire surface, and pattern the polycrystalline silicon film to form a predetermined polycrystalline silicon film. After forming a pattern and forming an insulating film on the entire surface, the insulating film in the peripheral circuit planned region was removed to expose the P-type silicon substrate surface, and thermal oxidation was performed to form a gate oxide film in the peripheral circuit planned region. Thereafter, a conductor film is formed on the entire surface, and the conductor film, the insulating film,
And sequentially patterning the polycrystalline silicon film pattern to form a control gate electrode composed of the conductor film and a floating gate electrode composed of the polycrystalline silicon film pattern,
The present invention is characterized in that the conductor film is patterned to form a gate electrode made of the conductor film in a peripheral circuit scheduled area.

[0021]

Before forming the first gate oxide film of the memory cell, the first gate oxide film can be formed after removing the oxide film existing in the frame area where the memory cell is to be formed by wet etching. It is possible to obtain a flash memory with little deterioration in film quality and little variation in threshold voltage after erasing.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1, which is a schematic plan view of a flash memory, and FIG. 2, which is a schematic cross-sectional view taken along line XX ′ and line YY ′ of FIG. 1, will be described. The gate type and source erase type memory cells are as follows.

(100) plane orientation, 2 × 10 17 c
P-type silicon substrate 101 having an impurity concentration of about m-3
A field oxide film 102 having a thickness of about 0.6 μm is provided in an element isolation region on the surface of the semiconductor device, and a stack gate type memory cell is provided in an element formation region. Each memory cell includes a first gate oxide film 106 having a thickness of about 10 nm provided on the surface of a P-type silicon substrate 101,
P-type silicon substrate 10 via first gate oxide film 106
A floating gate electrode 113 made of an N-type polycrystalline silicon film having an impurity concentration of about 1.times.10@19 cm @ -3 and a thickness of about 150 nm provided on the surface of the floating gate electrode 113; (A silicon oxide film having a thickness of about 7 nm, a silicon nitride film having a thickness of about 10 nm, and a silicon oxide film having a thickness of about 3 nm are stacked) and a floating gate with the insulating film 109 interposed therebetween. Also serves as a word line provided on the electrode 113 (for example,
A control gate electrode 112a, 112b, 112c, etc. having a film thickness of about 150 nm; a first source region 117ab, 117cd, etc. provided on the surface of the P-type silicon substrate 101; 101, and a drain region 118 provided on the surface of the substrate 101.

The first drain region 118 is composed of, for example, an N + type diffusion layer which is self-aligned with the control gate electrode 112a and the like, the control gate electrode 112a and the like, and the field oxide film 102. One first drain region 118 is shared by two memory cells. Each first drain region 1
Reference numeral 18 is connected to a bit line 116a and the like provided in the interlayer insulating film 115 through a bit contact hole 119a and the like provided in the interlayer insulating film covering the surface of the memory cell. The bit lines 116a and the like are orthogonal to the control electrodes 112a and the like via the interlayer insulating film 115. First source region 1
17ab and the like are constituted by an N-type diffusion layer provided on the surface of the P-type silicon substrate 101. For example, the first source region 117ab and the like are provided on the surface of the P-type silicon substrate in a self-aligned manner with the control gate electrode 112a and the like, the control gate electrode 112a and the like, the floating gate electrode 113 and the field oxide film 102, and A required number of memory cells among the memory cells belonging to the gate electrode 112a and the like and the control gate electrode 112a and the like are shared. Each first source region 117ab or the like is provided with a contact hole (not shown) provided in the interlayer insulating film 115 for every 16 bits, for example.
Through the bit line 11 on the surface of the interlayer insulating film 115.
6a and the like are connected in parallel.

FIG. 3 is a schematic plan view of the structure of a MOS transistor for a peripheral circuit, and FIG.
Referring to FIG. 4 which is a schematic cross-sectional view taken along the line B ′, an example of a MOS transistor for a peripheral circuit is as follows.

The element isolation region on the surface of the P-type silicon substrate 101 on which the memory cell portion is formed has a thickness of 0.3 mm.
A field oxide film 102 of about 6 μm is provided, and a MOS transistor is formed in an element formation region. M
The OS transistor includes a second gate oxide film 110 having a thickness of about 25 nm provided on the surface of a P-type silicon substrate 101.
And a gate electrode 11 made of an N-type second polycrystalline silicon film 111 having a thickness of about 150 nm on the surface of the P-type silicon substrate 101 via the second gate oxide film 110.
3 and the second provided on the surface of the P-type silicon substrate 101.
It is composed of a drain region 119 and a second source region 120 provided on the surface of the P-type silicon substrate 101.

FIGS. 1, 2, 3, 4, 5 and Y in FIG.
A schematic cross-sectional view of the manufacturing process along the line Y ′ and BB ′ in FIG.
Referring to FIG. 5 to FIG. 23, which also show cross-sectional area diagrams of the manufacturing process with lines, the flash memory of the present embodiment is manufactured as follows.

First, having a (100) plane orientation, 2 × 10
P-type silicon substrate 1 having a surface impurity of about 17 cm-3
A field oxide film 102 having a film thickness of about 0.6 μm is formed in the element isolation region on the surface of No. 01 by a thermal oxidation method (FIG. 5). Next, a first oxide film 103 is formed in the element formation region by a thermal oxidation method (FIG. 6). Thereafter, if necessary, ion implantation or the like is performed on the element region in the peripheral circuit portion to obtain desired characteristics. Do.

Next, a nitride film 104 is formed on the entire surface of the wafer, for example, to a thickness of about 120 nm by a CVD method (FIG. 7). Next, the memory cell formation planned area is covered with the photoresist 105 by using a known photolithography method (FIG. 8). Next, the nitride film 104 is left in the area where the memory cell is to be formed, and the vacant film in the peripheral circuit portion is removed by dry etching (FIG. 9).

Next, thermal oxidation is performed, and as a result, the film thickness of the first oxide film 103 in the peripheral circuit scheduled region increases to, for example, 8
0 nm. On the other hand, on the nitride film 104 in the memory cell planned region, the oxide film hardly grows because the nitride film 104 is hardly oxidized. The oxide film existing in the above is not shown). Next, the oxide film is removed by a wet etch method in order to remove the oxide film existing on the nitride film 104 (FIG. 11). Next, the nitride film 104 existing in the storage area where the memory cell is to be formed is removed by wet etching (FIG. 12). At this time, the thickness of the oxide film existing in the region where the memory cell is to be formed is greatly different from the thickness of the oxide film existing in the region where the peripheral circuit transistor is to be formed.

Next, the oxide film existing in the memory cell forming region is removed by a wet etching method (FIG. 13).
By utilizing the difference between the thickness of the oxide film existing in the memory cell formation scheduled area and the thickness of the oxide film existing in the peripheral circuit portion, only the oxide film existing in the memory cell formation scheduled area is removed.
The oxide film still exists in the frame area where the peripheral circuit is to be formed.

Next, oxidation is performed by thermal oxidation to form an oxide film in the element formation region (FIG. 14). At this time, the first gate oxide film 206 is formed in the memory cell forming region, and the peripheral circuit forming region is further oxidized. next,
A first polycrystalline silicon film 107 having a thickness of, for example, about 150 nm is formed on the entire surface of the wafer by a CVD method (FIG. 15).
Next, the first polycrystalline silicon film 107 is patterned in a stripe shape (so as to be parallel to the bit line) (FIG. 1).
6).

Next, the insulating film 1 having a total thickness of about 20 nm
09 is formed on the entire surface. This insulating film 109 is formed as follows. A silicon oxide film (not shown) having a thickness of about 7 nm formed by a high temperature vapor deposition method and a low pressure vapor deposition method (LP)
A silicon nitride film (not shown) by CVD) is left, and a silicon oxide film (not shown) having a thickness of about 3 nm is formed on the surface of the silicon nitride film (FIG. 17).

Next, the memory cells to be formed are covered with a photoresist 105, and the silicon oxide film, silicon nitride film, and silicon oxide film existing in the peripheral circuit forming region are sequentially removed to form a peripheral circuit. The P-type silicon substrate 101 in the expected deposit area is exposed (FIG. 18). Next, a second gate oxide film 110 for a peripheral circuit transistor is formed to a thickness of, for example, 25 nm by a thermal oxidation method (FIG. 19). Next, an N + type second polycrystalline silicon film 111 is formed on the entire surface (FIG. 20).

Next, in the memory cell forming region, the second polycrystalline silicon film 111, the insulating film 109 and the polycrystalline silicon film pattern 108 are sequentially patterned to form a control gate electrode made of the second polycrystalline silicon film 111. 11
2a, 112b, 112c and the like are formed with the floating gate electrode 113 made of the first polysilicon film pattern 108 (FIG. 21). In the embodiment, the control gate electrode 11 is formed using the N + type second polysilicon film 111 as a material.
2, the present invention is not limited to this, and the control gate electrode may be formed from a polycide film or a silicide film.

Next, in the area where the peripheral circuit is to be formed, the second
The polycrystalline silicon film 111 is patterned to form a gate electrode 114 made of the second polycrystalline silicon film 111 (FIG. 22). Thereafter, a first source region 117 and a first drain region 118 are formed in a region where a memory cell is to be formed (not shown). Also in the peripheral circuit spare region, the second drain region 120 and the second source region 12
1 (not shown).

Next, a BPS having a thickness of about 0.8 μm is formed on the entire surface.
An interlayer insulating thin film 115 made of a G film is formed (FIG. 2).
3). It should be noted that the control gate electrode 112a and the like
If not composed of polycrystalline silicon film, BPS
Prior to the formation of the G film, it is desirable to form a silicon oxide film of a required thickness by a high temperature vapor deposition method or the like. A bit contact 119a that meets the first drain region 118,
119b and the like are formed on the interlayer insulating film 115. For example, an aluminum-based metal film having a thickness of about 0.9 μm is formed on the entire surface, and this metal film is patterned to form a bit line 11.
6a and 116b are formed (FIGS. 1 and 2).

Here, if any quality deterioration occurs in the first gate oxide film 106 where the memory cell is located, the TE quality as shown in FIG.
There is a method of measuring the G pattern. In this TEG pattern, for example, 1000 memory cells are formed, their respective control gate electrodes are combined into one, each drain region is combined into one, and each source region is combined into one. Voltage can be applied from outside. The terminals of the control gate electrode, the drain region, and the source region are denoted by VCCG, VDDP, and VSSP, respectively, and the terminal of the P-type silicon substrate is denoted by VSUBP.

In order to evaluate the deterioration of the quality of the first gate oxide film using this TEG pattern, first, the TE
The G pattern is irradiated with ultraviolet light to electrically neutralize the floating gate electrode. Thereafter, all the memory cells are erased. At this time, erasing is performed by applying a voltage only to the source region.
Since excessive current flows in the source region, a positive voltage is applied to the source region and a negative voltage is applied to the control gate electrode. Thereafter, 1 V is applied to the drain region, and the voltage of the control gate is changed from -5 V to 5 V in steps of 0.1 V, and the drain current at this time is measured. The value of the drain current at this time is the sum of the drain currents of each memory cell because 1000 memory cells are connected in parallel (FIG. 25).

The first of each of the 1000 memory cells
When a certain part of the gate oxide film deteriorates the quality,
The erasing speed is faster than other normal memory cells, and as the erasing progresses, the difference in the drain current characteristics between the normal memory cell and the deteriorated memory cell appears remarkably. The current characteristic has a bump (FIG. 26). On the other hand, when the quality of all the first gate oxide films of each of the 1000 memory cells does not deteriorate, the drain current characteristics have no bumps. Therefore, if a certain drain current value in this drain current characteristic, for example, a value of VCGP when flowing 1 × 10 −8 A (hereinafter referred to as a threshold voltage) is measured in a wafer surface,
The degree of deterioration of the quality of the first gate oxide film can be evaluated. The smaller the variation in the threshold voltage, the less bumps in the drain current characteristics, and the smaller the variation in erase in all the memory cells.

The TEG according to the conventional method and the method according to the present invention are used.
A pattern was manufactured, and variations in threshold voltage were evaluated (FIG. 27). For erasing, apply -12 V to the control gate, apply 15 V to the source region, open the drain region, set the P-type silicon substrate to 0 V, and apply the above pulse to the TEG pattern for 0.1 second. I went. According to the manufacturing method of the present invention, the variation of the threshold voltage is smaller than that of the conventional manufacturing method.

As described above, in this embodiment, before the first gate oxide film of the memory cell is formed, the oxide film existing in the memory cell forming region is removed by the wet etching method, and then the first gate oxide film is formed. Can be obtained, a flash memory with less variation in threshold voltage after erasing can be obtained. Further, it is easy to form at least two types of oxide films having different thicknesses, that is, a gate oxide film in a memory cell portion and a gate oxide film in a peripheral circuit portion.

[0043]

As described above, according to the present invention, before the first gate oxide film of the memory cell is formed, the oxide film existing in the memory cell formation region is removed by the wet etching method. One gate oxide film can be formed. Therefore, the flash memory having the memory cell of the present invention
A flash memory with less variation in threshold voltage after erasing can be obtained. Further, it is easy to form at least two types of oxide films having different thicknesses, that is, a gate oxide film in a memory cell portion and a gate oxide film in a peripheral circuit portion.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of a memory cell portion according to an embodiment of the present invention, in which (a) is a line XX ′ of FIG.
(B) is a schematic sectional view taken along line YY '.

FIG. 3 is a schematic plan view of a transistor in a peripheral circuit according to an embodiment of the present invention.

4A and 4B are schematic cross-sectional views of a transistor in a peripheral circuit portion according to one embodiment of the present invention, in which FIG. 4A is a schematic cross-sectional view taken along line AA ′ of FIG. 3, and FIG. It is.

FIG. 5 illustrates a manufacturing process according to an embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view taken along line YY ′ in FIG. 1 and line BB ′ in FIG. 3.

FIG. 6 illustrates a manufacturing process according to an embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view taken along line YY ′ in FIG. 1 and line BB ′ in FIG. 3.

FIG. 7 illustrates a manufacturing process according to an embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view taken along line YY ′ in FIG. 1 and line BB ′ in FIG. 3.

FIG. 8 shows a manufacturing process of one embodiment of the present invention,
FIG. 2 is a schematic cross-sectional view taken along line YY ′ in FIG. 1 and line BB ′ in FIG. 3.

FIG. 9 shows a manufacturing process of one embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view taken along line YY ′ in FIG. 1 and line BB ′ in FIG. 3.

10 shows a manufacturing process of one embodiment of the present invention, and also shows a schematic cross-sectional view taken along line YY ′ in FIG. 1 and line BB ′ in FIG.

11 shows a manufacturing process of one embodiment of the present invention, and also shows a schematic cross-sectional view taken along line YY ′ in FIG. 1 and line BB ′ in FIG.

12 shows a manufacturing process of one embodiment of the present invention, and also shows a schematic cross-sectional view taken along line YY ′ in FIG. 1 and line BB ′ in FIG.

13 shows a manufacturing process of one embodiment of the present invention, and also shows a schematic cross-sectional view taken along line YY ′ in FIG. 1 and line BB ′ in FIG.

14 shows a manufacturing process of one embodiment of the present invention, and also shows a schematic cross-sectional view taken along line YY ′ in FIG. 1 and line BB ′ in FIG.

15 shows a manufacturing process of one embodiment of the present invention, and also shows a schematic cross-sectional view taken along line YY ′ in FIG. 1 and line BB ′ in FIG.

16 shows a manufacturing process of one embodiment of the present invention, and also shows a schematic cross-sectional view taken along line YY ′ in FIG. 1 and line BB ′ in FIG.

17 shows a manufacturing process of one embodiment of the present invention, and also shows a schematic cross-sectional view taken along line YY ′ in FIG. 1 and line BB ′ in FIG. 3.

18 shows a manufacturing process of one embodiment of the present invention, and also shows a schematic cross-sectional view taken along line YY ′ in FIG. 1 and line BB ′ in FIG.

19 shows a manufacturing process of one embodiment of the present invention, and also shows a schematic cross-sectional view taken along line YY ′ in FIG. 1 and line BB ′ in FIG. 3.

20 shows a manufacturing process of one embodiment of the present invention, and also shows a schematic cross-sectional view taken along line YY ′ in FIG. 1 and line BB ′ in FIG. 3.

21 shows a manufacturing process of one embodiment of the present invention, and also shows a schematic cross-sectional view taken along line YY ′ in FIG. 1 and line BB ′ in FIG.

FIG. 22 shows a manufacturing process of one embodiment of the present invention, and also shows a schematic cross-sectional view taken along line YY ′ in FIG. 1 and line BB ′ in FIG.

23 shows a manufacturing process of one embodiment of the present invention, and also shows a schematic cross-sectional view taken along line YY ′ in FIG. 1 and line BB ′ in FIG. 3.

FIG. 24 illustrates the effect of one embodiment of the present invention.
FIG. 4 is an equivalent circuit diagram of a TEG for easily measuring a variation in threshold voltage of a memory cell.

FIG. 25 is a measurement example of TEG in FIG. 24;

26 is a measurement example of the TEG in FIG. 24 when the TEG includes an over-erased cell and when the TEG does not include an over-erased cell.

FIG. 27 is a diagram showing the effect of one embodiment of the present invention;
FIG. 9 is a diagram showing a comparison of variation in threshold voltage after erasing;

FIG. 28 is a schematic plan view of a conventional flash memory.

29A and 29B are schematic cross-sectional views of a memory cell portion of a conventional flash memory, in which FIG. 29A is a schematic cross-sectional view taken along line XX ′ and FIG. 28B is a schematic cross-sectional view taken along line YY ′.

FIG. 30 is a schematic plan view of a transistor in a conventional peripheral circuit portion.

FIG. 31 is a schematic cross-sectional view of a transistor in a conventional peripheral circuit portion, where (a) is a line AA ′ of FIG.
(B) is a schematic sectional view taken along line BB '.

FIG. 28 is a view showing a manufacturing process of a conventional flash memory.
29 is a schematic cross-sectional view taken along the line YY ′ in FIG. 29 and the line BB ′ in FIG.

FIG. 33 is a view showing a conventional flash memory manufacturing process.
29 is a schematic cross-sectional view taken along the line YY ′ in FIG. 29 and the line BB ′ in FIG.

FIG. 34 is a view showing a process of manufacturing a conventional flash memory.
29 is a schematic cross-sectional view taken along the line YY ′ in FIG. 29 and the line BB ′ in FIG.

FIG. 35 is a view showing a process of manufacturing a conventional flash memory.
29 is a schematic cross-sectional view taken along the line YY ′ in FIG. 29 and the line BB ′ in FIG.

FIG. 36 is a view showing a process of manufacturing a conventional flash memory.
29 is a schematic cross-sectional view taken along the line YY ′ in FIG. 29 and the line BB ′ in FIG.

FIG. 37 is a diagram showing a conventional flash memory manufacturing process.
29 is a schematic cross-sectional view taken along the line YY ′ in FIG. 29 and the line BB ′ in FIG.

FIG. 38 shows a conventional flash memory manufacturing process.
29 is a schematic cross-sectional view taken along the line YY ′ in FIG. 29 and the line BB ′ in FIG.

FIG. 39 is a view showing a process of manufacturing a conventional flash memory.
29 is a schematic cross-sectional view taken along the line YY ′ in FIG. 29 and the line BB ′ in FIG.

FIG. 40 is a view showing a conventional flash memory manufacturing process.
29 is a schematic cross-sectional view taken along the line YY ′ in FIG. 29 and the line BB ′ in FIG.

FIG. 41 is a view showing a manufacturing process of a conventional flash memory.
29 is a schematic cross-sectional view taken along the line YY ′ in FIG. 29 and the line BB ′ in FIG.

FIG. 42 is a view showing a manufacturing process of a conventional flash memory.
29 is a schematic cross-sectional view taken along the line YY ′ in FIG. 29 and the line BB ′ in FIG.

FIG. 43 shows a conventional flash memory manufacturing process.
29 is a schematic cross-sectional view taken along the line YY ′ in FIG. 29 and the line BB ′ in FIG.

FIG. 44 is a view showing a conventional flash memory manufacturing process.
29 is a schematic cross-sectional view taken along the line YY ′ in FIG. 29 and the line BB ′ in FIG.

FIG. 45 shows a conventional flash memory manufacturing process.
29 is a schematic cross-sectional view taken along the line YY ′ in FIG. 29 and the line BB ′ in FIG.

[Explanation of symbols]

101, 201 P-type silicon substrate 102, 202 Field oxide film 103, 203 First oxide film 104 Nitride film 105, 205 Photoresist 106, 206 First gate oxide film 107, 207 First polycrystalline silicon film 108, 208 First Polycrystalline silicon film pattern 109, 209 Insulating film 110, 210 Second gate oxide film 111, 211 Second polycrystalline silicon film 112a, 112b, 112c, 112, 212a, 2
12b, 212c, 212 Control gate electrode 113, 213 Floating gate electrode 114, 214 Gate electrode 115, 215 Interlayer insulating layer 116a, 116b, 116, 216a, 216b, 2
16 bit line 117ab, 117cd, 217ab, 217cd First source region 118, 218 First drain region 119a, 119b, 219a, 219b Bit contact 120, 220 Second drain region 121, 221 Second source region

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (8)

(57) [Claims] A field oxide film is formed in a device isolation region on a surface of a P-type silicon substrate, and an oxide film is formed by thermal oxidation in a device formation region on a surface of the P-type silicon substrate.
After forming a nitride film on the entire surface and removing the nitride film only in the region where the memory cell is to be formed, and then performing thermal oxidation to increase the thickness of the oxide film in the peripheral circuit planned area, the nitride film is removed. Removing the upper oxide film, and removing the nitride film;
The entire surface of the oxide film is etched by the wet etching method to expose the surface of the P-type silicon substrate only in the memory cell formation planned area. Then, thermal oxidation is performed to form a gate oxide film in the memory cell formation planned area. An N-type polycrystalline silicon film having an impurity concentration is formed, the polycrystalline silicon film is patterned to form a predetermined polycrystalline silicon film pattern, and an insulating film is formed on the entire surface. After removing the film to expose the surface of the P-type silicon substrate and performing thermal oxidation to form a gate oxide film in the peripheral circuit planned region, a conductor film is formed on the entire surface, and the memory cell forming region is The conductor film, the insulating film, and the polysilicon film pattern are sequentially patterned to form a control gate electrode made of the conductor film and a floating film made of the polysilicon film pattern. Over gate electrode is formed, and further, in the peripheral circuit will amount range, the non-volatile semiconductor memory device characterized by comprising forming a gate electrode made of a conductive film by patterning the conductive film. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said control gate electrode is formed using a polycrystalline silicon film as said conductor film. 3. The nonvolatile semiconductor memory device according to claim 1, wherein said control gate electrode is formed using a polycide film as said conductor film. 4. The nonvolatile semiconductor memory device according to claim 1, wherein said control gate electrode is formed using a silicide film as said conductor film. 5. A step of forming a field oxide film in an element isolation region on a surface of a P-type silicon substrate, a step of forming an oxide film by thermal oxidation in an element formation region of a surface of the P-type silicon substrate, and Forming a nitride film, removing the nitride film only in a region where a memory cell is to be formed, removing the nitride film, performing a thermal oxidation process to increase the thickness of an oxide film in a peripheral circuit planned region, and forming the nitride film. Removing the upper oxide film, removing the nitride film, etching the entire oxide film by wet etching to expose the P-type silicon substrate surface only in the memory cell formation planned region, and performing thermal oxidation. A step of forming a gate oxide film in the memory cell formation planned area, a step of forming an N-type polycrystalline silicon film having a required impurity concentration on the entire surface, and a step of patterning the polycrystalline silicon film to a predetermined level. A step of forming a polycrystalline silicon film pattern, a step of forming an insulating film over the entire surface, a step of removing an insulating film in a peripheral circuit scheduled area and exposing a P-type silicon substrate surface, and a step of performing peripheral oxidation by performing thermal oxidation. Forming a gate oxide film in the region, forming a conductor film over the entire surface, and sequentially patterning the conductor film, the insulating film, and the polycrystalline silicon film pattern in the memory cell formation region. Forming a control gate electrode made of a conductive film and a floating gate electrode made of the polycrystalline silicon film pattern, and, in a peripheral circuit scheduled area, patterning the conductive film to form a gate electrode made of the conductive film. A method for manufacturing a nonvolatile semiconductor memory device, comprising a step of forming. 6. The method according to claim 1, wherein said control gate electrode is formed using a polycrystalline silicon film as said conductor film. 7. The method according to claim 1, wherein the control gate electrode is formed using a polycide film as the conductor film. 8. The method according to claim 1, wherein the control gate electrode is formed using a silicide film as the conductor film.