JP3160967B2 - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JP3160967B2 JP3160967B2 JP30389791A JP30389791A JP3160967B2 JP 3160967 B2 JP3160967 B2 JP 3160967B2 JP 30389791 A JP30389791 A JP 30389791A JP 30389791 A JP30389791 A JP 30389791A JP 3160967 B2 JP3160967 B2 JP 3160967B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor integrated
- integrated circuit
- pad
- input terminal
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体集積回路に係り、
特に入力端子に前段の終端抵抗を有するＥＣＬ（Ｅｍｉ
ｔｔｅｒ Ｃｏｕｐｌｅｄ Ｌｏｇｉｃ）論理回路を実
現するための半導体集積回路に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, ECL (Emi
The present invention relates to a semiconductor integrated circuit for implementing a ter-coupled logic (logic) circuit.
【０００２】[0002]
【従来の技術】従来の半導体集積回路の一例を図２に示
し説明する。この図２において、２１，２２は半導体集
積回路、２３は入力パッド、２４はＶＴＴパッド、２５
はエミッタホロワ出力である出力パッド、２６，２７は
トランジスタ、２８は終端抵抗、２９は終端電源ＶＴＴ
である。そして、ＥＣＬ論理回路のエミッタホロワ出力
である出力パッド２５は通常５０Ω程度の終端抵抗２８
で終端電源ＶＴＴ２９（通常−２．１Ｖ）に接続し終端
する。2. Description of the Related Art An example of a conventional semiconductor integrated circuit will be described with reference to FIG. In FIG. 2, 21 and 22 are semiconductor integrated circuits, 23 is an input pad, 24 is a VTT pad, and 25
Is an output pad which is an emitter follower output, 26 and 27 are transistors, 28 is a terminating resistor, 29 is a terminating power supply VTT
It is. The output pad 25, which is the emitter follower output of the ECL logic circuit, usually has a terminating resistor 28 of about 50Ω.
At the terminal power supply VTT29 (normally -2.1V) to terminate.
【０００３】ここで、このエミッタホロワ出力の出力パ
ッド２５と次段の入力パッド２３が離れている場合に
は、次段の入力パッド２３に極力近い位置に終端抵抗２
８を配置する必要があり、そういう意味で次段の半導体
集積回路内に終端抵抗２８を内蔵するのが理想的であ
る。すなわち、ＥＣＬ論理回路のエミッタホロワ出力の
終端抵抗は次段の入力端子に極力近い方が望ましく、次
段の半導体集積回路内に終端抵抗を設け、半導体集積回
路内で入力端子とＶＴＴ（終端抵抗）に接続してしまう
のが理想的である。When the output pad 25 of the emitter follower output is separated from the input pad 23 of the next stage, the terminating resistor 2 is located as close as possible to the input pad 23 of the next stage.
In this sense, it is ideal to incorporate the terminating resistor 28 in the next-stage semiconductor integrated circuit. That is, it is desirable that the terminating resistance of the emitter follower output of the ECL logic circuit be as close as possible to the input terminal of the next stage. A terminating resistor is provided in the semiconductor integrated circuit of the next stage. It is ideal to connect to
【０００４】さらに、終端電源ＶＴＴ２９に対する接続
も半導体集積回路内で行った方が良いが、こうすると、
前段の出力を複数に分岐（すなわち、ファンアウトを複
数にする）したときには、終端抵抗が複数並列になりイ
ンピーダンスマッチングがとれなくなるという不都合が
ある。したがって、終端電源ＶＴＴ２９を外部に出し、
終端するかしないかを選択する必要がある。Further, it is better to connect the terminal power supply VTT29 in the semiconductor integrated circuit.
When the output of the preceding stage is branched into a plurality of pieces (that is, a plurality of fan-outs), a plurality of terminating resistors are connected in parallel, and impedance matching cannot be performed. Therefore, the terminal power supply VTT29 is output to the outside,
You need to choose whether to terminate or not.
【０００５】[0005]
【発明が解決しようとする課題】この従来の半導体集積
回路では、入力に終端抵抗を接続する場合には、いちい
ち終端電源ＶＴＴに接続しなければならないので、終端
電源ＶＴＴのプリント板パターンの引き回しが複雑にな
るという課題があり、また、バイパスコンデンサも終端
の個数だけ必要になり、各々の入力端子に最適な位置に
接続することが困難になるという課題があり、したがっ
て、交流特性が劣化してしまうという課題があった。In this conventional semiconductor integrated circuit, when a terminating resistor is connected to the input, it must be connected to the terminating power supply VTT, so that the printed circuit board pattern of the terminating power supply VTT must be routed. There is a problem that it becomes complicated, and a bypass capacitor is required by the number of terminations, so that it is difficult to connect each input terminal to an optimum position. There was a problem of getting it.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体集積回路
は、ＥＣＬ論理回路の入力端子において、この入力端子
に接続されたコンデンサ，このコンデンサに直列に接続
された抵抗，この抵抗に直列に接続された終端制御端子
からなる直列回路と、ＥＣＬ論理回路の入力端子に一端
が接続され他端がＶＥＥに接続された定電流源とを備
え、終端制御端子は接地への接続とオープンとが切り替
え可能に構成したものである。According to the semiconductor integrated circuit of the present invention, at the input terminal of the ECL logic circuit, a capacitor connected to the input terminal and a capacitor connected in series to the input terminal.
Resistor, termination control terminal connected in series with this resistor
And one end to the input terminal of the ECL logic circuit
Bei a constant current source but the other end is connected is connected to VEE
The termination control terminal switches between connection to ground and open
It is configured to be possible .
【０００７】[0007]
【作用】本発明においては、半導体集積回路内で終端電
源ＶＴＴに終端しかつ終端するかしないかを選択するこ
とを可能とする。According to the present invention, it is possible to terminate the power to the termination power supply VTT in the semiconductor integrated circuit and to select whether or not to terminate.
【０００８】[0008]
【実施例】図１は本発明による半導体集積回路の一実施
例を示す回路図である。この図１において、１は入力パ
ッド、２はＶＥＥ（−５．２Ｖ）パッド、３はＶＣＣ
（ＧＮＤ）パッド、４は終端制御端子となるパッド、
５，６はトランジスタ、７〜１０は抵抗、１１はコンデ
ンサ、１２は定電流源で、この定電流源１２はトランジ
スタ５と抵抗８〜１０により構成されている。そして、
ＥＣＬ論理回路の入力端子に一端が接続され、他端にパ
ッドを有する抵抗７およびコンデンサ１１の直列回路
と、一端がＥＣＬ論理回路の入力端子に接続され、他端
がＶＥＥ（−５．２Ｖ）パッド２に接続された定電流源
１２を備えている。FIG. 1 is a circuit diagram showing one embodiment of a semiconductor integrated circuit according to the present invention. In FIG. 1, 1 is an input pad, 2 is a VEE (-5.2 V) pad, and 3 is VCC.
(GND) pad, 4 becomes termination control terminal pads,
Reference numerals 5 and 6 denote transistors, reference numerals 7 to 10 denote resistors, reference numeral 11 denotes a capacitor, and reference numeral 12 denotes a constant current source. The constant current source 12 includes a transistor 5 and resistors 8 to 10. And
One end is connected to the input terminal of the ECL logic circuit, and a series circuit of a resistor 7 and a capacitor 11 having a pad at the other end, and one end is connected to the input terminal of the ECL logic circuit, and the other end is VEE (−5.2 V). A constant current source 12 connected to the pad 2 is provided.
【０００９】つぎにこの図１に示す実施例の動作を説明
する。トランジスタ５と抵抗８〜１０により構成される
回路が定電流源であり、前段のエミッタホロワの直流電
流を供給している。また、抵抗７，コンデンサ１１によ
り構成される部分が終端インピーダンスを与え、終端す
る場合にはパッド４をＧＮＤにし、終端しない場合には
このパッド４をオープンとする。すなわち、このパッド
４が終端制御端子となる。そして、抵抗７およびコンデ
ンサ１１の直列回路による終端は交流的な終端であるの
で、パッド４をＧＮＤに接続することが可能となる。Next, the operation of the embodiment shown in FIG. 1 will be described. A circuit composed of the transistor 5 and the resistors 8 to 10 is a constant current source, and supplies a DC current of the emitter follower in the preceding stage. Further, a portion constituted by the resistor 7 and the capacitor 11 gives a terminating impedance. When terminating, the pad 4 is set to GND, and when not terminating, the pad 4 is opened. That is, the pad 4 serves as a termination control terminal. Since the termination of the series circuit of the resistor 7 and the capacitor 11 is an AC termination, the pad 4 can be connected to GND.
【００１０】[0010]
【発明の効果】以上説明したように本発明は、半導体集
積回路内で終端電源ＶＴＴに終端しかつ終端するかしな
いかを選択することができるようにしたので、終端イン
ピーダンスを直接ＧＮＤに接続することができ、プリン
ト板のパターンも複雑にならず、また、バイパスコンデ
ンサも不要である。したがって、交流特性も優れた半導
体集積回路を実現することができる効果がある。As described above, according to the present invention, it is possible to select whether or not to terminate to the terminating power supply VTT in the semiconductor integrated circuit, so that the terminating impedance is directly connected to GND. The pattern of the printed circuit board is not complicated, and no bypass capacitor is required. Therefore, there is an effect that a semiconductor integrated circuit having excellent AC characteristics can be realized.
【図１】本発明による半導体集積回路の一実施例を示す
回路図である。FIG. 1 is a circuit diagram showing one embodiment of a semiconductor integrated circuit according to the present invention.
【図２】従来の半導体集積回路の一例を示す回路図であ
る。FIG. 2 is a circuit diagram showing an example of a conventional semiconductor integrated circuit.
１ 入力パッド ２ ＶＥＥパッド ３ ＶＣＣパッド ４ パッド ５〜６ トランジスタ ７〜１０ 抵抗 １１ コンデンサ １２ 定電流源 DESCRIPTION OF SYMBOLS 1 Input pad 2 VEE pad 3 VCC pad 4 Pad 5-6 Transistor 7-10 Resistance 11 Capacitor 12 Constant current source
Claims (1)
の入力端子に接続されたコンデンサ，このコンデンサに
直列に接続された抵抗，この抵抗に直列に接続された終
端制御端子からなる直列回路と、前記ＥＣＬ論理回路の
入力端子に一端が接続され他端がＶＥＥに接続された定
電流源とを備え、前記終端制御端子は接地への接続とオ
ープンとが切り替え可能に構成されたことを特徴とする
半導体集積回路。1. An input terminal of an ECL logic circuit, a capacitor connected to the input terminal, and a capacitor connected to the input terminal.
A resistor connected in series, a terminal connected in series with this resistor
A series circuit comprising an end control terminal and an ECL logic circuit.
A constant current source having one end connected to the input terminal and the other end connected to VEE , wherein the termination control terminal is connected to ground and
A semiconductor integrated circuit characterized in that it can be switched between open and closed .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30389791A JP3160967B2 (en) | 1991-10-24 | 1991-10-24 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30389791A JP3160967B2 (en) | 1991-10-24 | 1991-10-24 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05121640A JPH05121640A (en) | 1993-05-18 |
| JP3160967B2 true JP3160967B2 (en) | 2001-04-25 |
Family
ID=17926583
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30389791A Expired - Fee Related JP3160967B2 (en) | 1991-10-24 | 1991-10-24 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3160967B2 (en) |
-
1991
- 1991-10-24 JP JP30389791A patent/JP3160967B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05121640A (en) | 1993-05-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |