JP3161366B2 - Variable sullate buffer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device, and more particularly to an output buffer for interfacing a signal to a transmission line in a CMOS circuit.

[0002]

2. Description of the Related Art FIG. 5 shows an example of the configuration of a conventional CMOS output buffer. Referring to FIG. 5, a P-channel MOS transistor (referred to as “P-channel transistor”) 4 and an N-channel MOS transistor (referred to as “N-channel transistor”) 5 corresponding to an output buffer, and an inverter 10 for driving these transistors are provided. In the case of this circuit configuration, the driving capability required for the output buffer and
Along with the recent increase in switching speed, a great deal of noise is generated in the output waveform during switching.

As a configuration for preventing this noise, for example, a noise reduction circuit as shown in FIG. 6 is used.
FIG. 6 is a diagram showing a configuration of a semiconductor integrated circuit proposed in, for example, Japanese Patent Application Laid-Open No. 5-191241, in which an output buffer and a slew rate setting means for making a slew rate of an input signal of the output buffer variable, It has a control terminal to which a control signal for the means is inputted.

Referring to FIG. 6, a gate of each of a P-channel transistor 4 and an N-channel transistor 5 corresponding to an output buffer is provided with an inverter 1 for driving them.
1 and 12 are provided. An N-channel transistor whose gate is connected to the control terminal EN is connected between the source of the N-channel transistor constituting the inverter 11 and the ground, an N-channel transistor whose gate input is the inverter output of the control terminal EN, and N whose gate is the power supply potential. The channel transistor is connected in parallel. A P-channel transistor whose gate is connected to the control terminal EN, a P-channel transistor whose gate terminal is ground potential, and an inverter output of the control terminal EN as a gate input are provided between the source of the P-channel transistor constituting the inverter 12 and the power supply. P-channel transistors are connected in parallel.

[0005] Regarding the inverter 11, the node n1 is at H level.
When changing from the level to the L level, the time constant at this time is reduced, and the slew rate of the waveform of the node n1 is increased.
Further, the value of the EN terminal changes the time constant of the node n1, thereby changing the value of the slew rate.

When the node n1 changes from the L level to the H level, the time constant is increased at this time, and the slew rate of the waveform of the node n1 is reduced.

On the other hand, regarding the inverter 12, the node n
The time constant at the time when 2 changes from the L level to the H level is reduced, and the slew rate of the waveform of the node n2 is increased. Further, the value of the slew rate is changed by making the time constant of the node n2 variable according to the value of the EN terminal.

When the node n2 changes from the H level to the L level, the time constant is increased at this time, and the slew rate of the waveform of the node n2 is reduced.

With the above configuration, the output buffer P
By dulling the gate waveform of the channel transistor 4 from the H level to the L level and the gate waveform of the N channel transistor 5 from the L level to the H level, the output terminal O
A slew rate is provided in the output waveform of the UT.

The output noise is suppressed by varying the value of the slew rate using the EN terminal.

Then, the P-channel transistor 4 and the N-channel transistor 5 serving as output buffers are turned on.
By providing a time difference between (ON) and OFF (OFF), a through current at the time of a signal change can be suppressed.

[0012]

In recent years, with the advance of device technology, the switching speed has been increased.
In such a situation, it is becoming difficult to make a relatively large sullate. Further, when a very wide slew rate such as several ns to several tens ns is required, it is impossible with a conventional circuit configuration.

Accordingly, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide an output buffer for interfacing a signal to a transmission line in a CMOS circuit, which has a variable slew rate and has a large slew rate. An object of the present invention is to provide an output buffer circuit that can handle the output buffer circuit.

[0014]

Means for Solving the Problems In order to achieve the above object, the present invention applies a slew rate to an output waveform by using a mirror circuit, and turns on and off the circuit, thereby providing a considerably wide slew rate to the output waveform. It is intended to be applied. More specifically, the present invention provides a mirror circuit at an output terminal and a gate terminal, and in an output buffer forming a slew rate by the mirror capacitance, turning on and off the mirror circuit by a control circuit to obtain a slew rate value. And a CMO comprising a P-channel MOS transistor and an N-channel MOS transistor connected in series between a high potential power supply and a low potential power supply and having a drain commonly connected to an output terminal.
An S-type output buffer, the output terminal and the P-channel M
A first mirror capacitor and a first transfer circuit connected in series between the gate terminal of the OS transistor and a gate terminal of the N-channel MOS transistor; a second Miller capacitance and a second transfer circuit, the first and second
Control the on / off of the transfer circuit
A control circuit for supplying a control signal to
A power buffer circuit, wherein said control circuit is
The input signal (IN) to the output buffer circuit is input,
A variable delay circuit that variably delays and outputs this,
The signal level of the input signal (IN) changes from H level to L level.
When the level changes from L level to H level,
First transfer circuit or second transfer circuit
Turns ON for the delay time of the variable delay circuit.

[0015]

Embodiments of the present invention will be described below. According to the preferred embodiment of the present invention, a mirror circuit is provided between the drain and the gate of the P-channel transistor and the N-channel transistor constituting the output buffer, and a considerably large slew rate can be applied to the output waveform by the mirror circuit.

Then, the mirror circuit is turned on and off by the control circuit, that is, a mirror capacitor and a transfer circuit are connected in series between the drain and the gate of the output buffer, and the transfer circuit is turned on and off. A sullate buffer can be configured.

[0017]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

FIG. 1 is a diagram showing the configuration of one embodiment of the present invention. Referring to FIG. 1, in the present embodiment, a P-channel transistor 4 and an N-channel transistor 5 corresponding to an output buffer are
It is configured to be driven by the channel transistor 8.
A mirror circuit 1 is formed between the drain and the gate of the P-channel transistor and the N-channel transistor constituting the output buffer. ON / OFF this mirror circuit 1
For this purpose, transfer circuits 6 and 6 'and the control circuit 2 are provided, and outputs A1 and A2 of the control circuit 2 are provided.
Turns the mirror circuit ON and OFF. That is,
The mirror circuit 1 is connected in parallel so that one end of two capacitors is P
The drain of the channel transistor 4 and the drain of the N-channel transistor 5 are commonly connected, and the other end is connected to the gate of the transistor via transfer circuits 6 and 6 '.

When the EN terminal is at the H level, the node A1 of the control circuit 2 is at the L level and the node A2 is at the H level, so that the transfer circuits 6, 6 'are turned ON. That is, the mirror circuit between the drain and gate of the output buffer is ON.
Is in a state where feedback is applied.

At this time, when the terminal IN changes from H level to L level, the nodes n1 and n2 in the figure change from L level to H level, and the OUT terminal changes from H level to L level. Since the mirror circuit 1 is ON, a mirror capacitance enters between a state where the node n2 is about to go to the H level and a state where the OUT terminal is about to go to the L level, and feedback is generated between the drain and the gate of the output buffer. Take it.
Therefore, a large slew rate is applied from the H level to the L level of the output waveform.

When the terminal IN changes from L level to H level, the nodes n1 and n2 change from H level to L level,
The OUT terminal changes from L level to H level. Since the mirror circuit is ON, the mirror capacitance enters between the state where the node n1 is about to go low and the state where the OUT terminal is about to go high, and feedback is applied between the drain and gate of the output buffer. For this reason, a large slew rate is applied from the L level to the H level of the output waveform.

When the EN terminal is at the L level, the node A1 is at the H level.
Since the level and the node A2 are at the L level, the transfer circuit 6 is turned off. The drain of the output buffer,
Since the mirror circuit between the gates is in an OFF state and no feedback is applied, a small slew rate is applied from the L level to the H level or from the H level to the L level of the output waveform.

As described above, by controlling the mirror circuit by the control circuit, a large slew rate and a small slew rate can be applied to the output waveform.

FIG. 2 is a diagram showing the configuration of the second embodiment of the present invention. Referring to FIG. 2, a P-channel transistor 4 and an N-channel transistor 5 corresponding to output buffers are driven by a P-channel transistor 7 and an N-channel transistor 8. A mirror circuit 1 is formed between the drain and the gate of the output buffer. Transfer circuits 6 and 9 and a control circuit 2 are provided to turn the mirror circuit 1 on and off.

The control circuit 2 includes a variable delay circuit 3, and controls the ON time of the transfer circuits 6 and 9 and the time for applying feedback based on the delay value.

The operation of the second embodiment of the present invention will be described.

When the EN terminal is at H level, nodes A1 and A
2, B1 and B2 are determined by the state of the IN terminal, and the transfer circuit 6 or 9 is turned on and off.

At this time, when the terminal IN changes from H level to L level, the nodes n1 and n2 change from L level to H level, and the OUT terminal changes from H level to L level. At this time, the transfer circuit 9 is turned on for the delay time of the variable delay circuit 3 and then turned off.

As described above, when the mirror circuit is ON, the state where the node n2 is about to go to the H level,
The mirror capacitance enters while the UT terminal is about to go low, and feedback is applied between the drain and gate of the output buffer. At this time, a variable slew rate is applied by changing the delay time of the delay circuit 3.

When the IN terminal changes from the L level to the H level, the nodes n1 and n2 change from the H level to the L level,
The OUT terminal changes from L level to H level. At this time, the transfer circuit 6 is turned on for the delay time of the variable delay circuit 3 and then turned off.

As described above, when the mirror circuit is ON, the mirror capacitance enters between the state where the node n1 is about to go low and the state where the OUT terminal is about to go high, and the drain of the output buffer is drained. There is feedback between the gates. At this time, a variable slew rate is applied by changing the delay time of the delay circuit 3.

When the EN terminal is at L level, the node A1 is at L level.
Since the level, the node A2 is at the L level, the node B1 is at the H level, and the node B2 is at the L level, the transfer circuits 6, 9 are turned off. The drain of the output buffer,
Since the mirror circuit between the gates is in an OFF state and no feedback is applied, a small slew rate is applied from the L level to the H level or from the H level to the L level of the output waveform.

As described above, by controlling the ON / OFF of the mirror circuit by the control circuit and controlling the ON time of the mirror circuit by the delay circuit in the control circuit, a large slew rate, an intermediate slew rate and a small slew rate are output. Can be applied to the waveform.

This operation is performed by using a circuit simulator SP
A simulation was performed using ICE and verified.

FIG. 3 shows an SPIC according to a first embodiment of the present invention.
It is a figure showing the simulation result (transient analysis result) by E. Input waveform to IN terminal and OUT
Observe the waveform at the terminal. The waveforms are shown when the EN terminal is controlled and the mirror circuit is OFF, ie, no feedback is applied, and when the mirror circuit is ON, ie, feedback is applied. Waveform A is an input waveform, waveforms B and C are output waveforms, waveform B is a state where the mirror circuit is OFF, and waveform C is a state where the mirror circuit is ON. It can be seen that the waveform C has a larger slew rate than the waveform B.

FIG. 4 is a diagram showing simulation results (transient analysis results) of the second embodiment of the present invention. The waveform is input to the IN terminal and the waveform at the OUT terminal is observed. The mirror circuit is turned off by controlling the EN terminal.
N, that is, a waveform obtained by changing the delay value in a state where feedback is applied. Waveform A is the input waveform, waveforms B, C, D
Is an output waveform, waveform B is a mirror circuit OFF state, waveform C is a mirror circuit ON state, a small delay value, and waveform D is a mirror circuit ON state, a large delay value waveform.
It can be seen that large slew rates are applied in the order of the waveforms B, C, and D.

[0037]

As described above, according to the present invention,
This has the effect that the sllate waveform can be output variably over a fairly wide range. The reason is that a mirror circuit is provided between the output terminal and the gate terminal, and in the output buffer that forms a slew rate by the mirror capacitance, the mirror circuit is turned on / off by the control circuit to make the slew rate value variable. is there.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a first embodiment of the present invention.

FIG. 2 is a diagram showing a circuit configuration of a second embodiment of the present invention.

FIG. 3 is a diagram showing a simulation result by SPICE of the first embodiment of the present invention.

FIG. 4 is a diagram showing a simulation result by SPICE of the second embodiment of the present invention.

FIG. 5 is a diagram showing a conventional output buffer.

FIG. 6 is a diagram showing a conventional noise reduction type output buffer.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 mirror circuit 2 control circuit 3 variable delay circuit 4 P-channel output transistor 5 N-channel output transistor 6 transfer circuit 7 output transistor drive P-channel transistor 8 output transistor drive N-channel transistor 9 transfer circuit 10 output transistor drive inverter 11 P-channel output transistor Drive inverter 12 N-channel output transistor drive inverter

Claims (3)

(57) [Claims] 1. A series configuration between a high potential power supply and a low potential power supply
Connected to the output terminal and a drain connected in common.
Channel MOS transistor and N-channel MOS transistor
A CMOS output buffer composed of a transistor;
A first mirror capacitor connected in series with the first terminal
An output terminal and a gate of the N-channel MOS transistor;
A second mirror capacitor connected in series with the
An amount and a second transfer circuit;The first and second transfer circuits are turned on.
.Control circuit that supplies a control signal for controlling off
An output buffer circuit comprising:
Circuit outputs an input signal (IN) to the output buffer circuit.
Variable delay that variably delays and outputs
Circuit, The signal level of the input signal (IN) changes from H level to L level.
When the level changes from L level to H level,
First transfer circuit or second transfer circuit
Turns on for the delay time of the variable delay circuit,  An output buffer circuit characterized in that: 2. A series connection between a high potential power supply and a low potential power supply.
Connected to the output terminal and the drain is connected in common.
Channel MOS transistor and N-channel MOS transistor
A CMOS output buffer composed of a transistor, and a gate of the output terminal and the P-channel MOS transistor.
A first mirror capacitor connected in series between the
And a first transfer circuit, and a gate of the output terminal and the N-channel MOS transistor.
A second mirror capacitor connected in series between the
Quantity and a second transfer circuit, and the first and second transfer circuits are turned on.
.Control circuit that supplies a control signal for controlling off
An output buffer circuit comprising:
Circuit outputs an input signal (IN) to the output buffer circuit.
Variable delay that variably delays and outputs
Input signal having a circuit and delayed by the variable delay circuit
From the input control signal (EN) and the first and
Turn on / off the second transfer circuit individually
First and second control signals to be (A1, A2; B1, B
2) and outputting the first and / or second transfer
By controlling the on-time of the circuit,
Output buffer, wherein the value of the packet is variable.
circuit. 3. The control signal (EN) is at an H level.
In this case, the input signal (IN) is changed from H level to L level.
Output from the control circuit when
By the second control signal (B1, B2), the second traffic signal is output.
Transfer circuit is turned on for the delay time of the variable delay circuit.
And then turn off to check if the input signal (IN) is at L level.
Output from the control circuit when
The first control signal (A1, A2)
The transfer circuit of No. 1 is the delay time of the variable delay circuit.
And then turns off. If the control signal (EN) is at L level,
The first and second control signals output from the troll circuit
As a result, the first and second transfer circuits are turned off.
3. The output buffer circuit according to claim 2, wherein