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JP3164084B2 - Semiconductor device frame - Google Patents
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JP3164084B2 - Semiconductor device frame - Google Patents

Semiconductor device frame

Info

Publication number
JP3164084B2
JP3164084B2 JP29834298A JP29834298A JP3164084B2 JP 3164084 B2 JP3164084 B2 JP 3164084B2 JP 29834298 A JP29834298 A JP 29834298A JP 29834298 A JP29834298 A JP 29834298A JP 3164084 B2 JP3164084 B2 JP 3164084B2
Authority
JP
Japan
Prior art keywords
copper wiring
wiring pattern
frame
semiconductor element
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP29834298A
Other languages
Japanese (ja)
Other versions
JP2000124351A (en
Inventor
洋 伊勢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP29834298A priority Critical patent/JP3164084B2/en
Publication of JP2000124351A publication Critical patent/JP2000124351A/en
Application granted granted Critical
Publication of JP3164084B2 publication Critical patent/JP3164084B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子を搭載
するための半導体装置のフレームに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame of a semiconductor device for mounting a semiconductor element.

【0002】[0002]

【従来の技術】半導体装置には、ガラスエポキシ樹脂製
の基板をフレームとして用い、基板上の中央部に半導体
素子設置用のアイランドを設け、その周辺に銅配線パタ
ーンを形成し、アイランドに設置された半導体素子の電
極と銅配線パターンとを半田付けし、半導体素子を樹脂
封止した構造のものがある。
2. Description of the Related Art In a semiconductor device, a substrate made of glass epoxy resin is used as a frame, an island for mounting a semiconductor element is provided in a central portion on the substrate, a copper wiring pattern is formed around the island, and the substrate is mounted on the island. There is a structure in which an electrode of a semiconductor element is soldered to a copper wiring pattern and the semiconductor element is sealed with a resin.

【0003】この種の半導体装置では、樹脂封止領域内
での半導体素子の電極と銅配線パターンとを半田付けす
る際に、その熱の影響を受けて基板に反りが生じて銅配
線の切れが発生することがある。
In this type of semiconductor device, when soldering an electrode of a semiconductor element and a copper wiring pattern in a resin-encapsulated region, the substrate is warped due to the heat and cut off the copper wiring. May occur.

【0004】そこで、従来では、熱影響による銅配線切
れを防止する手段が講じられている(特開平2−206
193号公報,特開平8−264647号公報,特開平
9−260579号公報参照)。
Therefore, conventionally, means for preventing disconnection of the copper wiring due to the influence of heat have been taken (Japanese Patent Laid-Open No. 2-206).
193, JP-A-8-264647 and JP-A-9-260579).

【0005】[0005]

【発明が解決しようとする課題】しかしながら、従来例
では、樹脂封止される領域での銅配線切れを防止するこ
とは可能であるが、銅配線の一部には、樹脂封止領域か
ら露出するものがある。この場合、その露出した銅配線
の部分が樹脂封止の際に生じる熱の影響を受けることと
なり、露出した銅配線に切れが生じてしまうという問題
がある。
However, in the conventional example, it is possible to prevent the copper wiring from being cut in the resin-sealed area, but a portion of the copper wiring is exposed from the resin-sealed area. There is something to do. In this case, the exposed portion of the copper wiring is affected by the heat generated at the time of resin sealing, and there is a problem that the exposed copper wiring is cut.

【0006】本発明の目的は、樹脂封止領域外に露出し
た銅配線が樹脂封止の熱影響によって断線するのを防止
した半導体装置のフレームを提供することにある。
An object of the present invention is to provide a frame of a semiconductor device in which a copper wiring exposed outside a resin sealing region is prevented from being disconnected due to a thermal effect of resin sealing.

【0007】[0007]

【課題を解決するための手段】前記目的を達成するた
め、本発明に係る半導体装置のフレームは、中央部に半
導体素子搭載用のアイランドを有し、その周辺に銅配線
パターンとダミー配線とを有し、前記アイランドに搭載
された半導体素子の電極と前記銅配線パターンとを電気
的に接続し、前記半導体素子を樹脂封止する半導体装置
のフレームであって前記銅配線パターンは前記樹脂封
止領域の内外に配置されており、前記ダミー配線は、前
記銅配線パターンの形成領域に、前記樹脂封止領域の内
外に渡って前記隣接する銅配線パターンの粗の部分に設
けられ、熱によるフレームの反りを抑えるものである
In order to achieve the above object, a semiconductor device frame according to the present invention is provided with a frame at a central portion.
Has an island for mounting conductive elements, and copper wiring around it
Has pattern and dummy wiring, mounted on the island
Electrical connection between the electrode of the semiconductor element and the copper wiring pattern.
Semiconductor device for electrically connecting and resin sealing the semiconductor element
A frame, the copper wiring pattern of the resin sealing
And the dummy wirings are arranged inside and outside the stop region.
In the area where the copper wiring pattern is formed,
Extend over the rough portion of the adjacent copper wiring pattern.
To suppress the warpage of the frame due to heat .

【0008】[0008]

【発明の実施の形態】以下、本発明の実施の形態を図に
より説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

【0009】図1は、本発明の一実施形態を示す平面図
である。図1に示す本発明に実施形態に係る半導体装置
は、ガラスエポキシ樹脂製の基板をフレーム1として用
い、フレーム1上の中央部に半導体素子設置用のアイラ
ンド1aを設け、その周辺に銅配線パターン2を形成
し、アイランド1aに設置された半導体素子(図示略)
の電極と銅配線パターン2とを半田付けし、半導体素子
を樹脂封止する構造のものである。
FIG. 1 is a plan view showing an embodiment of the present invention. A semiconductor device according to an embodiment of the present invention shown in FIG. 1 uses a substrate made of glass epoxy resin as a frame 1, an island 1 a for mounting a semiconductor element is provided in a central portion on the frame 1, and a copper wiring pattern is provided around the island 1 a. 2 and a semiconductor element (not shown) installed on the island 1a
And the copper wiring pattern 2 are soldered, and the semiconductor element is sealed with resin.

【0010】銅配線パターン2は、アイランド1a側の
端部に半導体素子の電極と半田付けするためのパッド2
aが設けられており、銅配線パターン2の反対側の端部
2bは、樹脂封止領域4を越えて外部に露出しており、
外部回路等に半田付けされるようになっている。
A copper wiring pattern 2 has a pad 2 for soldering to an electrode of a semiconductor element at an end on the island 1a side.
a is provided, and the end 2 b on the opposite side of the copper wiring pattern 2 is exposed outside beyond the resin sealing region 4.
It is designed to be soldered to an external circuit or the like.

【0011】ここで、樹脂封止領域4内の銅配線パター
ン2が形成されたフレーム1の内装部1bは、半導体素
子の電極と半田付けする際の熱により反りが生じ、樹脂
封止領域4外に露出した銅配線パターン2が形成された
フレーム1の外装部1cは、半導体素子を樹脂封止する
際、及び露出した銅配線パターン(端部2b)2を外部
回路等に半田付けする際などの場合に受ける熱で反りが
生じて、銅配線パターン2が断線する可能性がある。
Here, the interior portion 1b of the frame 1 in which the copper wiring pattern 2 is formed in the resin sealing region 4 is warped by the heat at the time of soldering to the electrodes of the semiconductor element, and the resin sealing region 4 is warped. The exterior portion 1c of the frame 1 on which the copper wiring pattern 2 exposed to the outside is formed, when the semiconductor element is sealed with a resin, and when the exposed copper wiring pattern (end portion 2b) 2 is soldered to an external circuit or the like. In such a case, there is a possibility that the copper wiring pattern 2 is disconnected due to warpage caused by the heat received.

【0012】フレーム1のうち、熱により反りを生じる
箇所について技術的な解析を行った結果、フレーム1に
設けられる銅配線パターン2が粗の部分に集中して発生
していることが分かった。さらに、樹脂封止領域4より
露出した部分でも、同様なことが言える。
As a result of a technical analysis of a portion of the frame 1 where warping occurs due to heat, it was found that the copper wiring pattern 2 provided on the frame 1 was concentrated on a rough portion. Further, the same can be said for a portion exposed from the resin sealing region 4.

【0013】そこで、本発明の実施形態では、フレーム
1の辺にほぼ直角に設けた銅配線パターン2のうち、隣
接する銅配線パターン2の間が広がって粗となる部分1
dにダミー配線3を銅配線パターン2とほぼ平行に設け
ている。なお、フレーム1には、銅配線パターン2を内
外に配置して設ける箇所があるが、この部分は内外の銅
配線パターン2が隣接して密に設けられるため、密の部
分1eではフレーム1に反りを生じることがなく、ダミ
ー配線3を設ける必要はない。以上のように、ダミー配
線3は、隣接する銅配線パターン2の粗密をなくするた
め、本来配線が不要な場所に設けるものである。
Therefore, in the embodiment of the present invention, of the copper wiring patterns 2 provided substantially at right angles to the sides of the frame 1, the portion 1 where the space between the adjacent copper wiring patterns 2 is widened and roughened is provided.
The dummy wiring 3 is provided substantially parallel to the copper wiring pattern 2 at d. In the frame 1, there is a portion where the copper wiring patterns 2 are arranged inside and outside. However, since this portion is densely provided adjacent to the copper wiring patterns 2 inside and outside, the dense portion 1e has There is no warpage, and there is no need to provide the dummy wiring 3. As described above, the dummy wirings 3 are provided in places where wirings are not originally required in order to eliminate the density of the adjacent copper wiring patterns 2.

【0014】さらに、フレーム1のうち、横方向の銅配
線パターン2と縦方向の銅配線パターン2との交差する
角部1fでは、ダミー配線3は相手方(横方向或いは縦
方向)の銅配線パターン2とほぼ直交する方向に配置し
て設け、フレーム1の角部1fに生じる反りを抑えるよ
うにしている。
Further, in the corner 1f of the frame 1 where the horizontal copper wiring pattern 2 and the vertical copper wiring pattern 2 intersect, the dummy wiring 3 is connected to the other (horizontal or vertical) copper wiring pattern. 2 is provided in a direction substantially perpendicular to the frame 2 so as to suppress the warp generated at the corner 1 f of the frame 1.

【0015】さらに、ダミー配線3は、半導体素子を樹
脂封止する樹脂封止領域4の内外に渡って延長させて設
ける。
Further, the dummy wiring 3 is provided so as to extend over the inside and outside of the resin sealing region 4 for sealing the semiconductor element with the resin.

【0016】樹脂封止領域4内の銅配線パターン2が形
成されたフレーム1の内装部1bは、半導体素子の電極
と半田付けする際に、熱の影響を受けるが、密に隣接し
た銅配線パターン2、及び銅配線パターン2の粗の部分
に設けたダミー配線3により、フレーム1の反りが抑え
られることとなる。
The interior portion 1b of the frame 1 in which the copper wiring pattern 2 in the resin sealing region 4 is formed is affected by heat when soldered to the electrodes of the semiconductor element. The pattern 2 and the dummy wiring 3 provided in the rough portion of the copper wiring pattern 2 suppress the warpage of the frame 1.

【0017】樹脂封止領域4外に露出した銅配線パター
ン2が形成されたフレーム1の外装部1cは、半導体素
子を樹脂封止する際、及び露出した銅配線パターン(端
部2b)2を外部回路等に半田付けする際などの場合
に、熱の影響を受けるが、密に隣接した銅配線パターン
2、及び樹脂封止領域4から外部に露出した銅配線パタ
ーン2の粗の部分に設けたダミー配線3により、フレー
ム1の反りが抑えられることとなる。
The exterior portion 1c of the frame 1 on which the copper wiring pattern 2 exposed outside the resin sealing region 4 is formed, when the semiconductor element is sealed with resin, and when the exposed copper wiring pattern (end portion 2b) 2 is formed. In the case of soldering to an external circuit or the like, it is affected by heat. However, it is provided on the copper wiring pattern 2 which is closely adjacent and the rough portion of the copper wiring pattern 2 which is exposed to the outside from the resin sealing region 4. The dummy wiring 3 suppresses the warpage of the frame 1.

【0018】[0018]

【発明の効果】以上説明したように本発明によれば、樹
脂封止領域の内外を問わず、いずれの箇所でも熱による
フレームの反りを防止して、銅配線パターンの断線を防
止することができる。
As described above, according to the present invention, it is possible to prevent the frame from being warped due to heat at any point regardless of the inside and outside of the resin sealing area, and to prevent disconnection of the copper wiring pattern. it can.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態に係る半導体装置のフレー
ムを示す平面図である。
FIG. 1 is a plan view showing a frame of a semiconductor device according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 フレーム 2 銅配線パターン 3 ダミー配線 4 樹脂封止領域 1 frame 2 copper wiring pattern 3 dummy wiring 4 resin sealing area

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 中央部に半導体素子搭載用のアイランド
を有し、その周辺に銅配線パターンとダミー配線とを有
し、前記アイランドに搭載された半導体素子の電極と前
記銅配線パターンとを電気的に接続し、前記半導体素子
を樹脂封止する半導体装置のフレームであって前記銅配線パターンは前記樹脂封止領域の内外に配置さ
れており、前記ダミー配線は、前記銅配線パターンの形
成領域に、前記樹脂封止領域の内外に渡って前記隣接す
る銅配線パターンの粗の部分に設けられ、熱によるフレ
ームの反りを抑えるものである ことを特徴とする半導体
装置のフレーム。
1. An island for mounting a semiconductor element in a central portion.
With a copper wiring pattern and dummy wiring around it.
And the electrodes of the semiconductor element mounted on the island
Electrically connecting the copper wiring pattern to the semiconductor element;
The is disposed a frame of a semiconductor device of a resin sealing, the copper wiring pattern on the inside and outside of the resin encapsulation region
And the dummy wiring has a shape of the copper wiring pattern.
In the resin forming area and the adjacent area.
Provided in the rough part of the copper wiring pattern
A frame for a semiconductor device, which suppresses warpage of a camera .
JP29834298A 1998-10-20 1998-10-20 Semiconductor device frame Expired - Fee Related JP3164084B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29834298A JP3164084B2 (en) 1998-10-20 1998-10-20 Semiconductor device frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29834298A JP3164084B2 (en) 1998-10-20 1998-10-20 Semiconductor device frame

Publications (2)

Publication Number Publication Date
JP2000124351A JP2000124351A (en) 2000-04-28
JP3164084B2 true JP3164084B2 (en) 2001-05-08

Family

ID=17858438

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29834298A Expired - Fee Related JP3164084B2 (en) 1998-10-20 1998-10-20 Semiconductor device frame

Country Status (1)

Country Link
JP (1) JP3164084B2 (en)

Also Published As

Publication number Publication date
JP2000124351A (en) 2000-04-28

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