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JP3164751B2 - Multilayer thin film wiring board - Google Patents
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JP3164751B2 - Multilayer thin film wiring board - Google Patents

Multilayer thin film wiring board

Info

Publication number
JP3164751B2
JP3164751B2 JP14163395A JP14163395A JP3164751B2 JP 3164751 B2 JP3164751 B2 JP 3164751B2 JP 14163395 A JP14163395 A JP 14163395A JP 14163395 A JP14163395 A JP 14163395A JP 3164751 B2 JP3164751 B2 JP 3164751B2
Authority
JP
Japan
Prior art keywords
film
circuit wiring
external lead
insulating film
wiring film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP14163395A
Other languages
Japanese (ja)
Other versions
JPH08335778A (en
Inventor
征一 高見
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP14163395A priority Critical patent/JP3164751B2/en
Publication of JPH08335778A publication Critical patent/JPH08335778A/en
Application granted granted Critical
Publication of JP3164751B2 publication Critical patent/JP3164751B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0201Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4673Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
    • H05K3/4676Single layer compositions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は混成集積回路装置や半導
体素子収納用パッケージ等に用いられる多層薄膜配線基
板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer thin film wiring board used for a hybrid integrated circuit device, a package for accommodating a semiconductor element, and the like.

【0002】[0002]

【従来の技術】従来、混成集積回路装置や半導体素子収
納用パッケージ等に使用される配線基板はその回路配線
がMoーMn法等の厚膜形成技術によって形成されてい
る。
2. Description of the Related Art Conventionally, a wiring board used for a hybrid integrated circuit device, a package for housing a semiconductor element, or the like has a circuit wiring formed by a thick film forming technique such as a Mo-Mn method.

【0003】このMoーMn法は、タングステン、モリ
ブデン、マンガン等の高融点金属から成る金属粉末に有
機溶剤、溶媒を添加し、ペースト状となした金属ペース
トを生もしくは焼結セラミック体の外表面にスクリーン
印刷法により回路配線としての所定パターンに印刷塗布
し、次にこれを還元雰囲気中で焼成し、高融点金属粉末
とセラミック体とを焼結一体化させる方法である。
In the Mo-Mn method, an organic solvent and a solvent are added to a metal powder composed of a high melting point metal such as tungsten, molybdenum, and manganese to form a paste-like metal paste on the outer surface of a raw or sintered ceramic body. In this method, a predetermined pattern as circuit wiring is printed and applied by screen printing, and then fired in a reducing atmosphere to sinter and integrate the high melting point metal powder and the ceramic body.

【0004】しかしながら、このMoーMn法を用いて
回路配線を形成した場合、回路配線は金属ペーストをス
クリーン印刷することにより形成されることから回路配
線の微細化が困難であり、回路配線の高密度化ができな
いという欠点を有していた。
However, when the circuit wiring is formed by using the Mo-Mn method, the circuit wiring is formed by screen-printing a metal paste, so that it is difficult to miniaturize the circuit wiring. There was a disadvantage that the density could not be increased.

【0005】そこで上記欠点を解消するために回路配線
を従来の厚膜形成技術により形成するのに替えて微細化
が可能な薄膜形成技術を用いて形成した多層薄膜配線基
板が使用されるようになってきた。
In order to solve the above-mentioned disadvantages, a multilayer thin-film wiring board formed by using a thin-film forming technique capable of miniaturization is used instead of forming a circuit wiring by a conventional thick-film forming technique. It has become.

【0006】この回路配線を薄膜形成技術により形成し
た多層薄膜配線基板は、通常、酸化アルミニウム質焼結
体やムライト質焼結体、炭化珪素質焼結体、窒化アルミ
ニウム質焼結体、ガラスセラミックス焼結体等から成る
絶縁基板上にアルミニウム、銅、クロム、ニッケル等か
ら成る回路配線膜とポリイミド等の有機高分子材料から
成る絶縁膜とを交互に多層に被着させた構造を有してお
り、回路配線膜に半導体素子やコンデンサ等の電極を半
田を介し接続させれば、半導体素子やコンデンサ等の各
電子部品はその各々が回路配線膜を介して互いに電気的
に接続されるようになっている。
A multilayer thin film wiring board in which the circuit wiring is formed by a thin film forming technique is usually made of an aluminum oxide sintered body, a mullite sintered body, a silicon carbide sintered body, an aluminum nitride sintered body, a glass ceramic. It has a structure in which a circuit wiring film made of aluminum, copper, chromium, nickel, etc. and an insulating film made of an organic polymer material such as polyimide are alternately applied in multiple layers on an insulating substrate made of a sintered body or the like. If the electrodes such as semiconductor elements and capacitors are connected to the circuit wiring film via solder, each electronic component such as the semiconductor elements and capacitors is electrically connected to each other via the circuit wiring film. Has become.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、前記多
層薄膜配線基板は回路配線膜に外部リード端子を従来一
般に使用されている金ー錫合金等から成るロウ材を用い
て取着し、回路配線膜を外部リード端子を介して他の外
部電気回路に電気的接続するようになした場合、金ー錫
合金等から成るロウ材の熱膨張係数が18×10-6/℃
であるのに対し回路配線膜の被着されているポリイミド
等の有機高分子から成る絶縁膜の熱膨張係数が40×1
-6/℃乃至50×10-6/℃であり、大きく相違する
ことから外部リード端子を取着するロウ材と絶縁膜に被
着されている回路配線膜との間にロウ材と絶縁膜の熱膨
張係数の相違に伴う大きな応力が発生し、この応力に起
因して外部リード端子の回路配線膜への取着の信頼性が
大きく低下するという欠点が誘発される。
However, in the multilayer thin-film wiring board, external lead terminals are attached to the circuit wiring film by using a brazing material made of a gold-tin alloy or the like generally used in the prior art. Is electrically connected to another external electric circuit through an external lead terminal, the brazing material made of a gold-tin alloy or the like has a thermal expansion coefficient of 18 × 10 −6 / ° C.
On the other hand, the thermal expansion coefficient of the insulating film made of an organic polymer such as polyimide on the circuit wiring film is 40 × 1.
0 −6 / ° C. to 50 × 10 −6 / ° C., which greatly differs from each other, so that the brazing material is insulated between the brazing material for attaching the external lead terminals and the circuit wiring film attached to the insulating film. A large stress is generated due to the difference in the coefficient of thermal expansion of the film, and this stress induces a disadvantage that the reliability of attaching the external lead terminal to the circuit wiring film is greatly reduced.

【0008】[0008]

【発明の目的】本発明は上記欠点に鑑み案出されたもの
で、その目的は回路配線膜に外部リード端子を強固に取
着し、回路配線膜に接続される電子部品を他の外部電気
回路に確実に電気的接続することができる多層薄膜配線
基板を提供することにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and has as its object to firmly attach an external lead terminal to a circuit wiring film and to connect an electronic component connected to the circuit wiring film to another external electric device. It is an object of the present invention to provide a multilayer thin-film wiring board that can reliably be electrically connected to a circuit.

【0009】[0009]

【課題を解決するための手段】本発明は絶縁基板上に薄
膜形成技術により有機高分子材料から成る絶縁膜と金属
材料から成る回路配線膜とを交互に多層に積層するとと
もに、前記回路配線膜に外部リード端子をロウ材を介し
て取着してなる多層薄膜配線基板であって、前記外部リ
ード端子がロウ材を介して取着される回路配線膜と接す
る絶縁膜の熱膨張係数が10×10-6/℃乃至30×1
-6/℃であるとともに前記外部リード端子のロウ付け
される回路配線膜と接する絶縁膜が、P−フェニレンジ
アミンとピロメリット酸無水物より得られるポリイミド
を20重量%含んだ4,4’−ジアミノジフェニルエー
テルと、ピロメリット酸無水物より得られるポリイミド
との共重合体で形成されていることを特徴とするもので
ある。
According to the present invention, an insulating film made of an organic polymer material and a circuit wiring film made of a metal material are alternately laminated in multiple layers on an insulating substrate by a thin film forming technique. A multilayer thin-film wiring board having external lead terminals attached thereto via a brazing material, wherein the thermal expansion coefficient of an insulating film in contact with a circuit wiring film to which the external lead terminals are attached via the brazing material is 10 × 10 -6 / ° C to 30 × 1
0-4 / ° C., and the insulating film in contact with the circuit wiring film to which the external lead terminal is to be brazed is 4,4 ′ containing 20% by weight of a polyimide obtained from P-phenylenediamine and pyromellitic anhydride. -Is formed of a copolymer of diaminodiphenyl ether and a polyimide obtained from pyromellitic anhydride.

【0010】[0010]

【0011】[0011]

【作用】本発明の多層薄膜配線基板によれば、外部リー
ド端子がロウ付けされる回路配線膜と接する絶縁膜の熱
膨張係数を10×10-6/℃乃至30×10-6/℃とす
るとともに外部リード端子のロウ付けされる回路配線膜
と接する絶縁膜をP−フェニレンジアミンとピロメリッ
ト酸無水物より得られるポリイミドを20重量%含んだ
4,4’−ジアミノジフェニルエーテルと、ピロメリッ
ト酸無水物より得られるポリイミドとの共重合体で形成
し、回路配線膜に外部リード端子を取着するロウ材の熱
膨張係数に近似させたことから回路配線膜に外部リード
端子をロウ材を用いて取着し、回路配線膜を外部リード
端子を介して他の外部電気回路に電気的接続するように
なした際、外部リード端子を取着するロウ材と絶縁膜に
被着されている回路配線膜との間にロウ材と絶縁膜の熱
膨張係数の相違に伴う大きな応力が発生することはな
く、その結果、外部リード端子は回路配線膜に強固に取
着され、回路配線膜に接続される電子部品を外部リード
端子を介して他の外部電気回路に確実に電気的接続する
ことが可能となる。
According to the multilayer thin film wiring board of the present invention, the thermal expansion coefficient of the insulating film in contact with the circuit wiring film to which the external lead terminals are to be brazed is 10 × 10 −6 / ° C. to 30 × 10 −6 / ° C. And 4,4′-diaminodiphenyl ether containing 20% by weight of a polyimide obtained from P-phenylenediamine and pyromellitic anhydride, and an insulating film in contact with a circuit wiring film to which an external lead terminal is to be brazed, and pyromellitic acid Formed from a copolymer with polyimide obtained from an anhydride, the external lead terminals were attached to the circuit wiring film. When the circuit wiring film is electrically connected to another external electric circuit via the external lead terminals, the circuit attached to the brazing material for attaching the external lead terminals and the insulating film is attached. There is no large stress generated between the wiring film and the thermal expansion coefficient between the brazing material and the insulating film. As a result, the external lead terminals are firmly attached to the circuit wiring film and connected to the circuit wiring film. It is possible to reliably electrically connect the electronic component to be connected to another external electric circuit via the external lead terminal.

【0012】[0012]

【実施例】次に本発明を添付図面に基づき詳細に説明す
る。図1は本発明の多層薄膜配線基板の一実施例を示し
1は絶縁基板、2は回路配線膜、3は絶縁膜である。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 shows an embodiment of a multilayer thin film wiring board according to the present invention, wherein 1 is an insulating substrate, 2 is a circuit wiring film, and 3 is an insulating film.

【0013】前記絶縁基板1は酸化アルミニウム質焼結
体、ムライト質焼結体、炭化珪素質焼結体、窒化アルミ
ニウム質焼結体、ガラスセラミックス焼結体等の電気絶
縁材料より成り、その上面に回路配線膜2と絶縁膜3と
から成る多層配線部Aが被着されている。
The insulating substrate 1 is made of an electrically insulating material such as an aluminum oxide sintered body, a mullite sintered body, a silicon carbide sintered body, an aluminum nitride sintered body, a glass ceramic sintered body, etc. Is covered with a multilayer wiring portion A including a circuit wiring film 2 and an insulating film 3.

【0014】前記絶縁基板1は多層配線部Aを支持する
支持部材として作用し、例えば、酸化アルミニウム質焼
結体からなる場合には、アルミナ、シリカ、マグネシ
ア、カルシア等の原料粉末に適当な有機溶剤、溶媒を添
加混合して泥漿状となすとともにこれをドクターブレー
ド法やカレンダーロール法等を採用することによってセ
ラミックグリーンシート(セラミック生シート)を形成
し、しかる後、前記セラミックグリーンシートに適当な
打ち抜き加工を施し、所定形状となすとともに高温(約
1600℃)で焼成することによって製作される。
The insulating substrate 1 functions as a supporting member for supporting the multilayer wiring portion A. For example, when the insulating substrate 1 is made of an aluminum oxide sintered body, an organic material suitable for a raw material powder such as alumina, silica, magnesia, and calcia is used. A solvent and a solvent are added and mixed to form a slurry, which is then formed into a ceramic green sheet (raw ceramic sheet) by employing a doctor blade method, a calender roll method, or the like. It is manufactured by punching, forming a predetermined shape, and firing at a high temperature (about 1600 ° C.).

【0015】また前記絶縁基板1の上面に被着されてい
る多層配線部Aは回路配線膜2と絶縁膜3とを交互に多
層に積層することによって形成されており、該回路配線
膜2に半導体素子4やコンデンサ5等の電子部品を半田
を介して接続すれば該半導体素子4やコンデンサ5等の
電子部品は回路配線膜2を介して各々が電気的に接続さ
れる。
The multilayer wiring portion A attached to the upper surface of the insulating substrate 1 is formed by alternately stacking the circuit wiring films 2 and the insulating films 3 in multiple layers. When electronic components such as the semiconductor element 4 and the capacitor 5 are connected via solder, the electronic components such as the semiconductor element 4 and the capacitor 5 are electrically connected via the circuit wiring film 2.

【0016】前記多層配線部Aの回路配線膜2は、例え
ばアルミニウム、銅、クロム、ニッケル等の金属材料か
ら成り、蒸着法やスパッタリング法等の薄膜形成技術及
びエッチング加工技術を採用することによって絶縁基板
1上で、間に絶縁膜3を挟んで多層に被着形成される。
この場合、回路配線膜2は薄膜形成技術により形成され
ることから回路配線膜2の微細化が可能となり回路配線
膜2を高密度に形成することができる。
The circuit wiring film 2 of the multilayer wiring portion A is made of a metal material such as aluminum, copper, chromium, nickel or the like, and is insulated by employing a thin film forming technique such as a vapor deposition method or a sputtering method and an etching technique. On the substrate 1, a multi-layer is formed with an insulating film 3 interposed therebetween.
In this case, since the circuit wiring film 2 is formed by a thin film forming technique, the circuit wiring film 2 can be miniaturized, and the circuit wiring film 2 can be formed at a high density.

【0017】尚、前記回路配線膜2はその厚みが0.5
μm未満であると回路配線膜2の電気抵抗値が大きくな
る傾向にあり、また20μmを越えると回路配線膜2を
薄膜形成技術により形成する際の内部応力によって回路
配線膜2が絶縁膜3より剥離し易くなる傾向にあること
から0.5μm乃至20μmの範囲が良く、好適には1
μm乃至10μmの厚みに、最適には2μm乃至5μm
の厚みにしておくことが良い。
The circuit wiring film 2 has a thickness of 0.5
If it is less than μm, the electric resistance of the circuit wiring film 2 tends to be large, and if it exceeds 20 μm, the circuit wiring film 2 is less than the insulating film 3 due to internal stress when the circuit wiring film 2 is formed by the thin film forming technique. The thickness is preferably in the range of 0.5 μm to 20 μm, and preferably 1 μm to 20 μm.
μm to 10 μm thickness, optimally 2 μm to 5 μm
It is good to keep the thickness.

【0018】また前記回路配線膜2のうち最上部に位置
するものには外部リード端子6が金ー錫合金等のロウ材
7を介して取着されており、該外部リード端子6は回路
配線膜2に接続されている半導体素子4やコンデンサ5
等の電子部品を他の外部電気回路に電気的に接続する作
用を為す。
An external lead terminal 6 is attached to the uppermost one of the circuit wiring films 2 via a brazing material 7 such as a gold-tin alloy. Semiconductor element 4 and capacitor 5 connected to film 2
And the like to electrically connect such electronic components to other external electric circuits.

【0019】前記外部リード端子6は鉄ーニッケルーコ
バルト合金や鉄ーニッケル合金、銅等の金属材料で形成
されており、例えば、鉄ーニッケルーコバルト合金等の
インゴット(塊)を圧延加工法や打ち抜き加工法等、従
来周知の金属加工を施すことによって所定の形状に形成
される。
The external lead terminals 6 are formed of a metal material such as an iron-nickel-cobalt alloy, an iron-nickel alloy, or copper. It is formed into a predetermined shape by performing a conventionally known metal working such as a punching method.

【0020】更に前記回路配線膜2の間には絶縁膜3が
配されており、該絶縁膜3は上下に位置する各回路配線
膜2の電気的絶縁を維持する作用を為す。
Further, an insulating film 3 is disposed between the circuit wiring films 2, and the insulating film 3 has a function of maintaining electrical insulation of the circuit wiring films 2 located above and below.

【0021】前記絶縁膜3はポリイミド樹脂等の有機高
分子材料から成り、例えば4,4’ージアミノジフェニ
ルエーテル50モル%、ジアミノジフェニルスルホン5
0モル%、3,3’ービフェニルテトラカルボン酸二無
水物から成るポリマ溶液を絶縁基板1上にスピンコーテ
ィング法により塗布し、しかる後、これに約400℃の
熱を加えてポリマ溶液を熱架橋させることによって絶縁
基板1上で回路配線膜2の間に被着形成される。
The insulating film 3 is made of an organic polymer material such as a polyimide resin. For example, 50 mol% of 4,4′-diaminodiphenyl ether,
A polymer solution containing 0 mol% of 3,3′-biphenyltetracarboxylic dianhydride is applied onto the insulating substrate 1 by a spin coating method, and then heated at about 400 ° C. to heat the polymer solution. By cross-linking, it is formed between the circuit wiring films 2 on the insulating substrate 1.

【0022】尚、前記絶縁膜3はその厚みが0.5μm
未満であると絶縁膜3にピンホールが発生して絶縁膜3
を挟んで上下に形成された回路配線膜2間の電気的絶縁
を図ることが困難となる傾向にあり、また40μmを越
えると絶縁膜3を形成する際の内部応力によって絶縁膜
3が回路配線膜2より剥離し易くなる傾向にあることか
ら0.5μm乃至40μmの範囲が良く、好適には2.
5μm乃至20μmの厚みに、最適には5μm乃至15
μmの厚みにしておくことが良い。
The thickness of the insulating film 3 is 0.5 μm.
If it is less than 3, a pinhole is generated in the insulating film 3 and the insulating film 3
There is a tendency that it is difficult to achieve electrical insulation between the circuit wiring films 2 formed above and below the insulating film 3. If the thickness exceeds 40 μm, the insulating film 3 may be damaged due to internal stress when the insulating film 3 is formed. The thickness is preferably in the range of 0.5 μm to 40 μm, and more preferably 2.
5 μm to 20 μm thickness, optimally 5 μm to 15 μm
It is good to keep the thickness of μm.

【0023】更に前記絶縁膜3のうち、少なくとも外部
リード端子6がロウ材7を介して取着される回路配線膜
2と接する絶縁膜3aの熱膨張係数が10×10-6/℃
乃至30×10-6/℃となっており、これによって回路
配線膜2に外部リード端子6をロウ材7を用いて取着し
ても外部リード端子6を取着するロウ材7と絶縁膜3a
に被着されている回路配線膜2との間にロウ材7と絶縁
膜3aの熱膨張係数の相違に伴う大きな応力が発生する
ことはなく、その結果、外部リード端子6は回路配線膜
2に強固に取着され、回路配線膜2に接続されている半
導体素子4やコンデンサ5等の電子部品を外部リード端
子6を介して他の外部電気回路に確実に電気的接続する
ことが可能となる。
Further, the thermal expansion coefficient of the insulating film 3a of the insulating film 3 that contacts at least the circuit wiring film 2 to which the external lead terminals 6 are attached via the brazing material 7 is 10 × 10 −6 / ° C.
To 30 × 10 −6 / ° C., so that even when the external lead terminals 6 are attached to the circuit wiring film 2 using the brazing material 7, the brazing material 7 for attaching the external lead terminals 6 and the insulating film 3a
No large stress is generated between the circuit material 2 and the circuit wiring film 2 due to the difference in the thermal expansion coefficient between the brazing material 7 and the insulating film 3a. The electronic components such as the semiconductor element 4 and the capacitor 5 which are firmly attached to the circuit wiring film 2 and connected to the circuit wiring film 2 can be reliably electrically connected to other external electric circuits via the external lead terminals 6. Become.

【0024】前記絶縁膜3のうち、少なくとも外部リー
ド端子6がロウ材7を介して取着される回路配線膜2と
接する絶縁膜3aは、例えば、Pーフェニレンジアミン
とピロメリット酸無水物より得られるポリイミドを20
重量%含んだ4,4’ージアミノジフェニルエーテル
と、ピロメリット酸無水物より得られるポリイミドとの
共重合体で形成されており、ポリマ溶液を絶縁基板1上
にスピンコーティング法により塗布し、しかる後、これ
に約400℃の熱を加えてポリマ溶液を熱架橋させるこ
とによって外部リード端子6がロウ材7を介して取着さ
れる回路配線膜2の下部に配される。
In the insulating film 3, at least the insulating film 3a in contact with the circuit wiring film 2 to which the external lead terminals 6 are attached via the brazing material 7 is made of, for example, P-phenylenediamine and pyromellitic anhydride. The resulting polyimide is 20
It is formed of a copolymer of 4,4'-diaminodiphenyl ether containing 4% by weight and a polyimide obtained from pyromellitic anhydride, and a polymer solution is applied onto the insulating substrate 1 by a spin coating method. The external lead terminals 6 are disposed under the circuit wiring film 2 to be attached via the brazing material 7 by applying heat of about 400 ° C. to thermally crosslink the polymer solution.

【0025】尚、前記外部リード端子6がロウ材7を介
して取着される回路配線膜2と接する絶縁膜3aはその
熱膨張係数が10×10-6/℃未満、あるいは30×1
-6/℃を越えると外部リード端子6を取着するロウ材
7と絶縁膜3aに被着されている回路配線膜2との間に
ロウ材7と絶縁膜3aの熱膨張係数の相違に伴う大きな
熱応力が発生し、外部リード端子6を回路配線膜2に強
固に取着することができなくなる。従って、前記外部リ
ード端子6がロウ材7を介して取着される回路配線膜2
と接する絶縁膜3aはその熱膨張係数が10×10-6
℃乃至30×10-6/℃の範囲に特定される。
The insulating film 3a in contact with the circuit wiring film 2 to which the external lead terminals 6 are attached via the brazing material 7 has a thermal expansion coefficient of less than 10 × 10 −6 / ° C. or 30 × 1.
If the temperature exceeds 0 -6 / ° C., the difference in the thermal expansion coefficient between the brazing material 7 and the insulating film 3a between the brazing material 7 for attaching the external lead terminal 6 and the circuit wiring film 2 provided on the insulating film 3a. As a result, a large thermal stress is generated, and the external lead terminals 6 cannot be firmly attached to the circuit wiring film 2. Accordingly, the circuit wiring film 2 to which the external lead terminals 6 are attached via the brazing material 7
Has a thermal expansion coefficient of 10 × 10 −6 /
It is specified in the range of 30 ° C. to 30 × 10 −6 / ° C.

【0026】かくして上述の多層薄膜配線基板によれ
ば、絶縁基板1の上面に被着させた多層配線部Aの回路
配線膜2に半導体素子4やコンデンサ5等の電子部品を
半田を介して接続すれば半導体素子4やコンデンサ5等
の電子部品はその各々が回路配線膜2を介して電気的に
接続され、外部リード端子6を他の外部電気回路基板に
接続すれば半導体素子4やコンデンサ5等の電子部品は
外部リード端子6を介して外部電気回路基板に電気的に
接続される。
Thus, according to the above-described multilayer thin film wiring board, electronic components such as the semiconductor element 4 and the capacitor 5 are connected to the circuit wiring film 2 of the multilayer wiring portion A attached on the upper surface of the insulating substrate 1 via solder. Then, the electronic components such as the semiconductor element 4 and the capacitor 5 are electrically connected to each other via the circuit wiring film 2, and if the external lead terminals 6 are connected to another external electric circuit board, the semiconductor element 4 and the capacitor 5 Such electronic components are electrically connected to an external electric circuit board via the external lead terminals 6.

【0027】尚、本発明は上述の実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲であれば種
々の変更は可能であり、例えば、上述の実施例において
外部リード端子6の表面にニッケル、金等の耐蝕性に優
れ、且つロウ材と濡れ性の良い金属をメッキ法により
0.1μm乃至20μmの厚みに被着させておくと外部
リード端子6の酸化腐食を有効に防止することができる
とともに外部リード端子6と外部電気回路基板との接続
を良好となすことができる。従って、前記外部リード端
子6はその表面にニッケル、金等を0.1μm乃至20
μmの厚みに被着させておくことが好ましい。
It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention. If a metal having excellent corrosion resistance, such as nickel and gold, and a good wettability with a brazing material is applied to the surface of the surface to a thickness of 0.1 μm to 20 μm by a plating method, the oxidative corrosion of the external lead terminals 6 can be effectively prevented. In addition, the connection between the external lead terminals 6 and the external electric circuit board can be improved. Therefore, the external lead terminal 6 is made of nickel, gold,
It is preferable that it is applied to a thickness of μm.

【0028】[0028]

【0029】[0029]

【発明の効果】本発明の多層薄膜配線基板によれば、外
部リード端子がロウ付けされる回路配線膜と接する絶縁
膜の熱膨張係数を10×10-6/℃乃至30×10-6
℃とするとともに外部リード端子のロウ付けされる回路
配線膜と接する絶縁膜をP−フェニレンジアミンとピロ
メリット酸無水物より得られるポリイミドを20重量%
含んだ4,4’−ジアミノジフェニルエーテルと、ピロ
メリット酸無水物より得られるポリイミドとの共重合体
で形成し、回路配線膜に外部リード端子を取着するロウ
材の熱膨張係数に近似させたことから回路配線膜に外部
リード端子をロウ材を用いて取着し、回路配線膜を外部
リード端子を介して他の外部電気回路に電気的接続する
ようになした際、外部リード端子を取着するロウ材と絶
縁膜に被着されている回路配線膜との間にロウ材と絶縁
膜の熱膨張係数の相違に伴う大きな応力が発生すること
はなく、その結果、外部リード端子は回路配線膜に強固
に取着され、回路配線膜に接続される電子部品を外部リ
ード端子を介して他の外部電気回路に確実に電気的接続
することが可能となる。
According to the multilayer thin film wiring board of the present invention, the thermal expansion coefficient of the insulating film in contact with the circuit wiring film to which the external lead terminals are to be brazed is 10 × 10 −6 / ° C. to 30 × 10 −6 /.
° C and the insulating film in contact with the circuit wiring film to which the external lead terminals are to be brazed is 20% by weight of a polyimide obtained from P-phenylenediamine and pyromellitic anhydride.
It was formed from a copolymer of the contained 4,4'-diaminodiphenyl ether and a polyimide obtained from pyromellitic anhydride, and approximated to the thermal expansion coefficient of a brazing material for attaching external lead terminals to a circuit wiring film. Therefore, when an external lead terminal is attached to the circuit wiring film using a brazing material and the circuit wiring film is electrically connected to another external electric circuit via the external lead terminal, the external lead terminal is removed. No large stress is generated between the brazing material to be attached and the circuit wiring film attached to the insulating film due to the difference in the coefficient of thermal expansion between the brazing material and the insulating film. The electronic components firmly attached to the wiring film and connected to the circuit wiring film can be reliably electrically connected to other external electric circuits via external lead terminals.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の多層薄膜配線基板の一実施例を示す断
面図である。
FIG. 1 is a sectional view showing one embodiment of a multilayer thin film wiring board of the present invention.

【符号の説明】[Explanation of symbols]

1・・・・・・絶縁基板 2・・・・・・回路配線膜 3・・・・・・絶縁膜 6・・・・・・外部リード端子 7・・・・・・ロウ材 A・・・・・・多層配線部 DESCRIPTION OF SYMBOLS 1 ... Insulating board 2 ... Circuit wiring film 3 ... Insulating film 6 ... External lead terminal 7 ... Brazing material A ... .... Multilayer wiring part

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】絶縁基板上に薄膜形成技術より有機高分
子材料から成る絶縁膜と金属材料から成る回路配線膜と
を交互に多層に積層するとともに、前記回路配線膜に外
部リード端子をロウ材を介して取着してなる多層薄膜配
線基板であって、前記外部リード端子がロウ材を介して
取着される回路配線膜と接する絶縁膜の熱膨張係数が1
0×10-6/℃乃至30×10-6/℃であるとともに前
記外部リード端子のロウ付けされる回路配線膜と接する
絶縁膜が、P−フェニレンジアミンとピロメリット酸無
水物より得られるポリイミドを20重量%含んだ4,
4’−ジアミノジフェニルエーテルと、ピロメリット酸
無水物より得られるポリイミドとの共重合体で形成され
ていることを特徴とする多層薄膜配線基板。
1. A with laminated in multiple layers alternating with more comprising an organic polymer material insulating film and the circuit wiring film made of a metal material film forming technique on an insulating substrate, a row of external lead terminals to the circuit wiring film a multilayer thin film wiring board formed by attaching via the timber, the thermal expansion coefficient of the insulating film before Kigai unit lead terminal in contact with the circuit wiring film which is attached via a brazing material 1
0 × 10 -6 / ℃ to prior as well as a 30 × 10 -6 / ℃
Contact with the circuit wiring film to be soldered to the external lead terminal
Insulation film without P-phenylenediamine and pyromellitic acid
4, containing 20% by weight of polyimide obtained from water
4'-diaminodiphenyl ether and pyromellitic acid
Formed with a copolymer with polyimide obtained from anhydride
Multilayer thin film wiring board, characterized by that.
JP14163395A 1995-06-08 1995-06-08 Multilayer thin film wiring board Expired - Fee Related JP3164751B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14163395A JP3164751B2 (en) 1995-06-08 1995-06-08 Multilayer thin film wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14163395A JP3164751B2 (en) 1995-06-08 1995-06-08 Multilayer thin film wiring board

Publications (2)

Publication Number Publication Date
JPH08335778A JPH08335778A (en) 1996-12-17
JP3164751B2 true JP3164751B2 (en) 2001-05-08

Family

ID=15296587

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14163395A Expired - Fee Related JP3164751B2 (en) 1995-06-08 1995-06-08 Multilayer thin film wiring board

Country Status (1)

Country Link
JP (1) JP3164751B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4012375B2 (en) * 2001-05-31 2007-11-21 株式会社ルネサステクノロジ Wiring board and manufacturing method thereof
JP4689375B2 (en) * 2005-07-07 2011-05-25 富士通株式会社 Laminated substrate and electronic device having the laminated substrate
CN115547962B (en) * 2022-10-25 2026-02-24 广州天极电子科技股份有限公司 Film circuit with gold-tin preformed bonding pad with buffer structure and preparation method thereof

Also Published As

Publication number Publication date
JPH08335778A (en) 1996-12-17

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