JP3166682B2 - Phase shift circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase shift circuit for shifting the phase of an input signal by a phase shift amount corresponding to the frequency.

[0002]

2. Description of the Related Art In an audio device or the like, a process of shifting the phase of an audio signal is often performed. In particular, in a surround device or the like, a phase shift circuit capable of shifting the phase from 0 to -2π depending on the frequency of the audio signal is required.

There is an all-pass filter as a means for performing such a phase shift. FIG. 4 shows a configuration of an all-pass filter 100 as an example. The all-pass filter 100 includes an operational amplifier 101, resistors 102 to 104, and a capacitor 105. Here, the resistors 103 and 104 have the same resistance value. Therefore, if the input voltage of the all-pass filter 100 is Vi and the output voltage is Vo, the input voltage Vn of the inverting input terminal (-) of the operational amplifier 101 is given by the following equation. Vn = (Vi + Vo) / 2 (1)

On the other hand, assuming that the resistance value of the resistor 102 is R1, the capacitance value of the capacitor 305 is C1, and the angular frequency of the input voltage Vi is ω, the non-inverting input terminal (+) of the operational amplifier 101
Is given by the following equation. Vp = Vi / (1 + jωC1R1) (2)

Here, in the configuration shown in the drawing, a virtual short circuit is performed between the inverting input terminal (-) and the non-inverting input terminal (+) of the operational amplifier 101 by negative feedback operation, and Vp = Vn. It will be. (Vi + Vo) / 2 = Vi / (1 + jωC1R1) (3)

By transforming equation (3), the transfer function H of the all-pass filter 100 is obtained as follows. H = Vo / Vi = (1−jωC1R1) / (1 + jωC1R1) (4)

From the equation (4), the amplification factor A of the all-pass filter 100 is as follows: A = │H│ = │ (1-jωC1R1) / (1 + jωC1R1) │ = │ (1-jωC1R1) │ / │ (1 + jωC1R1) | = 1 (5) Therefore, the input signal Vi of any frequency passes through the all-pass filter 100 with the same amplitude.

The phase of the input signal Vi is shifted when passing through the all-pass filter 100. In this case, the phase shift amount θ is given by the following equation. θ = arg (H) = − 2 tan −1 (ωC1R1) (6)

As is apparent from the above equation (6), the amount of phase shift given to the input signal Vi by the all-pass filter 100 changes from 0 to -π due to the change of the frequency f = ω / 2π of the input signal. FIG. 5 shows the relationship between the frequency f and the amount of phase shift of the all-pass filter 100.

FIG. 6 shows a phase shift circuit in which two all-pass filters 100A and 100B having the configuration described above are cascaded. In this phase shift circuit, the all-pass filters 100A and 100B can shift the phase of the input signal from 0 to -π depending on the frequency. Therefore, the phase shift circuit shown in FIG. 6 can perform a phase shift from 0 to −2π as shown in FIG. 7, and can be used in the above-described surround device and the like.

[0011]

The phase shift circuit shown in FIG. 6 requires two operational amplifiers, as is apparent from FIG. Therefore, when configuring an integrated circuit for an audio device including this phase shift circuit, it is necessary to form many elements as components of the two operational amplifiers on an IC chip. For this reason, there has been a problem that the area of the IC chip increases and the unit price of the IC chip increases.

The present invention has been made in view of the circumstances described above, and has a small number of elements and is inexpensive.
It is an object of the present invention to provide a phase shift circuit capable of shifting the phase up to 2π.

[0013]

According to the present invention, there is provided a phase shift circuit for shifting the phase of an input signal by an amount corresponding to the frequency of the input signal and outputting the shifted signal from an output terminal. An output current and 2 of the first output current
A current output type operational amplifier having a magnitude of ３ times and outputting a second output current having a phase opposite to that of the first output current;
A first time constant circuit formed by connecting a first resistor and a first capacitor in series, and passing a part of the first output current; and the first time constant of the first output current A second resistor that guides a current that does not flow to a circuit to the output terminal, the second resistor having a resistance twice as large as the first resistor, and a second resistor that passes a part of the second output current. A capacitor, and a third resistor for guiding a current of the second output current that does not flow through the second capacitor to the output terminal, and is configured by the second capacitor and the third resistor. The gist of the present invention is a phase shift circuit characterized in that the time constant is smaller than the time constant of the first time constant circuit.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments will be described to make the present invention easier to understand. Such an embodiment shows one aspect of the present invention, and does not limit the present invention, and can be arbitrarily changed within the scope of the present invention.

FIG. 1 is a circuit diagram showing a configuration of a phase shift circuit according to an embodiment of the present invention. In FIG. 1, reference numeral 10 denotes an input terminal to which an input signal is applied, and 11 denotes an input resistor.
Reference numeral 12 denotes a current operational amplifier that amplifies a current supplied through the input resistor 11. This current operational amplifier 1
2 input terminals are virtually grounded. Therefore, an input current I proportional to the input signal flows from the input terminal 10 to the input terminal of the current operational amplifier 12 via the input resistor 11. The current operational amplifier 12 amplifies the input current I, and I1 = 3 from one of the two output terminals.
A current I is output, and I2 = -2 from the other output terminal.
The current I is output.

Various types of current operational amplifiers having such a function are conceivable. FIG. 2 shows an example. Here, a configuration example of the current operational amplifier 12 will be described with reference to FIG.

In FIG. 2, sources of P-channel MOS (metal oxide semiconductor structure) transistors P1 and P2 are commonly connected. This common connection point and the positive power supply VDD
A constant current source CC1 capable of supplying a constant current 2I10 is interposed between the two. Here, the gate of the P-channel MOS transistor P1 is connected to the input terminal 10 via the input resistor 11.
And a P-channel MOS transistor P2
Gate is grounded. And a P-channel MOS
The drain of transistor P1 is connected to the drain and gate of N-channel MOS transistor N1 and the gate of N-channel MOS transistor N2.
The source of the channel MOS transistor N1 is a negative power supply VSS.
It is connected to the. On the other hand, the drain of the P-channel MOS transistor P2 is
2 is connected to the drain of the N-channel MOS
The source of the transistor N2 is connected to the negative power supply VSS.

The circuit composed of the components described above constitutes a differential amplifier. Here, the operation of the differential amplifier will be described assuming an ideal case. First, P
When the gate level of channel MOS transistor P1 matches the ground level, gate bias of the same magnitude is applied to P channel MOS transistors P1 and P2. At this time, N-channel MOS transistors N1 and N2 operate as a current mirror. Therefore, the current 2I10 of the constant current source CC1 is divided into two, and currents I10 of the same magnitude flow through the P-channel MOS transistor P1 and the P-channel MOS transistor P2, respectively.

However, the P-channel MOS transistor P
When the gate level of 1 becomes higher than the ground level, the gate bias of the P-channel MOS transistor P1 decreases, so that the current flowing to the P-channel MOS transistor P1 becomes, for example, I10-.DELTA.I, and the current flowing to the P-channel MOS transistor P2 becomes I10 + ΔI. As a result, the level of the drain of the N-channel MOS transistor N2 changes in the positive direction, and conversely, the level of the drain of the N-channel MOS transistor N1 changes in the negative direction.

Further, a P-channel MOS transistor P1
When the gate level of the N-channel MOS transistor N2 becomes lower than the ground level, the operation is completely opposite to that described above.
The level of the drain of the S transistor N1 changes in the positive direction.

The drain of the N-channel MOS transistor N2 forms the output terminal of the differential amplifier described above, and is connected to the gate of the N-channel MOS transistor N3. The source of the N-channel MOS transistor N3 is connected to the negative power source VSS, and the drain is connected to the positive power source VD via a constant current source CC2 capable of supplying a constant current I20.
D. The drain of the N-channel MOS transistor N3 is connected to the gate of the P-channel MOS transistor P1 in the differential amplifier. That is, the output signal of the differential amplifier is N-channel MO
This is a configuration in which negative feedback is provided to the differential amplifier via the S transistor N3.

With such a configuration, the P channel M
The gate of the OS transistor P1 is always in a virtual ground state. That is, if the P-channel MOS transistor P
When the gate level of 1 is going to be higher than the ground level, the level of the drain of N-channel MOS transistor N2 changes in the positive direction, thereby increasing the gate bias of N-channel MOS transistor N3. The conductance increases, preventing an increase in the level of the gate of P-channel MOS transistor P1. Conversely, when the gate level of P-channel MOS transistor P1 is going to be lower than the ground level, the level of the drain of N-channel MOS transistor N2 changes in the negative direction.
Since the gate bias of the S transistor N3 decreases,
The conductance of N-channel MOS transistor N3 is reduced, and a decrease in the level of the gate of P-channel MOS transistor P1 is prevented. Thus, the P-channel MO
The operation of matching the level of the gate of the S transistor P1 to the ground level is always performed.

Then, a P-channel MOS transistor P
Since gate 1 is thus virtually grounded,
The current I proportional to the input voltage of the input terminal 10 is the input resistance 1
1 and the current I and the constant current I from the constant current source CC2.
20 plus I20 + I flows through N-channel MOS transistor N3. At this time, the operating point of N-channel MOS transistor N3 is in the saturation region.
The gate voltage required to flow the drain current I20 + I to the OS transistor N3 is equal to the N-channel MOS transistor N
2 is output from the drain. That is, the gate voltage required to flow the drain current I20 + I is equal to the N-channel MO.
When not applied to S transistor N3, the drain level of N-channel MOS transistor N3 rises → the gate bias of P-channel MOS transistor P1 decreases → the gate voltage of N-channel MOS transistor N3 increases → the N-channel MOS transistor N3 The operation of preventing the drain level from rising is performed.
The gate voltage required to flow the drain current I20 + I is N
This is applied to the channel MOS transistor N3.

The N-channel MOS transistor N4 has a source connected to the negative power supply VSS and a drain connected to the positive power supply VDD via a constant current source CC3 capable of supplying a constant current 2I20.
It is connected to the. The gate of the N-channel MOS transistor N4 has an N-channel MOS transistor N3.
Similarly, an output voltage from the drain of N-channel MOS transistor N2 is applied. Where N channel M
OS transistor N4 has twice the size of N-channel MOS transistor N3. Therefore, when the drain current I20 + I flows through the N-channel MOS transistor N3, the drain current 2I20 + 2I can flow through the N-channel MOS transistor N4.
Then, the constant current 2I20 from the constant current source CC3 flows into the N-channel MOS transistor N4.
It is possible to pull in. This is the output current I2 = -2I of the current operational amplifier.

Next, an N-channel MOS transistor N5
Has a source connected to the negative power supply VSS and a gate connected to N-channel MOS transistors N3 and N4.
Similarly, an output voltage from the drain of N-channel MOS transistor N2 is applied. Where N channel M
The OS transistor N5 has a size three times as large as the N-channel MOS transistor N3. Therefore, when drain current I20 + I flows through N channel MOS transistor N3, drain current 3I20 + 3I can flow through N channel MOS transistor N5.

The sources of the P-channel MOS transistors P6 and P7 are connected to the positive power supply VDD.
The drain of the N-channel MOS transistor N5 is connected to the drain and gate of the P-channel MOS transistor P6 and the P-channel MOS transistor P7.
Connected to the gate. Here, P-channel MOS
Transistors P6 and P7 form a current mirror.

Therefore, N-channel MOS transistor N
5, a drain current 3I20 + 3I flows through the P-channel MOS transistor P7.

The constant current source CC4 is a constant current source capable of supplying a constant current 3I20. One end of the constant current source CC4 is connected to the positive power supply VDD, and the other end is connected to the drain and gate of the N-channel MOS transistor N6 and the N-channel MOS transistor N6.
It is connected to the gate of OS transistor N7. These N channel MOS transistors N6 and N7
Each source is connected to the negative power supply VSS. Here, N channel MOS transistors N6 and N7 form a current mirror, and a constant current 3I20 from constant current source CC4 flows through N channel MOS transistor N6. Therefore, the same drain current 3I20 flows through the N-channel MOS transistor N7.

The drain of the N-channel MOS transistor N7 is connected to the P-channel MOS transistor P
7 is connected to the drain. Where P channel M
As described above, the drain current 3 is applied to the OS transistor P7.
I20 + 3I flows. On the other hand, the constant current 3I20 from the constant current source CC4 flows through the N-channel MOS transistor N7. Therefore, the current 3I flows from the connection point between the drains of the N-channel MOS transistor N7 and the P-channel MOS transistor P7 to the outside. This is the output current I1 = 3I of the current operational amplifier. The above is the details of the current operational amplifier 12 illustrated in FIG.

In FIG. 1, the output terminal of the current I1 in the current operational amplifier 12 is a resistor 21 and a capacitor 2
2 is grounded. A resistor 2 is connected between the output terminal of the current I1 and the output terminal 40 of the phase shift circuit.
3 is inserted. On the other hand, the output terminal of the current I2 in the current operational amplifier 11 is grounded via the capacitor 31. Further, a resistor 32 is interposed between the output terminal of the current I2 and the output terminal 40 of the phase shift circuit. Here, the resistor 21 has a resistance value R1, and the resistor 23 has a resistance value R2 = 2R1 which is twice as large. The capacitance C1 of the capacitor 22 is larger than the capacitance C2 of the capacitor 31. The resistor 32 has a resistance value R3
The time constant C2R3 of the time constant circuit including the resistor 32 and the capacitor 31 is sufficiently smaller than the time constant C1R1 of the time constant circuit including the resistor 21 and the capacitor 22. . The above is the details of the configuration of the phase shift circuit according to the present embodiment.

Next, the operation of the phase shift circuit will be described. First, the output current I1 of the current operational amplifier 12 is expressed by a time constant circuit comprising a resistor 21 and a capacitor 22 and a resistor 2
Divide into three. Here, the current IA flowing through the resistor 23 is obtained as follows. IA = (I1 / ((1 / (R1 + (1 / jωC1))) + (1 / R2))) (1 / R2) = I1 (1 + jωC1R1) / (1 + jωC1 (R1 + R2)) = 3I (1 + jωC1R1) / ( 1 + jωC1 (R1 + R2)) = 3I (1 + jωC1R1) / (1 + 3jωC1R1) (7) In the above equation (7), ω represents the angular frequency of the input current I.

On the other hand, the output current I 2 of the current operational amplifier 12
Is shunted to the capacitor 31 and the resistor 32. here,
The current IB flowing through the resistor 33 is obtained as follows. IB = (I2 / (jωC2 + (1 / R3))) (1 / R3) = I2 / (1 + jωC2R3) = − 2I / (1 + jωC2R3) (8)

Therefore, the output current IOUT of the phase shift circuit output from the output terminal 40 is as follows. IOUT = IA + IB = 3I (1 + j.omega.C1R1) / (1 + 3j.omega.C1R1) -2I / (1 + j.omega.C2R3) = I (1-3.omega.2C1C2R1R3 -j.omega. (3C1R1-3C2R3) / (1-3.omega.2C1R2C3R1) (A + jQ) (9)

However, in the above equation (9), A = 1-3ω2C1C2R1R3 (10) P = ω (3C1R1-3C2R3) (11) Q = ω (3C1R1 + C2R3) (12)

Then, a transfer function H between the input current I and the output current IOUT in the phase shift circuit is obtained from the equation (9) as follows. H = IOUT / I = (A-jP) / (A + jQ) (13)

Next, the phase shift amount θ of the phase shift circuit will be described. First, the phase shift amount θ can be obtained from the transfer function H shown in the above equation (13) as shown in the following equation. θ = arg (H) = − tan−1 P / A−tan−1 Q / A = θ1 + θ2 (14) where, in the above equation (14), θ1 = −tan−1P / A (15) θ2 = -Tan-1Q / A (16)

From the above equations (10) to (16), the manner of change of the phase shift amount θ when the angular frequency ω is changed from 0 to ∞ is as follows.

First, when the angular frequency ω is 0, A =
1, P = 0 and Q = 0. Accordingly, both θ1 and θ2 in the above equation (14) become 0, and the phase shift amount θ of the phase shift circuit becomes 0.

Next, when the angular frequency ω is 0, ω0 = 1 / √ (3
A case in which the distance is within the section up to C1C2R1R3) will be described. In this section, A changes from 1 to 0 as ω increases, and P and Q increase linearly from 0,
P / A and Q / A will change from 0 to ∞ as the angular frequency ω increases. Therefore, θ1 and θ2 are
In any case, the phase shift circuit changes from 0 to -π / 2 according to the increase of the angular frequency ω, and the phase shift amount θ of the phase shift circuit changes from 0 to -π.

Next, the case where the angular frequency ω is within the section from ω0 to ∞ will be described. In this section, A changes from 0 to −∞ with an increase in ω, and P and Q increase linearly, so that P / A and Q / A change from −∞ with an increase in the angular frequency ω. It will change to zero. . Therefore, in this section, both θ1 and θ2 change from −π / 2 to −π in accordance with the increase of the angular frequency ω, and the phase shift amount θ of the phase shift circuit changes from −π to −2π. Become.

As described above, according to the present embodiment, as shown in FIG. 3, a frequency characteristic in which the phase shift amount θ changes from 0 to −2π according to the change in frequency is obtained.

Next, the gain G of the phase shift circuit will be described. First, the gain G can be obtained from the transfer function H shown in the above equation (13) as shown in the following equation. G = | H | = | (A-jP) / (A + jQ) | = | A-jP | / | A + jQ | = √ (A2 + P2) / √ (A2 + Q2) (17)

P and Q in the above equation (17) are given by the above equations (11) and (12). In this embodiment, the time constant C2R3 is a value sufficiently smaller than the time constant C1R1. Therefore, P and Q may be considered to be substantially equal, and the gain G in the above equation (17) is 1 throughout the entire frequency band.

As described above, in the phase shift circuit according to the present embodiment, the output current IOUT whose phase is shifted in the range of 0 to -2π from the input signal by the frequency of the input signal.
Is obtained, and the gain between the input signal and the output current is maintained substantially constant throughout the entire frequency band.

[0045]

As described above, according to the present invention, the number of elements is smaller and the cost is lower than that of the conventional one, and
There is an effect that a phase shift circuit capable of phase shifting up to -2π is obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a phase shift circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a configuration example of a current operational amplifier according to the first embodiment.

FIG. 3 is a diagram showing a frequency characteristic of a phase shift amount in the embodiment.

FIG. 4 is a circuit diagram illustrating a configuration example of an all-pass filter.

FIG. 5 is a diagram showing a frequency characteristic of a phase shift amount of the all-pass filter.

FIG. 6 is a circuit diagram showing a configuration example of a conventional phase shift circuit in which all-pass filters are cascaded in two stages.

FIG. 7 is a diagram illustrating a frequency characteristic of a phase shift amount of the phase shift circuit.

[Explanation of symbols]

10 input terminal, 11 input resistance, 12 current operational amplifier (current output type operational amplifier), 21 first resistor, 22 first capacitor, 23 second resistor,
31 ... second capacitor, 32 ... third resistor, 40
…… Output terminal.

Claims (1)

(57) [Claims] 1. A phase shift circuit for shifting the phase of an input signal by an amount corresponding to the frequency of the input signal and outputting the shifted output signal from an output terminal, the first output current being proportional to the input signal and the first output being A current output type operational amplifier having a magnitude two thirds of the current and outputting a second output current having a phase opposite to that of the first output current, and a first resistor and a first capacitor connected in series A first time constant circuit that is connected to allow a part of the first output current to pass therethrough, and guides a current of the first output current that does not flow through the first time constant circuit to the output terminal. A resistor, wherein the first
A second resistor having a resistance value that is twice the resistance of the second output current, a second capacitor that allows a part of the second output current to pass through, and a second output current that does not flow through the second capacitor. A third resistor for guiding a current to the output terminal, wherein a time constant formed by the second capacitor and the third resistor is smaller than a time constant of the first time constant circuit. A phase shift circuit characterized by the following.