JP3166749B2 - Semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, as one of semiconductor devices, FIG.
9 and FIG. 20 are known. The semiconductor device includes a semiconductor substrate 101, a trench isolation film 102 formed on the semiconductor substrate 101, and a first local polysilicon pad for a word line 103 and a bit line formed on the trench isolation film 102. 104, a second local polysilicon pad 105 for a capacitor contact, the trench isolation film 102, the word line 103, the first local polysilicon pad 104, and an interlayer insulating film 106 formed on the second local polysilicon pad 105. And a contact hole 107 formed in the interlayer insulating film 106;
It has a contact member 108 formed in the contact hole 107 and a bit line 109 formed on the interlayer insulating film 106 so as to be connected to the upper surface of the first local polysilicon pad 105.

A method for manufacturing this semiconductor device will be described. As shown in FIGS. 20 and 21, a trench isolation film 102 is formed on a semiconductor substrate 101 and this trench isolation film 10 is formed.
After forming a word line 103, a first local polysilicon pad 104, and a second local polysilicon pad 105 on the semiconductor device 2, an interlayer insulating film having a thickness of 0.5 to 1.0 micrometers as shown in FIG. 106 is deposited. Next, as shown in FIG. 22, the interlayer insulating film 106 is flattened by CMP so that the film thickness of the interlayer insulating film 106 on the local polysilicon pad 107 becomes about 0.1 to 0.15 μm. Thereafter, as shown in FIG.
Is applied and exposure for forming the contact hole 107 is performed, and then the contact hole 107 in the cell is formed using the resist 110 as a mask. Contact hole 10
When performing the exposure for forming 7, for example, having a hole having a diameter of 0.2 micrometers in the cell,
A mask having a hole having a diameter of 0.25 micrometers in the peripheral circuit portion is used. This is for lowering the resistance of the contact member in the peripheral circuit portion than the resistance of the contact member in the cell. Thereafter, as shown in FIG. 19, a contact member 108 is formed in a contact hole 107, and the first local polysilicon pad 105 is formed.
A bit line 109 is formed on the interlayer insulating film 104 so as to be connected to the upper surface of the semiconductor device.

[0004]

However, in the conventional method of manufacturing a semiconductor device, when performing exposure for forming a contact hole, a hole having a small diameter is formed in a cell and a large diameter is formed in a peripheral circuit. Since a mask having holes is used, if the exposure amount is adjusted to the holes in the mask in the cell, overexposure occurs in the holes in the mask in the peripheral circuit portion, so that the diameter of the contact holes in the peripheral circuit portion becomes larger than a desired size, and There is a problem that it cannot be made according to dimensions. Further, in the conventional semiconductor device and the method of manufacturing the same, there is a problem that it is difficult to open a contact in the cell with miniaturization of the cell.

An object of the present invention is to provide a semiconductor device which can increase an exposure margin for forming a contact hole and does not need to form a fine contact hole in a cell, and a method of manufacturing the same. It is in.

[0006]

According to a first aspect of the present invention, there is provided a semiconductor substrate, a separation film formed on the semiconductor substrate, and a word line formed on the separation film. A first local conductive pad for a line and a bit line, a second local conductive pad for a capacitor contact having the same thickness as the first local conductive pad, a separation film and a word line. An interlayer insulating film formed so that the upper surfaces of the first local conductive pad and the second local conductive pad are exposed; a contact hole formed only in a peripheral circuit portion of the interlayer insulating film; and a contact hole formed in the contact hole It has a contact member of the peripheral circuit portion and a bit line formed on the interlayer insulating film so as to be connected to the contact member and connected to the upper surface of the first local conductive pad.

According to a second aspect of the present invention, there is provided a semiconductor substrate, an isolation film formed on the semiconductor substrate, a first local conductive pad for word lines and bit lines formed on the isolation film, A second local conductive pad for a capacitive contact having a thickness smaller than that of the first local conductive pad, and only an upper surface of the first local conductive pad formed on the isolation film, the word line and the second local conductive pad An interlayer insulating film formed so as to be exposed, a contact hole formed only in a peripheral circuit portion of the interlayer insulating film, a contact member of the peripheral circuit portion formed in the contact hole, and a first member connected to the contact member. A bit line formed on the interlayer insulating film so as to be connected to the upper surface of the local conductive pad.

According to a third aspect of the present invention, in the second aspect, the thickness of the first local conductive pad is larger than the thickness of the second local conductive pad by 0.05 to 0.1 micrometers. It is characterized by the following.

According to a fourth aspect of the present invention, a step of forming an isolation film on a semiconductor substrate, a first local conductive pad for a word line and a bit line on the isolation film, and a first local conductive pad Forming a second local conductive pad for a capacitive contact having the same thickness as that of the first conductive layer;
Depositing an interlayer insulating film on the first local conductive pad and the second local conductive pad, and flattening the interlayer insulating film until the upper surfaces of the first local conductive pad and the second local conductive pad are exposed Forming a contact hole only in the peripheral circuit portion of the interlayer insulating film; forming a contact member of the peripheral circuit portion in the contact hole, connecting the contact member to the contact member, and connecting to the upper surface of the first local conductive pad. Forming a bit line on the interlayer insulating film.

The invention according to claim 5 is a step of forming an isolation film on a semiconductor substrate, a first local conductive pad for a word line and a bit line on the isolation film, and a first local conductive pad. Forming a second local conductive pad for a capacitive contact having a smaller thickness, and depositing an interlayer insulating film on the isolation film, the word line, the first local conductive pad, and the second local conductive pad A step of flattening the interlayer insulating film until only the upper surface of the first local conductive pad is exposed; a step of forming a contact hole only in a peripheral circuit portion of the interlayer insulating film; Forming a bit line on the interlayer insulating film so as to form a member, connect to the contact member, and connect to the upper surface of the first local conductive pad.

According to a sixth aspect of the present invention, in the fifth aspect, the thickness of the first local conductive pad is larger than the thickness of the second local conductive pad by 0.05 to 0.1 micrometers. It is characterized by the following.

[0012]

Next, embodiments of the present invention will be described in detail with reference to the drawings. 1 and 2 show a semiconductor device as a first embodiment of the present invention. A semiconductor device according to a first embodiment of the present invention includes a semiconductor substrate 1, a trench isolation film 2 formed on the semiconductor substrate 1, and a word line 3 formed on the trench isolation film 2. A first local polysilicon pad 4 for a bit line, a second local polysilicon pad 5 for a capacitance contact, and a first local polysilicon pad 4 and a second local polysilicon pad 5 formed on the trench isolation film 2 and the word line 3. An interlayer insulating film 6 having an upper surface exposed, a contact hole 7 formed only in a peripheral circuit portion of the interlayer insulating film 6, and a contact member 8 of the peripheral circuit portion formed in the contact hole 7; And a bit line 9 formed on the interlayer insulating film 6 so as to be connected to the contact member 8 and connected to the upper surface of the first local polysilicon pad 4.

Next, a method of manufacturing the semiconductor device shown in FIGS. 1 and 2 will be described. First, as shown in FIGS. 3 and 4,
After forming the trench isolation film 2 on the semiconductor substrate 1,
On the trench isolation film 2, a first local polysilicon pad 4 for word lines 3 and bit lines and a second local polysilicon pad 5 for a capacitor contact having the same thickness as that of the first local polysilicon pad 4 are formed. Form. Next, as shown in FIG. 4, an interlayer having a thickness of 0.5 to 1.0 μm is formed on the trench isolation film 2, the word line 3, the first local polysilicon pad 4, and the second local polysilicon pad 5. An insulating film 6 is deposited. Next, as shown in FIG. 5 and FIG.
The interlayer insulating film 6 is planarized by CMP until the upper surfaces of the first local polysilicon pad 4 and the second local polysilicon pad 5 are exposed.

Next, as shown in FIG. 7, after a resist 10 is formed on the interlayer insulating film 6, exposure is performed, and then a contact hole 7 is formed only in a peripheral circuit portion of the interlayer insulating film 6 by etching. Next, as shown in FIG. 2, after removing the resist 10, the contact member 8 of the peripheral circuit portion is formed in the contact hole 7 and at the same time, the interlayer insulating film 6 is A bit line 9 is formed thereon. These contact members 8 and bit lines 9 are formed in the next step. First, a polysilicon film 11 having a thickness of about 400 to 800 angstroms is deposited on the entire surface of the interlayer insulating film 6, and then a thickness of about 0.1 to 0.15 micrometers is formed on the polysilicon film 11. Is deposited. Next, the wiring is exposed and etched.

Next, a semiconductor device according to a second embodiment of the present invention will be described in detail with reference to the drawings. In the second embodiment of the present invention, the same components as those in the first embodiment of the present invention are denoted by the same reference numerals. As shown in FIGS. 8 and 9, a semiconductor device according to a second embodiment of the present invention includes a semiconductor substrate 1, a trench isolation film 2 formed on the semiconductor substrate 1, and a trench isolation film 2. A first local poly-silicon pad 4 for word lines 3 and bit lines, a second local poly-silicon pad 5 for a capacitive contact having a smaller thickness than the first local poly-silicon pad 4, and a trench isolation film 2, an interlayer insulating film 6 formed on the word line 3 and the second local polysilicon pad 5 so that only the upper surface of the first local polysilicon pad 4 is exposed, and only a peripheral circuit portion of the interlayer insulating film 6 , A contact member 8 of a peripheral circuit portion formed in the contact hole 7, and connected to the contact member 8 and connected to the upper surface of the first local polysilicon pad 4. And a bit line formed on the interlayer insulating film 6 so that.

Next, a method of manufacturing the semiconductor device shown in FIGS. 8 and 9 will be described. First, as shown in FIGS. 10 and 11, a trench isolation film 2 is formed on a semiconductor substrate 1, and then a word line 3 is formed on the trench isolation film 2. Next, as shown in FIG. 11, a polysilicon film 13 having a thickness of 0.5 μm is deposited on the trench isolation film 2 and the word lines 3. Next, as shown in FIG. 11, after a resist 14 is formed on the polysilicon film 13 and is exposed, etching is performed. Next, as shown in FIG. 12, a resist 15 is formed again on the polysilicon film 13 and is exposed to light, followed by etching to perform the first local polysilicon pad 4 for bit lines and a thinner than the first local polysilicon pad. A second local polysilicon pad 5 for a capacitor contact having a thickness is formed. In this case, the first local polysilicon pad 4 and the second local polysilicon pad 5 are so arranged that the thickness of the first local polysilicon pad 4 is 0.05 to 0.1 μm thicker than the thickness of the second local polysilicon pad 5. To form

Next, as shown in FIG.
After the removal of the trenches 4 and 15, the trench isolation film 2, the word line 3 and the first local polysilicon pad 4 are formed as shown in FIG.
And a film thickness of 0.5 to 0.5 on the second local polysilicon pad 5
An interlayer insulating film 6 having a thickness of 1.0 μm is deposited. Next, as shown in FIGS. 15, 16 and 17,
The interlayer insulating film 6 is planarized by CMP until only the upper surface of the first local polysilicon pad 4 is exposed. Next, FIG.
As shown in FIG. 1, after forming a resist 16 on the interlayer insulating film 6, the resist 16 is exposed to light and then etched to form the interlayer insulating film 6.
Contact hole 7 is formed only in the peripheral circuit section of FIG. Next, as shown in FIGS. 8 and 9, after removing the resist 16, the contact member 8 of the peripheral circuit portion is formed in the contact hole 7 and at the same time, the first local polysilicon pad 4 is removed.
Bit line 9 on interlayer insulating film 6 so as to be connected to the upper surface of
To form These contact members 8 and bit lines 9 are formed in the next step. First, a polysilicon film 11 having a thickness of about 400 to 800 angstroms is deposited on the entire surface of the interlayer insulating film 6, and then a thickness of about 0.1 to 0.15 micrometers is formed on the polysilicon film 11. Is deposited. Next, the wiring is exposed and etched.

In the second embodiment of the present invention, only the upper surface of the first local polysilicon pad 4 for connecting the bit line is exposed when the interlayer insulating film 6 is flattened, so that the second local polysilicon pad 5 is connected to the other local polysilicon pad 5. There is an advantage that the short circuit can be reduced.

In the above embodiment, the bit line 9 may be formed separately from the contact member 8 after the contact member 8 is formed in the contact hole 7.

[0020]

According to the present invention, it is not necessary to simultaneously open the contact holes in the cells having different sizes and in the peripheral circuit portion, and it is sufficient to form the contact only in the peripheral circuit portion, thereby increasing the exposure margin of the contact hole. Can be done. Further, according to the present invention, since a wiring can be formed directly on the local polysilicon pad exposed when the interlayer insulating film is flattened, it is not necessary to form a fine contact hole in the cell.

[Brief description of the drawings]

FIG. 1 is a plan view showing a semiconductor device as a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating the semiconductor device of FIG. 1 cut along line AA ′.

FIG. 3 is a view for explaining steps of a method for manufacturing the semiconductor device of FIG. 1;

FIG. 4 is a view for explaining another step of the method for manufacturing the semiconductor device of FIG. 1;

FIG. 5 is a view for explaining another step of the method for manufacturing the semiconductor device of FIG. 1;

FIG. 6 is a view for explaining another step of the method for manufacturing the semiconductor device of FIG. 1;

FIG. 7 is a view for explaining another step of the method for manufacturing the semiconductor device of FIG. 1;

FIG. 8 is a plan view showing a semiconductor device as a second embodiment of the present invention.

9 is a cross-sectional view illustrating the semiconductor device of FIG. 8 cut along line BB ′.

10 is a view illustrating a step of a method of manufacturing the semiconductor device in FIG. 8;

FIG. 11 is a drawing for explaining another step of the method for manufacturing the semiconductor device of FIG. 8;

FIG. 12 is a drawing for explaining another step of the method for manufacturing the semiconductor device of FIG. 8;

FIG. 13 is a view for explaining another step of the method for manufacturing the semiconductor device of FIG. 8;

FIG. 14 is a drawing for explaining another step of the method for manufacturing the semiconductor device of FIG. 8;

FIG. 15 is a drawing for explaining another step of the method for manufacturing the semiconductor device of FIG. 8;

16 is a view for explaining another step of the method for manufacturing the semiconductor device of FIG. 8;

FIG. 17 is a view for explaining another step of the method for manufacturing the semiconductor device of FIG. 8;

FIG. 18 is a view for explaining another step of the method for manufacturing the semiconductor device of FIG. 8;

FIG. 19 is a sectional view showing a conventional semiconductor device.

20 is a view illustrating a step of a method of manufacturing the conventional semiconductor device of FIG. 19;

21 is a view for explaining another step of the method for manufacturing the conventional semiconductor device of FIG. 19;

FIG. 22 is a view illustrating another step of the method of manufacturing the conventional semiconductor device in FIG. 19;

FIG. 23 is a view for explaining another step of the method for manufacturing the conventional semiconductor device of FIG. 19;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor substrate 2 trench isolation film 3 word line 4 first local polysilicon pad 5 second local polysilicon pad 6 interlayer insulating film 7 contact hole 8 contact member 9 bit line 10 resist 11 polysilicon film 12 WSi film 13 polysilicon film 14 to 16 resist

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/108 H01L 21/762 H01L 21/8242

Claims (6)

(57) [Claims] A semiconductor substrate; an isolation film formed on the semiconductor substrate; a first local conductive pad for word lines and bit lines formed on the isolation film; A second local conductive pad for a capacitive contact having the same thickness as that of the local conductive pad; a first local conductive pad and the second local conductive formed on the isolation film and the word line; An interlayer insulating film formed so that an upper surface of the pad is exposed; a contact hole formed only in a peripheral circuit portion of the interlayer insulating film; a contact member of the peripheral circuit portion formed in the contact hole; A bit line formed on the interlayer insulating film so as to be connected to a member and connected to an upper surface of the first local conductive pad. 2. A semiconductor substrate, an isolation film formed on the semiconductor substrate, and first and second word lines and bit lines formed on the isolation film.
A local conductive pad, a second local conductive pad for a capacitive contact having a thickness smaller than that of the first local conductive pad, formed on the isolation film, the word line, and the second local conductive pad. The interlayer insulating film formed so that only the upper surface of the first local conductive pad is exposed; a contact hole formed only in a peripheral circuit portion of the interlayer insulating film; a peripheral circuit formed in the contact hole And a bit line formed on the interlayer insulating film so as to be connected to the contact member and connected to an upper surface of the first local conductive pad. 3. The semiconductor device according to claim 2, wherein
The semiconductor device according to claim 1, wherein a thickness of the first local conductive pad is larger than a thickness of the second local conductive pad by 0.05 to 0.1 micrometers. 4. A step of forming an isolation film on a semiconductor substrate, a first local conductive pad for word lines and bit lines on the isolation film, and a thickness of the first local conductive pad. Forming a second local conductive pad for a capacitor contact having the same thickness; and an interlayer insulating film on the isolation film, the word line, the first local conductive pad, and the second local conductive pad. Depositing; and flattening the interlayer insulating film until the upper surfaces of the first local conductive pad and the second local conductive pad are exposed; and contact holes only in peripheral circuit portions of the interlayer insulating film. Forming a contact member of a peripheral circuit portion in the contact hole and connecting the contact member to a bit line on the interlayer insulating film so as to be connected to an upper surface of the first local conductive pad. Forming a semiconductor device. 5. A step of forming an isolation film on a semiconductor substrate; a first local conductive pad for word lines and bit lines on the isolation film; and a thinner film thickness than the first local conductive pad Forming a second local conductive pad for a capacitive contact; and depositing an interlayer insulating film on the isolation film, the word line, the first local conductive pad, and the second local conductive pad. A step of flattening the interlayer insulating film until only an upper surface of the first local conductive pad is exposed; a step of forming a contact hole only in a peripheral circuit portion of the interlayer insulating film; Forming a contact member of the circuit portion and forming a bit line on the interlayer insulating film so as to be connected to the contact member and connected to an upper surface of the first local conductive pad. Manufacturing method of a semiconductor device. 6. The method of manufacturing a semiconductor device according to claim 5, wherein said first local conductive pad has a thickness of said second local conductive pad.
A method of manufacturing a semiconductor device, wherein the thickness is 0.05 to 0.1 micrometers thicker than the thickness of the local conductive pad.