JP3167167B2 - Spatial light receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spatial light receiver for converting a digital signal into an optical signal and receiving the demodulated signal.

[0002]

2. Description of the Related Art A speaker system using spatial light transmission will be described below as an example. Optical transmission has a fatal drawback in that when light is interrupted by a person crossing or the like, sound is cut off. Hereinafter, a conventional system which has solved this disadvantage will be described.

FIG. 3 is a diagram showing a configuration on the transmitting side.
a is an Lch analog input terminal, 101b is an Rch analog input terminal, 102 is an AD conversion circuit for converting an analog signal into a digital signal, 103 is a transmission signal processing circuit for converting audio data into a predetermined format, 104 is a modulation circuit, 105a and 105b
Is a light emitting element driver, and 106a and 106b are light emitting elements.

Next, the operation of the transmitting side will be described. The Lch and Rch audio analog signals input from the input terminals 101a and 101b are
Is converted into a digital signal by the transmission signal processing circuit 103.
Is converted to a predetermined transmission format.

FIG. 4 is a view showing an example of a transmission format, which is a format of the digital audio interface standard CP-340 of the Electronic Industries Association of Japan (EIAJ). In the figure, one frame is Lch of preamble B or M and Rch of W is preamble.
, And each sub-frame is composed of bits 0 to 31 of 3 bits.
It is composed of two bits.

The first four bits of each subframe are a synchronization preamble signal, which also serves as a channel identification signal and a synchronization signal of audio data transmitted in the subframe. Audio data is 20-bit DATA
Is transmitted using P is a parity for checking whether there is an error in bits 4 to 31. Hereinafter, description of other data in FIG. 4 will be omitted because the technique is a known technique.

The output of the transmission signal processing circuit 103 is modulated by a modulation circuit 104. The modulation signal 104a is converted into an optical signal by the light emitting element driver 105a and the light emitting element 106a and transmitted to the Lch speaker system. The modulated signal 104a is further converted into an optical signal by the light emitting element driver 105b and the light emitting element 106b and transmitted to the Rch speaker system.

FIG. 5 is a block diagram showing the configuration of a speaker system on the receiving side, where 200a is an Lch speaker system and 200b is an Rch speaker system. In the figure, 201a and 201b are light receiving elements, 20
2a and 202b are amplification circuits, 203a and 203b are adders, 204a and 204b are signal processing circuits, 205a and 2b.
05b denotes a DA conversion circuit, 206a and 206b denote power amplifiers, and 207a and 207b denote speakers.

Next, since the same operation is performed for the Lch and the Rch, the operation of the Lch speaker will be described here.
The light transmitted from the light emitting element 106a is received by the light receiving element 201a.
, And the light transmitted from the light emitting element 106b is received by the light receiving element 201b and converted into an electric signal. The received signal 202c amplified by the amplifier circuit 202a is Rc
The received signal 202d amplified by the amplifier circuit 202b of the h speaker system 200b is added by the adder 203a. The output of the adder 203a is subjected to demodulation and Lch digital audio signal extraction by a signal processing circuit 204a. The extracted Lch digital audio signal is D
After being converted into an analog signal by the A conversion circuit 205a, the power is amplified by the power amplifier 206a, and
7a is output as a sound.

In this loudspeaker system, even if one of the Lch and Rch loudspeakers is interrupted, the other optical signal can be received, thereby enabling normal stereo reproduction.

[0011]

Since the conventional device is configured as described above, if one optical signal is interrupted, only the noise is output from the interrupted channel amplifier. The output S / N of the amplifier is the output 202c of the amplifier.
Is lower than the S / N. When one of the light receiving elements is irradiated with the optical signal of the remote controller, the output signals 202c and 202 of the adders 203a and 203b of both channels are output.
Since the remote control signal is superimposed on d, there is a problem that normal sound is not output from both speakers.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and can perform normal stereo reproduction without deteriorating S / N even if one of the two optical signals is interrupted. It is an object of the present invention to obtain a spatial light receiving device capable of performing the following.

It is another object of the present invention to provide a spatial light receiver capable of reproducing a normal sound even when an optical signal from a remote controller is irradiated.

[0014]

A spatial light receiving apparatus according to the present invention selects and reproduces an error-free digital audio signal from digital audio signals extracted from optical signals received by Lch and Rch speaker systems, respectively. It is configured.

Further, as a clock for reproducing the selected digital audio signal, a clock synchronized with the selected digital audio signal is selected and generated by a PLL circuit which receives the clock.

[0016]

The spatial light receiving apparatus according to the present invention converts a received signal into a digital signal, judges the quality of the signal, and selects and reproduces one of the two received signals. No S / N degradation of the received signal is caused.

Further, since a clock for reproducing the selected digital audio signal is generated by the PLL circuit, stable processing can be performed.

Even if the remote control signal is incident on the light receiving element of one of the speaker systems, the signals of the two systems are not added.
Digital audio signals for ch can be reproduced.

[0019]

[Embodiment 1] An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a circuit configuration of a speaker system, wherein 1a is an Lch speaker system,
Reference numeral 1b denotes an Rch speaker system, and both 1a and 1b have the same circuit configuration. In the figure, 110 is a demodulator,
Reference numeral 51 denotes a reception signal extraction circuit which outputs Lch and Rch audio data 51a and a parity check result 51b of each subframe from the output signal of the demodulator 110. 5
Reference numeral 3 denotes an error determination circuit for performing an error determination of each word from a lock determination result 50a indicating whether the PLL state is locked or unlocked and a parity check result 51b. 52 denotes an error in the data reproduced by itself. A selection signal generation circuit that outputs "1" only when the error determination result of the signal received by the Rch speaker system 1b input from the terminal 66a is correct, and outputs "0"otherwise;
A selector 6 outputs an input A when the selection signal is "0", and outputs a B input when the selection signal is "1". Reference numeral 55 denotes a shift register with a parallel load function. Reference numeral 57 denotes a PLL circuit.

Reference numeral 59 denotes a switch circuit, which is a DA conversion circuit 11
A signal designating which of the two channels of data input to 2 is to be output, "0"
Lch when (GND), Rc when "1" (VDD)
h. When the switch circuit 59 is "0" as shown in the figure, this system becomes an Lch speaker system and "1".
In this case, an Rch speaker system is provided. 63 is a power amplifier, 64 is a speaker, 65a is a terminal for inputting audio data received by the Rch speaker system 1b,
A signal corresponding to 51a is input. Reference numeral 80 denotes a format circuit for converting a digital audio signal into a EIAJ standard format.

Reference numeral 66a denotes an Rch input from a terminal 65a.
It is an error determination result (signal corresponding to 53a) of audio data. 67a is an output terminal of the audio data 51a reproduced by the Lch speaker system 1a, and 68a is L
Error judgment result 5 of signal received by ch speaker system
An output terminal 3a and 69a are terminals (signals corresponding to 50b) for inputting a load clock of data input from the terminal 65a. 70a is an Lch speaker system 1b
Is an output terminal of the load clock of the data reproduced in step (1).
Note that 65b to 70b are terminals of the Rch speaker system 1b, and 65a to 70a of the Lch speaker system 1a.
81a is the formatting circuit 8
A terminal for outputting an output of 0, 81b is an output terminal of the Rch formatting circuit.

Next, the operation will be described with reference to the time chart of FIG. First, an operation when a light signal can be received normally will be described. The signal 110a demodulated at the timing shown in FIG. 2A is input to the received signal extraction circuit 51, and the time-division multiplexed Rch and Lch audio data 51a is output at the timing shown in FIG. The parity check result 51b of the subframe is output. In this case, since there is no error, the parity check result 51
“b” is output as “0”.

The error determination circuit 53 receives the lock determination result and the parity check result as input, determines that there is no error because the PLL is locked, and there is no error in the parity check result, and outputs "0". The output timing of the error determination circuit 53 is shown in FIG. In the figure, P _L1 indicates a judgment result for _L1 , and P _R1 indicates a judgment result for R1. This determination is performed for each subframe, that is, for each audio data word, and the error check result 53a is output. The selection signal generation circuit 52 outputs a signal 52a of “0” because the error determination circuit 53 outputs no error. Therefore, selectors 54 and 56 select input A.

The load clock 50b (FIG. 2E) output from the clock recovery circuit 111 is input to the PLL circuit 57 via the selector 56. The PLL circuit 57 generates a stable load clock 57a whose timing is almost the same as that of the load clock 50b but has little jitter, and also generates a timing signal to be supplied to the shift register 55, the DA converter 112, and the like. P
By selecting the time constant of the LL circuit 57, the stability of the clock can be easily increased.

The reproduced data 51a (FIG. 2)
(B)) shows the load clock 57 via the selector 54.
a (at substantially the same timing as in FIG. 2E), the data is parallel-loaded into the shift register 55 at the rising timing.
The serial signal 55a (FIG. 2F) is sent to the DA conversion circuit 112. Further, the serial signal 55a is converted to EIAJ formatted in formatting circuit 80, is output from the pin 8 1a.

The DA conversion circuit 112 outputs a channel signal specified by the switch circuit 59 using the channel identification signal. This signal is power-amplified by the amplifier 63 and drives the speaker 64. Although not shown, the data transfer clock of the shift register 55 and the DA
A clock for processing the signal selected by the selector 54, such as a clock required for the conversion circuit 112, is generated by the PLL circuit 57. As described above, the input signals of the terminals 66a, 65a, and 69a are not used in the state where the light can be normally received.

Next, an operation when an optical signal input to the Lch speaker system is interrupted will be described. FIG.
(G) shows the demodulated data 110a when the light is blocked,
This is an example of a case where data disappears during the demodulation of data R1 (time t1).

In this case, P in the clock recovery circuit 111
The LL circuit becomes unclocked, and the parity check result of the received signal also becomes erroneous, so that the error determination circuit 53 determines that there is an error. On the other hand, the optical signal input to the Rch speaker system 1b is correctly reproduced, and the signal input to the terminal 66a indicates no error. Therefore, the selection signal generation circuit 52 outputs a signal 52a of “1”. Since there is no received signal, the PLL circuit in the clock recovery circuit is in an unlocked state. Therefore, the timing of the output 53a (FIG. 2 (I)) of the error determination circuit 53 is shifted to the time t2, which is slightly shifted from the lock timing. Since a signal indicating an error is output and the selection circuits 54 and 56 select the input B at time t2, the Lch digital audio signal 51a (FIG.
The signal received by the Lch speaker system 1a is output up to L1 of (H)), but the signal received by the Rch speaker system 1b input from the terminal 69a (the timing is the same as in FIG. 2B) is output after R1. Output from the selector 54.

The input to the PLL circuit 57 is at time t.
Since the normal clock input from the terminal 69a is input after the second, the PLL circuit 57 does not lose its phase or lose its lock. The parallel output of the selector 54 is loaded into the shift register 55 with the load clock 57a, and is transferred to the DA conversion circuit 112 as a serial signal. FIG. 2M shows a period in which each word of two channels is transferred. Since correct data and a stable clock are always supplied to the DA conversion circuit 112, stereo reproduction can be performed without noise at the data switching point.

Although not shown, a configuration for performing DA conversion after passing through a digital filter is generally performed. The digital filter requires a clock having a frequency of 256 Fs or 512 Fs (Fs is a sampling frequency) for calculation, and a clock synchronized with data. When the clock generated by the clock recovery circuit 111 is supplied to a digital filter to be used as a master clock, when the clock is switched to the master clock of the Rch speaker system 1b, the phase does not match at the switching point, causing a malfunction and generating noise.

In this embodiment, since the PLL circuit 57 generates various clocks for processing the digital audio signal selected by the selector 54, such as an operation clock, there is no inconvenience as described above. PLL circuit 5
By increasing the time constant of 7, the stability of the clock can be increased.

[0032]

As described above, according to the present invention, when an optical signal transmitted by time-division multiplexing a two-channel digital signal is received by two speaker systems and one of the received signals has an error, Since the received signal received by the other speaker is reproduced, the two channels can be reproduced without sound interruption even if one optical signal is not received. Moreover, since signals are exchanged between the speaker systems using digital signals, the S / N ratio does not deteriorate.

Further, since a clock synchronized with the received signal having no error is selected and the clock is generated by the PLL circuit using the clock as an input signal, a stable clock can be supplied and noise-free reproduction can be performed.

Further, even if the remote control signal is applied to the light receiving element of one of the speaker systems, the signal of the other speaker system is not affected, and the erroneous signal is replaced with the signal received by the other speaker system. There is an effect that a spatial light receiving device with high reliability which does not occur can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a receiving-side circuit of a spatial light receiving device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of this embodiment.

FIG. 3 is a block diagram showing a configuration of a transmission side circuit of a conventional spatial light receiving device.

FIG. 4 is a diagram illustrating a configuration of a transmission signal.

FIG. 5 is a block diagram showing a configuration of a receiving side circuit of the conventional spatial light receiving device.

[Explanation of symbols]

 Reference Signs List 51 received signal extraction circuit 53 error determination circuit 54 selection circuit 56 selection circuit 57 PLL circuit 66 input terminal of error determination result 69 input terminal of reference signal 80 formatting circuit 111 clock recovery circuit 201 light receiving element

Continuation of front page (56) References JP-A-3-96022 (JP, A) JP-A-2-71626 (JP, A) JP-A-2-292920 (JP, A) JP-A-4-297140 (JP) , A) JP-A-5-7183 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04B 1/10 H04B 10/10 H04B 10/22 H04R 27/00

Claims (4)

(57) [Claims] 1. A digital signal of a plurality of channels is multiplexed, converted into a predetermined format, converted into an optical signal, and optical signals transmitted in at least first and second directions are individually received. The digital signals extracted from these electrical signals are converted to electrical signals, and the presence or absence of errors is determined. If an error is detected, the signal is transmitted to the other direction without error.
Select the digital signal extracted from the optical signal, the spatial light receiving device configured to output into an analog signal, clock recovery for generating a first reference signal synchronized with the digital signal issued extracted Means and in the other direction
Input means for inputting a second reference signal synchronized with a digital signal extracted from the transmitted optical signal ; selecting means for selecting one of the input first and second reference signals; A first PLL having an output of the selection means as an input
And a reference signal synchronized with the error-free digital signal is input to a first PLL circuit, and a signal of an error-free digital signal selected using a clock generated by the first PLL circuit. A spatial light receiving device having a configuration for performing processing. 2. The clock recovery circuit according to claim 1, wherein the clock recovery circuit has a second PLL circuit, the means for extracting a signal has error detection means, and the error determination means has a lock state of the second PLL circuit and a reception state. A spatial light receiving apparatus characterized in that the presence or absence of an error is determined from a signal error detection result. 3. A digital signal of a plurality of channels is multiplexed, converted into a predetermined format, converted into an optical signal, and optical signals transmitted in at least the first and second directions are individually received. The digital signals extracted from these electrical signals are converted to electrical signals, and the presence or absence of errors is determined. If an error is detected, the signal is transmitted to the other direction without error.
In the spatial optical receiver that is configured to select and output a digital signal extracted from the optical signal, a clock recovery means for generating a first reference signal synchronized with the digital signal issued extracted, the other direction Input means for inputting a second reference signal synchronized with a digital signal extracted from the optical signal transmitted to the first and second reference signals, and an error-free signal among the input first and second reference signals. Selecting means for selecting the one synchronized with the digital signal, a first PLL circuit receiving an output of the selecting means as an input, and a formatting circuit for converting the selected digital signal into a predetermined format;
A spatial light receiving device, wherein the formatting circuit is operated using a clock generated by the first PLL circuit. 4. The clock recovery circuit according to claim 2, wherein the clock recovery circuit has a second PLL circuit, the means for extracting a signal has error detection means, and the error determination means has a lock state of the second PLL circuit and a reception state. A spatial light receiving apparatus characterized in that the presence or absence of an error is determined from a signal error detection result.