JP3167280B2 - Delay circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit for delaying an analog signal formed by a semiconductor device.

[0002]

2. Description of the Related Art An example of a delay circuit which can delay an analog signal, is composed of semiconductor elements, is easy to be integrated into a LSI, and can cope with a low power supply voltage is disclosed in Japanese Patent Laid-Open No. 5-3 / 1993.
A circuit as shown in FIG. 5 which is disclosed in Japanese Patent Application Laid-Open No. 08-247 is known.

In FIG. 5, if the current value of the current source I501 is I _O1 and the emitter resistance of the transistor Q501 is re, re is given by (Equation 1).

[0004]

(Equation 1)

[0005] than (Equation 1), re is understood that it is possible to control the current value I _O1 of the current source I 501. Next, assuming that the current amplification factor hfe of the transistor Q501 is sufficiently large and the stray capacitance of the circuit is sufficiently small,
Transfer function H from input terminal 501 to output terminal 502
(Ω) is represented by (Equation 2).

[0006]

(Equation 2)

Further, the resistance value of the first resistor R501 and the resistance value of the second resistor
The resistance value of the resistor R502 is equal to that of the first capacitor C50.
When the capacitance value of the first capacitor C502 is equal to the capacitance value of the second capacitor C502, the expression (2) can be reduced, which simplifies the operation.

Assuming that R ₂ = R ₁ = R and C ₁ = C ₂ = C, the transfer function H (jω) from the input terminal 501 to the output terminal 502 is given by (Equation 3).

[0009]

(Equation 3)

FIGS. 6 (a) and 6 (b) explain the frequency characteristics of (Equation 3). (Equation 3) is a special case of (Equation 2), but well represents the features of the conventional example. The amplitude characteristic G (ω) of (Equation 3) is (Equation 4).

[0011]

(Equation 4)

The group delay characteristic Td (ω) is given by (Equation 5).

[0013]

(Equation 5)

Note that the delay time Tdo in the low band is represented by (Equation 6).

[0015]

(Equation 6)

FIG. 6 (a) shows the amplitude characteristic G (ω) obtained by approximating the amplitude characteristic G (ω) by a polygonal line using a logarithmic representation in the vertical and horizontal axes.
FIG. 6B illustrates the group delay characteristic Td (ω) in logarithmic representation only on the horizontal axis. 6A and 6B, the horizontal axis (frequency axis) is normalized, and the numerical value is ωRC
Is the value of And each characteristic is re = R / 2
And the case where re is doubled and halved.

From FIG. 6A, the amplitude characteristic is represented by re = R /
It can be seen that when the value is 2, the high region is flat, when re <R / 2, the high region is lifted, and when re> R / 2, the high region is attenuated. Also, from FIG. 6B, the low-band delay time is re
= R / 2, 2RC, re <R / 2, decrease, re
> R / 2, the frequency characteristic is
It can be seen that the flat band narrows when ω = 0.1 / RC, and when re increases and the delay time increases, the flat band narrows.

6 (a) and 6 (b), since the flat region of the amplitude characteristic is sufficiently wider than the flat region of the delay time with respect to the change of re, the circuit of FIG. Just pay attention.

FIG. 7 shows an NPN delay circuit 721 constructed using the NPN transistors shown in FIG. 5 and a PPN transistor constructed using PNP transistors of the opposite conductivity type.
This shows a delay circuit in which an NP-type delay circuit 722 is connected in series and configured as a unit circuit.

As shown in FIG. 7, the reason why an NPN type delay circuit 721 and a PNP type delay circuit 722 using NPN type and PNP type transistors are connected in series is that the input terminal 501
This is to make the DC potentials of the power supply and the output terminal 502 equal to each other, and to effectively utilize the dynamic range of the power supply voltage.

In FIG. 7, if the current values of the current sources I701 and I702 are I _O1 and I _O2 , respectively, and I _O1 and I _O2 are equal, the emitter resistance r of the transistors Q701 and Q702 is
e become equal, and these re can be controlled by the current values I _O1 and I _O2 of the current sources I701 and I702 as shown by (Equation 1).

Next, as in FIG.
1 and Q702 have sufficiently large current amplification factors hfe, and
The stray capacitance of the circuit is assumed to be sufficiently small, and the resistance R7
01, R702, R704, and R705 have the same resistance value and the capacitors C701, C702, C703, and C704 have the same capacitance value, the input terminal 701 to the output terminal 7
The transfer function H (ω) up to 02 is represented by (Equation 7).

[0023]

(Equation 7)

Further, when the delay time Td (ω) is obtained from (Equation 7), it becomes (Equation 8).

[0025]

(Equation 8)

The delay time Tdo in the low frequency band is given by (Equation 9)
Indicated by

[0027]

(Equation 9)

The current values I _O1 and I _O1 of the current sources I701 and I702,
Since re changes by controlling I _O2 , the circuit of FIG. 7 can control the delay times Td and Tdo. Also, as in FIG. 5, FIG. 7 has an all-pass characteristic when re = R / 2.

In FIG. 7, transistors Q701 and Q702
If the base-emitter voltages are equal, the input terminal 70
1 and the DC potential of the output terminal 702 become equal, so that a dynamic range can be ensured even when multiple stages are connected with a low power supply voltage, and a large delay can be obtained.

When this circuit is built in an IC, N
The difference between the characteristics of the PN-type and PNP-type transistors and the variation of each transistor causes a difference in the input / output voltage of the unit delay circuit, thereby limiting the dynamic range. The variation in the output voltage increases as the number of stages increases. However, this can be corrected by adding a circuit that controls the ratio between the current value I _O1 of the current source I 701 of the NPN delay circuit 721 and the current value I _O2 of the current source I 702 of the PNP delay circuit 722. it can.

[0031]

However, in the conventional delay circuit as described above, as can be seen from FIGS. 6A and 6B, the band of the circuit is determined by the product of RC.
Since both the amplitude characteristic and the group delay characteristic become the flattest at re = R / 2, the current values I _O1 and I _{O2 of} the current sources that determine the value of re are also limited in a certain range. On the other hand, since various loads such as stray capacitances are applied to the actual circuit, depending on the amplitude and frequency of the input signal, the drive capacity of the circuit is insufficient due to the limitation of the current value of the current source. This may cause deterioration of high frequency characteristics.

In particular, in the case of the unit delay circuit shown in FIG. 7, the current source current I _O1
The base-emitter voltage difference between the NPN transistor and the PNP transistor is corrected by controlling the ratio between the current and the current source current I _O2 . Due to the correction, the respective current source currents I _O1 and I _O2 have considerable variation, and N
The frequency characteristics and the delay amount of the PN delay circuit 721 and the PNP delay circuit 722 may have variations and secondary distortions that affect the use, and may cause insufficient driving capability due to insufficient current source current. .

The present invention solves the above-mentioned problems. An NPN-type delay circuit and a PN
Provided is a delay circuit that can prevent variations in characteristics between P-type delay circuits and variations in DC transmission characteristics, and can enhance driving capability without affecting characteristics as a delay circuit.

[0034]

To solve the above problems, a delay circuit according to the present invention comprises an NPN transistor and a PNP transistor.
When correcting the variation of the input / output voltage when the base-emitter voltage of the transistor varies, the relative current between the circuit current of the NPN delay circuit and the circuit current of the PNP delay circuit is corrected. It is characterized in that the variation of the circuit current with respect to the variation of the inter-voltage is reduced as much as possible.

As described above, N for the variation of each element
Variations in characteristics between the PN-type delay circuit and the PNP-type delay circuit and variations in DC transmission characteristics can be prevented, and the driving capability can be enhanced without affecting the characteristics of the delay circuit.

[0036]

A delay circuit according to a first embodiment of the present invention has a base connected to an input terminal, an emitter connected to one end of a third resistor, and a collector connected to a second reference potential via a second resistor. A first transistor of one conductivity type connected to the point and one end of the second capacitor; a base connected to one end of the first resistor and one end of the second capacitor; an emitter connected to one end of the sixth resistor; Fifth
A first reference potential point and a second transistor of the opposite conductivity type connected to one end of the fourth capacitor via the third resistor.
One end of the resistor is connected to a first reference potential point via a first current source, one end of the first resistor and a first or second reference potential point via a first capacitor, One end of the resistor of 6,
The second reference potential point is connected to one end of the fourth resistor via the second current source and the first or second reference potential point via the third capacitor. One end of the fourth capacitor is connected to serve as an output terminal, and each of the above elements is controlled by controlling the relative value of the current value of the first current source and the current value of the second current source to form the base of the first transistor. The sum of the emitter-to-emitter voltage and the voltage drop at the third resistor due to the current of the first current source and the sixth resistor due to the base-emitter voltage of the second transistor and the current of the second current source; Are equalized to compensate for the DC potential difference between the input terminal and the output terminal.

A delay circuit according to a second aspect uses the configuration according to the first aspect as a basic delay circuit, and the basic delay circuit includes n
The stages are connected in series (n is a positive integer of 1 or more).
The delay circuit according to claim 3, wherein the base is connected to the input terminal, the emitter is connected to one end of the third resistor, and the collector is connected to the second reference potential point and one end of the second capacitor via the second resistor. A first transistor of one conductivity type, a base connected to one end of a first resistor and one end of a second capacitor, an emitter connected to one end of a sixth resistor, and a collector connected to the first resistor via a fifth resistor. A second transistor of a reverse conductivity type connected to a reference potential point and one end of a fourth capacitor is provided, and one end of a third resistor is connected to one end of a first resistor via one end of a seventh resistor and the first capacitor. Connected to a second reference potential point, one end of a seventh resistor is connected to the first reference potential point and one end of the first resistor via a first current source,
One end of the sixth resistor is connected to one end of the eighth resistor and the first or second reference potential point via the third capacitor,
Is connected to a second reference potential point potential and one end of a fourth resistor via a second current source, and one end of the fourth resistor is connected to one end of a fourth capacitor to output. Terminal, and controls each element by controlling the relative value between the current value of the first current source and the current value of the second current source, thereby setting the base-emitter voltage of the first transistor and the current value of the first current source. The sum of the voltage drop at the third resistor and the seventh resistor due to the current, the base-emitter voltage of the second transistor and the current at the sixth resistor and the eighth resistor due to the current of the second current source. Equalize the sum with the voltage drop,
The DC potential difference between the input terminal and the output terminal is configured to be compensated.

According to a fourth aspect of the present invention, the delay circuit according to the third aspect is a basic delay circuit, and the basic delay circuit is n
The stages are connected in series (n is a positive integer of 1 or more).
According to these configurations, the NPN transistor and the PNP
When correcting the variation of the input / output voltage when the base-emitter voltage of the transistor varies, the relative current between the circuit current of the NPN delay circuit and the circuit current of the PNP delay circuit is corrected. The variation of the circuit current with respect to the variation of the inter-voltage is reduced as much as possible.

Hereinafter, a delay circuit according to an embodiment of the present invention will be specifically described with reference to the drawings. (Embodiment 1) A delay circuit according to Embodiment 1 of the present invention will be described.

FIG. 1 is a circuit diagram showing a configuration of the delay circuit according to the present embodiment. In the delay circuit of the present embodiment, as shown in the circuit diagram of FIG. 1, the base is at the input terminal 101, the emitter is at one end of the third resistor R103, and the collector is at the second resistor R103.
A first terminal of one conductivity type connected to a power supply terminal 103 serving as a second reference potential point and one end of a second capacitor C102 via the second reference potential point
Transistor (for example, NPN transistor) Q1
01 and one end of the third resistor R103 are connected to the first current source I
101, a first reference potential point, ground, one end of a first resistor R101, and a power supply end 103 via a first capacitor C101. A base is connected to one end of the first resistor R101 and a second end of the first resistor R101. A second transistor of an opposite conductivity type, having an emitter connected to one end of a sixth resistor R106, an emitter connected to one end of a sixth resistor R106, and a collector connected to the ground and one end of a fourth capacitor C104 via a fifth resistor R105. For example, a PNP transistor Q102), one end of a sixth resistor R106 is connected to the power supply terminal 3 via a second current source I102, one end of a fourth resistor R104, and a ground via a third capacitor C103. Is connected to one end of the fourth resistor R104 and the fourth capacitor C1.
04 is connected to one end and used as an output terminal 102.

This circuit shows a unit circuit of a delay circuit in which a configuration using an NPN transistor and a configuration using a PNP transistor of the opposite conductivity type are connected in series, and a pair of the configuration is used.

As described above, the delay circuit 121 using an NPN transistor (hereinafter referred to as an NPN delay circuit) 121 and the delay circuit using a PNP transistor (hereinafter referred to as a PNP transistor)
The reason for connecting the series delay circuits 122 in series is to make the DC potentials of the input terminal 101 and the output terminal 102 equal so as to effectively utilize the dynamic range of the power supply voltage.

The operation of the delay circuit configured as described above will be described below. First, a description will be given using the NPN delay circuit 121 of FIG. A DC voltage Vcc is applied to the power supply terminal 103, and the input terminal 101
It is assumed that a DC bias voltage V1 at which the transistors Q101 and Q102 can operate is applied. Current source I101
Is expressed as I _O1 and the emitter resistance of the transistor Q101 is expressed as re.

[0044]

(Equation 10)

(Equation 10) shows that re can be controlled by the current value I _O1 of the current source I 101. Here, assuming that Re = re + R ₃ (R ₃ is the resistance value of the resistor R103), the current amplification factor hfe of the transistor Q101 is sufficiently large, and the stray capacitance of the circuit is sufficiently small, the input terminal 101 and the transistor Q102 Transfer function H (ω) to base (= NPN delay circuit 121)
Is represented by (Equation 11).

[0046]

[Equation 11]

The condition that (Equation 11) indicates the all-pass characteristic is as follows.
The numerator is {1-jω} (R₁ R_Two C ₁ C_Two )｝ × ｛1+
jω√ (R₁ R_Two C₁ C_Two )｝, So the denominator is
{1 + jω} (R₁ R_Two C₁ C_Two )｝^Two If
You. That is, R_Two = 2Re, R₁ C_Two + ReC₁ + R
eC_Two = 2√ (R₁ R_Two C₁ C_Two ), (Equation 11) is
Shows all-pass characteristics.

Here, the ratio of R ₂ and R ₁ is a, C ₁ , C ₂
Where b is the ratio of R, ie, R ₂ = aR ₁ and C ₁ = bC ₂ , the following equation is obtained.

[0049]

(Equation 12)

From the above, a and b satisfy a certain condition,
When Re = R _2/2, (Formula 11) is found to exhibit all-pass characteristics. In particular, when a = 1 and b = 1, that is,
When the resistance value of the first resistor R101 is equal to the resistance value of the second resistor R102, and the capacitance value of the first capacitor C101 is equal to the capacitance value of the second capacitor C102, (Equation 11) is approximately Can be easy.

Assuming that R ₂ = R ₁ = R and C ₁ = C ₂ = C, the transfer function H (jω) from the input terminal 101 to the output terminal 102 becomes (Equation 13).

[0052]

(Equation 13)

FIGS. 2A and 2B illustrate the frequency characteristics of (Equation 13). (Equation 13) is a special case of (Equation 11), but well illustrates the characteristics of the delay circuit of the present embodiment.

The amplitude characteristic G (ω) of (Equation 13) is expressed by (Equation 1)
4).

[0055]

[Equation 14]

The group delay characteristic Td (ω) is given by (Equation 15)
Becomes

[0057]

(Equation 15)

Note that the delay time Tdo in the low frequency band is given by (Equation 1)
6).

[0059]

(Equation 16)

FIG. 2A illustrates the amplitude characteristic G (ω) by polygonal approximation in the vertical and horizontal axis co-logarithmic representation. FIG. 2B shows the group delay characteristic Td (ω) in logarithmic representation only on the horizontal axis. In FIGS. 2A and 2B,
The horizontal axis (frequency axis) is normalized and the numerical value is the value of ωRC. The respective characteristics are obtained when Re = R / 2 and when Re is doubled and halved.

From FIG. 2A, the amplitude characteristic is expressed as Re = R / 2.
It can be seen that when is higher, the higher region is flat, when Re <R / 2, the higher region is lifted, and when Re> R / 2, the higher region is attenuated. From FIG. 2B, the low-frequency delay time is expressed as Re = R
/ 2, 2RC, Re <R / 2, decrease, Re> R
/ 2, the frequency characteristic increases.
It can be seen that the flat band is narrowed to 0.1 / RC, and when Re becomes large and the delay time increases, the flat band becomes narrow.

When comparing FIGS. 2A and 2B, the flat region of the amplitude characteristic is sufficiently wider than the flat region of the delay time with respect to the change of Re. It is only necessary to pay attention to the characteristic band.

Note that if the more general characteristic of (Equation 11) substantially satisfies the condition of (Equation 12), the value of Re is close to R / 2 and the values of FIGS. ) Is almost equal to the characteristic shown in FIG.

As described above, the NPN delay circuit 121 shown in FIG.
Has the characteristics of a delay circuit, and the Re can be controlled by the current value _IO1 . Therefore, the transfer function H (ω)
Can be controlled, and the delay time Td (ω) and Tdo can be controlled.

Further, if the variable range of re is set near Re = R / 2, the amplitude characteristic of the NPN type delay circuit 121 in FIG. 1 can obtain a constant characteristic up to a high band. Further, since it is Re = re + R _3, relative to the conventional circuit, the variable range of Re by current I _O1 (= variable range of the delay time) has become smaller, maintaining the same characteristics as the conventional circuit Mom the value of re it is possible to reduce by the amount of R _3, correspondingly, can flow a large amount of current source current I _O1. As a result, the amplitude of the input signal is large,
It is possible to eliminate the drive capacity shortage when the frequency is high.

Similarly, the NPN delay circuit 121 and the PNP
Also in the unit delay circuit in which the type delay circuits 122 are connected in series, if the current values I _O1 and I _{O2 of} the current sources I101 and I102 are equal, the emitter resistances re of the transistors Q101 and Q102 become equal, and these re are ( Equation 1
As shown by 0), control can be performed by the current values I _O1 and I _O2 of the current sources I101 and I102.

Current increase of transistors Q101 and Q102
The width ratio hfe is sufficiently large and the stray capacitance of the circuit is sufficient
And the resistance values of R103 and R106 are equal.
Re = re + R_Three (Re is the transistor Q101
The emitter resistance of Q102, R _Three Is for R103 and R106
Resistance value), and furthermore, resistors R101, R102, R1
03 and R104 have the same resistance value, and the capacitances C101 and C1
Assuming that the capacitance values of 02, C103, and C104 are equal,
Transfer function H from input terminal 101 to output terminal 102
(Ω) is represented by (Equation 17).

[0068]

[Equation 17]

From equation (17), the delay time Td (ω)
Is obtained as (Equation 18).

[0070]

(Equation 18)

Further, the delay time Tdo in the low frequency band is given by (Equation 1)
9).

[0072]

[Equation 19]

The current values I _O1 and I _O1 of the current sources I101 and I102,
Since Re changes by controlling I _O2 , the circuit of FIG. 1 can control the delay times Td and Tdo. Also, R
When e = R / 2, all-pass characteristics are obtained.

The potential point connecting the capacitors C101 and C103 may be either the ground or the power supply terminal 103. Next, when the unit delay circuits of FIG. 1 are connected in multiple stages in order to obtain a large delay, the multi-stage connection circuit is a repetition of the basic circuit, so that the mask design is easy and the degree of integration is improved. Thus, a configuration suitable for IC integration can be obtained.

Further, since the delay circuit is composed of a simple circuit based on PNP and NPN transistors, the number of elements is relatively small, and the delay circuit can be realized without using much current. , The dynamic range can be widened.

When the delay circuit of this embodiment is built in an IC, a difference occurs in the input / output voltage of the unit delay circuit due to a difference in characteristics between the NPN type transistor and the PNP type transistor and a variation in each transistor. Limit the dynamic range. The variation in the output voltage increases as the number of stages increases. However, this means that the ratio of the current value I _O1 of the current source I 101 of the NPN delay circuit 121 to the current value I _O2 of the current source I 102 of the PNP delay circuit 122 is
The correction can be made by performing control using a circuit that performs control so as to satisfy the relationship of (Equation 20).

[0077]

(Equation 20)

Further, V _BE1 and I _O1 and V _BE2 and I _O2 have
There is a relationship as shown in equations (Equation 21) and (Equation 22).

[0079]

(Equation 21)

[0080]

(Equation 22)

Assuming that I _S1 and I _S2 vary, V _BE1 + R
_If V _BE2 + R ₆ · I _O2 is larger than ₃ · I _O1 , then V
I _O2 is reduced in order to reduce the _BE2. Then, similarly, R ₆ · I _O2 also decreases at the same time, and as a result, V
_BE1, the conventional method had done V _BE2 only correction of the dropout voltage of the delay circuit, the variation of I _O1 and I _O2 is smaller.

From (Equation 20), (Equation 21), and (Equation 22), the relationship between I _S1 and I _S2 and the variation between I _O1 and I _O2 is as shown in (Equation 23).

[0083]

(Equation 23)

FIG. 3 illustrates (Equation 23). In FIG. 3, the horizontal axis is an NPN transistor and a PNP.
The variance of the V _BE of the transistor (I _S2 / I _S1 ) and the vertical axis represent the variance of the current value of the current source (I _O2 / I _O1 ) for correcting the variation of the V _BE . Therefore, the illustrated (Equation 2)
3) The more steep the slope of the line, the more V _BE1 and V _BE2
That is, the variation of I _O1 and I _{O2 with} respect to the variation of the above is large.

In FIG. 3, kT / q (approximately 26
The ratio (H) of the magnitude of the voltage drop of R ₃ · I _O1 to mV) is used as a variable factor. (When there is no R ₃₎ when H = 0, the slope indicating the variation of I _O1 and I _O2 for variations of I _S1 and I _S2 is 1, which is the maximum. As H increases, the slope indicating the variation between I _O1 and I _O2 decreases.

Therefore, if the voltage drop of R ₃ · I _O1 is made large within the range of the size of Re with respect to R and the size of the variable range of the delay circuit, the NPN-type transistor can be used to compensate for differences in transistor characteristics and individual variations. Variations in performance between the delay circuit and the PNP-type delay circuit can be suppressed, and insufficient driving capability of the circuit can be eliminated. (Embodiment 2) A delay circuit according to Embodiment 2 of the present invention will be described.

FIG. 4 is a circuit diagram showing a configuration of the delay circuit according to the present embodiment. In the delay circuit of this embodiment, as shown in the circuit diagram of FIG. 4, the base is connected to the input terminal 401, the emitter is connected to one end of the third resistor R403, and the collector is connected to the second resistor R403.
A first transistor of one conductivity type (for example, an NPN transistor) Q connected to a power supply terminal 403 serving as a second reference potential point and one end of a second capacitor C402 via a second reference potential point 402
401 and one end of the third resistor R403 are connected to the seventh resistor R403.
407 and the power supply terminal 40 via the first capacitor C401.
3 and one end of a seventh resistor R407 is connected to one end of a first resistor R408 via a first current source I401.
, The base is connected to one end of the first resistor R408 and one end of the second capacitor C402, the emitter is connected to one end of the sixth resistor R406, and the collector is connected to the fifth terminal.
A second transistor (for example, a PNP transistor) Q402 connected to the ground and one end of the fourth capacitor C404 via the resistor R405, and one end of the sixth resistor R406 is connected to the eighth resistor R406. Is connected to ground via a third capacitor C403 and one end of an eighth resistor R409 is connected to a power supply terminal 403 and one end of a fourth resistor R410 via a second current source I402. , One end of the fourth resistor R410 and one end of the fourth capacitor C404 are connected to form an output terminal 402.

As in FIG. 1, this delay circuit is an NPN-type delay circuit 421 constructed using NPN-type transistors.
And a PNP-type delay circuit 422 composed of PNP-type transistors of the opposite conductivity type connected in series to form a unit circuit of a pair of delay circuits.

The operation of the delay circuit configured as described above will be described below. First, a description will be given using the NPN delay circuit 421 in FIG. NP of Embodiment 1
Similarly to the N-type delay circuit 121, it can be seen that re can be varied by the current value I _O1 of the current source I401.

Here, Re = re + R ₃ (R ₃ is a resistance R
Resistance of _{403), R = R 7 +} R 8 (R 7, R 8 is R4
07, R408) and the transistor Q401
Is sufficiently large and the stray capacitance of the circuit is sufficiently small, the transfer function H (ω) (= N) from the input terminal 401 to the base of the transistor Q402 is assumed.
The transfer function of the PN delay circuit is expressed by (Equation 24).

[0091]

(Equation 24)

Here, when comparing (Equation 11) and (Equation 24), the resistance values of R407 and R408 are expressed as R (= R
₇ + R ₈ ) = R ₁ , the circuit of FIG. 4 exhibits the same amplitude characteristics and group delay characteristics as the circuit of FIG. 1, and functions as a delay circuit equivalent to the delay circuit of FIG. You can see that.

Also, for the PNP delay circuit 422, R ₄ = R ₉ + R ₁₀ (where R ₄ is R1 in FIG. 1).
04, R ₉ : R409 resistance, R ₁₀ : R41
The resistance value is 0. ), The circuit of FIG. 4 shows the same amplitude characteristics and group delay characteristics as the delay circuit of FIG.

When the delay circuit of this embodiment is incorporated in an IC, similar to the circuit of FIG. 1, the difference in characteristics between the NPN type and PNP type transistors and the variation of each transistor cause the unit delay circuit There is a difference in input / output voltage,
Limit the dynamic range. The variation in the output voltage increases as the number of stages increases. However, this is the current value of the current source I 401 I _O1 and the current source I40
The ratio of the two current values I _O2 can be corrected by controlling the ratio so as to satisfy the relationship of (Equation 25).

[0095]

(Equation 25)

Further, V _BE1 and I _O1 , and V _BE2 and I _O2 have the relations as shown in (Equation 26) and (Equation 27), respectively.

[0097]

(Equation 26)

[0098]

[Equation 27]

As in the first embodiment, (Equation 25) and (Equation 25)
26) and (Equation 27), I_S1, I _S2And I_O1, I_O2No ba
The variation relationship is as shown in (Equation 28).

[0100]

[Equation 28]

From (Equation 23) and (Equation 28) and FIG. 3, FIG.
In the configuration of FIG. 1, since H can be selected to be large while maintaining the amplitude characteristic and the group delay characteristic similarly to the configuration of FIG. 1, the variation of I _O1 and I _O2 with respect to the variation of I _S1 and I _S2. The condition can be further reduced.

Therefore, (R ₃ + R ₇ ) · R (R ₃ + R ₇ ) ・
If the voltage drop of I _O1 is increased, an NPN-type delay circuit and P
Variations in performance of the NP-type delay circuit can be suppressed, and insufficient driving capability of the circuit can be eliminated.

[0103]

As described above, according to the present invention, the variation in the input / output voltage when the base-emitter voltage of the NPN transistor and the PNP transistor varies is described.
When correcting by changing the relative value of the circuit current of the NPN-type delay circuit and the circuit current of the PNP-type delay circuit, the variation of the circuit current with respect to the variation of the base-emitter voltage can be reduced as much as possible.

Therefore, the NP with respect to the variation of each element
Variations in characteristics between the N-type delay circuit and the PNP-type delay circuit and variations in DC transmission characteristics can be prevented, and the driving capability can be enhanced without affecting the characteristics of the delay circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a delay circuit according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of a frequency characteristic according to the first embodiment;

FIG. 3 is an explanatory diagram of an improvement effect of the first embodiment.

FIG. 4 is a circuit diagram showing a configuration of a delay circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a conventional NPN type delay circuit.

FIG. 6 is an explanatory diagram of frequency characteristics of the conventional example.

FIG. 7 is a unit circuit diagram using the conventional delay circuit.

[Description of References] Q101, Q401 NPN transistor Q102, Q402 PNP transistor I101, I102, I401, I402 Current source R101-R106, R402-R410 Resistance C101-C104, C401-C404 Capacitor 101, 401 Input terminal 102, 402 Output terminal 103, 403 Power supply terminal 121, 421 NPN type delay circuit 122, 422 PNP type delay circuit

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03H 11/26

Claims (4)

(57) [Claims] 1. A one-conductivity-type one in which a base is connected to an input terminal, an emitter is connected to one end of a third resistor, and a collector is connected to a second reference potential point and one end of a second capacitor via a second resistor. First
, A base at one end of the first resistor and one end of the second capacitor, an emitter at one end of the sixth resistor, and a collector at the first reference potential point and the fourth resistor via the fifth resistor. A second transistor of the opposite conductivity type connected to one end of the capacitor is provided, and one end of the third resistor is connected to the first reference potential point, one end of the first resistor, and the first resistor via the first current source. And one end of the sixth resistor is connected to the second reference potential point and the fourth reference potential point via the second current source.
And one end of the fourth resistor and one end of the fourth capacitor are connected to one end of the fourth resistor and the first or second reference potential point via the third capacitor to form an output terminal. Is controlled by controlling the relative value of the current value of the first current source and the current value of the second current source, and the third resistance by the base-emitter voltage of the first transistor and the current of the first current source. , And the sum of the voltage between the base and the emitter of the second transistor and the voltage drop at the sixth resistor due to the current of the second current source are equalized. A delay circuit configured to compensate for a potential difference. 2. The basic delay circuit according to claim 1, wherein said basic delay circuit has n stages (n is a positive integer of 1 or more).
A delay circuit connected in series. 3. A one-conductivity type having a base connected to an input terminal, an emitter connected to one end of a third resistor, and a collector connected to a second reference potential point and one end of a second capacitor via a second resistor. First
, A base at one end of the first resistor and one end of the second capacitor, an emitter at one end of the sixth resistor, and a collector at the first reference potential point and the fourth resistor via the fifth resistor. A second transistor of the opposite conductivity type connected to one end of the capacitor, and one end of the third resistor connected to one end of the seventh resistor and the first or second reference potential point via the first capacitor; Connect to
One end of the seventh resistor is connected to the first reference potential point and one end of the first resistor via the first current source, and one end of the sixth resistor is connected to one end of the eighth resistor and the first resistor. 3 is connected to the first or second reference potential point via the third capacitor, and one end of the eighth resistor is connected to the second reference potential point potential via the second current source.
And one end of a fourth resistor is connected to one end of a fourth capacitor to serve as an output terminal, and each of the elements is connected to a current value of a first current source and a current value of a second current source. Controlling the relative value of the first transistor, the sum of the base-emitter voltage of the first transistor, the voltage drop at the third and seventh resistors due to the current of the first current source, and the second transistor Configured to equalize the sum of the base-emitter voltage and the voltage drop at the sixth resistor and the eighth resistor due to the current of the second current source to compensate for the DC potential difference between the input terminal and the output terminal. circuit. 4. The basic delay circuit according to claim 3, wherein said basic delay circuit has n stages (n is a positive integer of 1 or more).
A delay circuit connected in series.