JP3169604B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a high-speed diode, in which the off-angle of a semiconductor substrate is set in a range of 3 to 5 degrees,
The present invention relates to a semiconductor device capable of suppressing an increase in a forward voltage and obtaining good reverse recovery characteristics.

[Conventional technology]

FIG. 1 shows an example of a conventional high-speed diode element having a planar structure.

Epitaxial growth on N + type silicon substrate 1
A silicon region 2 is formed. Here, a P + type silicon region 3 is formed, and an electrode metal layer 5 is
Then, the electrode metal layer 6 is formed on the lower N + type silicon substrate. Note that lifetime killer diffusion of Au, Pt, electron beam, and the like was performed in the vicinity of the Pn junction in order to compensate for a decrease in switching speed due to accumulation of injected carriers in the Pn junction.

The reverse recovery characteristic (current waveform at the time of reverse recovery of the diode shown in FIG. 2) of the high-speed diode having the planar structure manufactured by such a method is the peak current I _rp at the time of reverse recovery.
And the di / dt at the time of reverse recovery becomes a steep characteristic, which is a problem.

Even in the conventional planar type high-speed diode,
Means for reducing the peak current at the time of reverse recovery can be reduced by lowering the concentration of the P + type silicon region 3 in FIG. 1, but the forward voltage increases as the number of accumulated carriers decreases. The soft recovery of di / dt at the time of reverse recovery depends on the lifetime of the N-type silicon region 2 shown in FIG. 1, and the soft recovery of di / dt is possible to some extent by reducing the lifetime. However, the forward voltage tends to increase as the lifetime decreases.

In any of the conventional high-speed diodes having a planar structure, there is a negative trade-off between the reverse recovery characteristic and the forward voltage, and it has been difficult to improve the characteristics of both without contradicting each other.

Japanese Patent Application Laid-Open No. S59-115566 discloses a technical example of a low-loss semiconductor rectifying element in which an increase in forward voltage is suppressed.

[Problems to be solved by the invention]

Therefore, an object of the present invention is to suppress an increase in the forward voltage,
And peak current reduction during reverse recovery and di / dt during reverse recovery
It is an object of the present invention to provide a semiconductor device capable of obtaining good reverse recovery characteristics such as soft recovery of a semiconductor device.

[Means for solving the problem]

In order to achieve the above object, an N + silicon substrate having a changed plane orientation, which is a feature of the present invention, is used to suppress an increase in forward voltage and to reduce a peak current at the time of reverse recovery. An N-type silicon region is formed.

In addition, reduction of peak current during reverse recovery and di during reverse recovery
In order to achieve a soft recovery of / dt, a deep junction P + layer and a shallow junction and low concentration P layer are alternately arranged at appropriate intervals in the N-type silicon region.

[Action]

The semiconductor device provided by the present invention has a structure in which a deep junction P + layer and a shallow junction and a low-concentration P layer are alternately arranged at an appropriate interval. Form silicon region, N + / N
Since the junction is sharpened, an increase in the forward voltage can be suppressed, and good reverse recovery characteristics can be obtained.

〔Example〕

An embodiment of the present invention will be described below with reference to a longitudinal sectional view of the high-speed diode shown in FIG.

An N-type silicon region 2 is formed by epitaxial growth on a slicing N + -type silicon substrate 1 having a crystal main surface of (100) and a tilt angle (4 degrees) with respect to a tilt direction <010>. In this N-type silicon region, a deep junction P + type silicon region 3 and a shallow junction and low concentration P-type silicon region 4 are formed.
Are formed alternately at appropriate intervals, an Al metal layer 6 is formed using an opening in the oxide film 5, and then a chromium metal layer 7 is formed on the lower N + silicon substrate 1. Then, an electron beam is irradiated for the purpose of compensating for a decrease in the switching speed.

The peak current at the time of reverse recovery occurs at the moment when a reverse voltage is applied to the Pn junction. That is, since the space charge region occurs at the moment when it tries to expand from the Pn junction, the accumulated carriers near the Pn junction,
That is, if the amount of holes injected from the P layer to the N layer is reduced, the peak current at the time of reverse recovery can be reduced. Therefore, in the semiconductor device provided by the present invention, a shallow junction and a low-concentration P layer 4 are formed at appropriate intervals.

In addition, since the deep junction P + layer 3 and the above-described shallow junction and low-concentration P layer 4 are alternately arranged, as shown in FIG.
A region a having a large layer thickness and a region b having a small N layer thickness are formed. When a reverse voltage is applied to the Pn junction, the carriers in the region b where the N layer thickness is small decrease sharply, but the carriers existing in the region a where the N layer thickness is large are larger than those in the region where the N layer thickness is small. Also diminishes slowly with a delay, so that di / dt during reverse recovery is a soft recovery characteristic.

FIG. 5 shows a comparison of current waveforms at the time of reverse recovery between the device manufactured according to the present embodiment and a conventional high-speed diode device having a planar structure. A shows the current waveform at the time of reverse recovery of the device manufactured according to the present embodiment. It can be seen that the peak current at the time of reverse recovery is smaller than that of B of the conventional device, and di / dt is soft recovery. .

In the above, when the shallow junction and the concentration of the P layer are reduced,
Since the number of accumulated carriers decreases, the forward voltage tends to increase. Therefore, in order to suppress an increase in the forward voltage, N-type silicon is formed by epitaxial growth on an N + silicon substrate having a changed plane orientation, which is a feature of the present invention, and the N + / N junction is sharpened.

FIG. 4B shows a concentration profile of an N + / N junction when N-type silicon is formed by epitaxial growth on an N + silicon substrate whose plane orientation is not changed, wherein A is an N + silicon substrate whose plane orientation is changed according to the present invention. This is the case where N-type silicon is formed by epitaxial growth on
It can be seen that the / N junction is sharp. Due to the steepness of the N + / N junction, the injection efficiency of electrons is increased, the accumulated carriers as an internal total can be secured, and an increase in the forward voltage can be suppressed.

Further, since the N + / N junction is made steeper, when a reverse voltage is applied to the Pn junction, the number of residual carriers inside the N layer that recombine with holes injected from the P layer is reduced. The peak current at the time is significantly reduced.

FIG. 6 shows a change in the peak current value at the time of the reverse recovery when the off angle (slicing angle) of the N + silicon substrate is changed which is a feature of the present invention. As is apparent from FIG. 6, by setting the off angle of the N + silicon substrate in the range of 3 ° to 5 °, it is possible to perform the reverse recovery compared to the case where the plane orientation is not changed (the substrate off angle is 0 °). Can be reduced to about 1/3. Therefore, it is possible to provide a semiconductor device which suppresses an increase in forward voltage and has good reverse recovery characteristics.

The steepness of the N + / N junction is a method that can be realized by means such as N + / N wafer bonding.

〔The invention's effect〕

According to the present invention, there is an effect that an increase in the forward voltage can be suppressed, a peak current during reverse recovery can be reduced, and di / dt during reverse recovery can be soft-recovered.

[Brief description of the drawings]

1 is a longitudinal sectional view of a conventional high-speed diode having a planar structure, FIG. 2 is a current waveform diagram at the time of reverse recovery of the diode, FIG. 3 is a longitudinal sectional view of a high-speed diode of one embodiment of the present invention, FIG. 4 is a concentration profile diagram showing the N + / N junction of the semiconductor device of the present invention and the conventional semiconductor device in comparison with each other, and FIG. FIG. 6 is a characteristic chart showing a change in peak current value at the time of reverse recovery when the substrate off-angle is changed in the semiconductor device of the present invention. 1 ... semiconductor substrate, 2 ... epitaxial layer, 3 ... P
+ Layer, 4 ... P layer, 6,7 ... metal layer.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Hiromi Hosoya 3-1-1, Sachimachi, Hitachi City, Ibaraki Pref. Hitachi, Ltd. Hitachi Plant (56) References 50-43884 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/861

Claims (1)

(57) [Claims] 1. A silicon substrate having a crystal main surface of (100) and having an off angle in a range of 3 to 5 degrees in a <010> direction, and a silicon substrate formed on the silicon substrate and A silicon region having the same conductivity type and a lower concentration than the silicon substrate; a silicon region having a conductivity type opposite to that of the silicon region and having a deep junction formed on the silicon region; A diode characterized by having a shallow junction and a low-concentration silicon region of the opposite conductivity type alternately arranged.