JP3174608B2 - Linear interpolation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a linear interpolation system for linearly interpolating an analog signal sampled at regular intervals and converting the analog signal into a continuous analog signal.

[0002]

2. Description of the Related Art A waveform obtained by sampling an analog signal at a constant interval by a sample and hold circuit changes discontinuously in a stepwise manner at each sampling time. Many of the output signals of the DA conversion circuit have the same waveform. Such a waveform rises quickly and contains high frequency components.

When a signal that changes discontinuously as described above is used as a control signal for an analog circuit, the control output signal changes discontinuously, and the output becomes unstable if the response speed of the control circuit is not sufficient. Undesirable phenomena may occur. In addition, a signal in a voice band has many high-frequency components, which makes the sound hard to hear. In order to avoid the above-described problem, a triangular waveform in which values at each sample point are continuously connected by a line segment is usually used. This waveform is obtained from a linear interpolation circuit that calculates the difference between sample values at adjacent sample points and integrates the difference at each sample interval.

FIG. 7 is a diagram showing a conventional linear interpolation circuit on which the present invention is based, and FIG. 8 is a time chart showing the operation of the conventional linear interpolation circuit shown in FIG. In FIG. 7, 11 is a sampler, 12 is a sample and hold circuit, 13 is a delay circuit, 14 is a subtraction circuit, and 15 is an integration circuit. Also, in FIG. 8, is a sample point, is an output C of the sample and hold circuit 12, is a delay circuit 13.
D is the input E of the integration circuit 15 and the integration circuit 1
5 is a time chart showing an output F of 5;
FIG. 3 is a diagram in which the output F of the integrating circuit 15 and the output C of the sample-and-hold circuit 12 are overlaid.

Next, using the time chart of FIG.
The operation of the linear interpolation circuit shown in FIG. 7 will be described. In FIG. 7, the sampler 11 samples the analog signal shown by the waveform A in FIG. 7 at the sample period T shown in FIG. 8, and generates the sample output shown by the waveform B in FIG.

The sample-and-hold circuit 12 holds the sample signal B, which is the output of the sampler 11, for each sample period and converts it into a step-like waveform C shown in FIG. The delay circuit 13 delays the output C of the sample and hold circuit 12 by one sample period, and generates a signal D shown in FIG. The subtraction circuit 14 subtracts the output signal C of the sample-and-hold circuit 12 and the output signal D of the delay circuit 13 and changes the magnitude E of the signal during one sample period (FIG. 8).
Solid line). That is, as shown in FIG.
The input signal VN-1 at the time of the sample period N-1 is obtained by the delay circuit 13, and the calculation shown by the following equation is performed by the subtraction circuit 14.
The difference ΔVN of N is obtained (k in FIG.
1).

ΔVN = k (VN−VN−1) The integrating circuit 15 integrates the output E of the subtracting circuit 14 and generates an output F signal shown by a dotted line in FIG. Here, the output F of the integration circuit 15 rises (or decreases) with a slope proportional to the input E of the integration circuit 15, and the slope of the output F is the output VN of the sample-and-hold circuit 12 in the sample period.
If the difference between the output VN-1 of the sample-and-hold circuit 12 one sample cycle before is ΔVN, then ΔVN / τ.
(Τ is an integration constant. In FIG. 8, since τ = T, the slope of the output EN (t) of the integration circuit 15 is ΔVN / T
Becomes). The amount by which the output F of the integration circuit 15 increases (or decreases) during each sample period is proportional to the input E of the integration circuit 15 and is proportional to the length of the sample period T.

Therefore, if the sample period is T,
At the sample point N + 1, since t = T, the integration circuit 1
5 where the output EN (t) changes during each sample period.
N is given by the following equation (in FIG. 8, since τ = T, ΔEN
= ΔVN). .DELTA.EN = EN (T) =. DELTA.VN.times.T / .tau. = K (VN-VN-1) .times.T / .tau. That is, as shown in FIG. The output C is integrated, and a signal having a triangular waveform shown in FIG. 8 in which the values at the sample points are connected by a line segment is output.

In practice, the output of the integrating circuit is not constant depending on the initial state. Therefore, by making the operation of the integration circuit slightly incomplete (for example, connecting a high resistance to the capacitor of the integration circuit in parallel), the average value of the output signal can be fixed to a constant value. By the way, the above linear interpolation circuit has a problem that when the sampling interval is changed, the amplitude of the output signal changes.

Next, this point will be described with reference to the time chart of FIG. The figure shows a sample and hold circuit 1
2 is a time chart when the output period of the sample and hold circuit 12 is the same and the sample period is set to 2T.
Represents the input E of the integration circuit 15 and the integration circuit 15
Is shown.

As is apparent from FIG. 9, when the magnitude of the output of the sample-and-hold circuit 12 (FIG. 9) is the same as that of FIG. 8, the output E of the subtraction circuit 14 (the input of the integration circuit of FIG. 9). Since the magnitude of E) does not change, the integration circuit 15
Of the output F is the same as that in FIG. On the other hand, the output F of the integration circuit 15 increases in proportion to the length of the sample period. In the case of FIG. 9, the sample period is twice that of FIG. The amplitude increases twice as compared with the case of FIG.

That is, the amplitude of the output of the linear interpolation circuit,
Assuming that the ratio of the change in the input is a gain, increasing the sample period increases the gain of the linear interpolation circuit, and shortening the sample period decreases the gain, contrary to the above case. As described above, the conventional linear interpolation circuit has a drawback that if the length of the sample period is changed, the gain of the linear interpolation circuit also changes.

[0013]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the prior art, and has been made in consideration of the above problem. The purpose is to provide.

[0014]

In order to solve the above-mentioned problems, the present invention is configured as shown in FIG. 1. According to the first aspect of the present invention, an input signal is sampled at a constant period. A sample-and-hold circuit 2 that generates an output that changes discontinuously in a stepwise manner by holding the previous sample value until the next sample time, and a delay that delays the output of the sample-and-hold circuit 2 by one sample period. A circuit 3, a subtraction circuit 4 for obtaining a change in the output of the sample-and-hold circuit 2 by obtaining a difference between outputs of the delay circuit 3 and the sample-and-hold circuit 2, and an integration circuit 6 for integrating the output of the subtraction circuit 4 with the door, a signal that changes discontinuously stepwise, in the linear interpolation method to convert to their respective sample point triangular signal connecting with line segments, depending on the sample period, stepped From varying signal, triangular signal
Compensation means 7 for changing the conversion gain when converting to a signal
Is provided.

[0015] and, by the gain compensation means 7, also I by the change of the sample period, from the signal that changes in a stepwise manner, the three
Compensation is performed so that the conversion gain at the time of conversion into an angular wave signal is constant . The invention of claim 2 of the present invention compensates for a change in gain by making the time constant of the integration circuit 6 variable, and the invention of claim 3 provides the subtraction circuit 4
Is made variable to compensate for the change in gain.

Further, in the invention of claim 4, a variable gain circuit 5 is separately added as means for compensating for a change in gain.

[0017]

The sample-and-hold circuit 2 generates an output that changes discontinuously in a stepwise manner by holding an input signal sampled at a constant period until the next sampling time. The output signal of the sample-and-hold circuit 2 that changes in a stepwise manner is delayed by one sample period by the delay circuit 3.
The subtraction circuit 4 obtains a difference between the output of the delay circuit 3 and the sample and hold circuit 2 to obtain a change in the output of the sample and hold circuit 2. The integration circuit 6 integrates the output of the subtraction circuit 4 and converts the signal that changes stepwise into a triangular-wave signal that connects each sampling point with a line segment.

When the sampling period changes, the slope of the output of the integration circuit 6 is constant and the integration time changes, so that the amplitude of the output of the integration circuit, that is, the gain changes. The gain compensating means 7 changes the time constant of the integrating circuit, the gain of the subtracting circuit, or the gain of a separately added gain variable circuit or the like according to the sampling period to compensate for the change in gain.

[0019]

2 and 3 show a first and a second embodiment of the present invention. The first and second embodiments of the present invention are embodiments in which the integration time constant of the integration circuit 15 shown in FIG. 7 is changed according to the sample period to compensate for a change in gain due to the sample period. FIG. 3 shows an embodiment of the integration circuit 15 for changing the integration time constant.

In the first embodiment shown in FIG. 2, OP1 is an operational amplifier, C1 is a capacitor, R1 to RN are resistors,
S1 is a switch. In the figure, an operational amplifier OP
Numeral 1 denotes an integrating circuit constituted by a capacitor C1 provided in a feedback circuit and resistors R1 to RN provided in an input circuit. The switch S1 is a switch that is switched by means such as a relay or a changeover switch, and switches the resistors R1 to RN in accordance with the sampling period to change the integration time constant.

In the figure, the integration time constant τ of the integration circuit is represented by the following equation (1) (C is the capacitance of the capacitor C1, and R is the resistance of the resistors R1 to RN). τ = CR (1) The output voltage Vo of the integrating circuit is expressed by the following equation (2) with respect to the input voltage Vi (if the initial state is ignored).

Vo = −Vi × t / τ (2) Therefore, in the first embodiment shown in FIG. 2, in order for the gain of the linear interpolation circuit to be constant with respect to the change of the sampling period, , The integration time constant τ is set to the sampling period T
Should be changed so that τ / T = constant. In the above embodiment, the value of the input resistors R1 to RN of the integration circuit is switched by the switch S1, but, for example, when the number of switching of the integration time constant is large or the integration time constant is to be changed continuously. in case of,
As a means for changing the input resistance of the integrating circuit, a means for continuously changing the resistance value such as a variable resistor can be used.

In the above embodiment, the switch S
1, the values of the input resistors R1 to RN of the integration circuit are switched. In addition, for example, by providing a plurality of capacitors of the integration circuit and switching the capacitors by switches, the integration time constant can be similarly changed. . In the second embodiment of the present invention shown in FIG. 3, the same components as those in FIG. 2 are denoted by the same reference numerals, and DA1 is a multiplying DA converter.

In FIG. 3, the operational amplifier OP1 forms an integrating circuit by a capacitor C1 provided in a feedback circuit and a multiplying DA converter DA1 provided in an input circuit. The DA converter DA1 is a current output type multiplication type DA converter, and its configuration is shown in FIG. In FIG. 4, a dotted line in the figure indicates a DA converter, and a digital input is applied to terminals T1 to T6 and a terminal VREF
Is applied with a reference voltage, and an output is obtained from terminals OUT1 and OUT2. It should be noted that the drawing shows output terminals OUT1, OUT
2 shows an example in which an operational amplifier 0P2 having a capacitor is connected to a feedback circuit.

In the DA converter shown in FIG. 1, a resistor R is connected in a ladder network type, and a changeover switch SD1 is provided by a digital input signal applied to terminals T1 to T6.
To SD6, and outputs an analog signal corresponding to the digital signal supplied to the terminals T1 to T6 to the output terminal O.
UT1 and OUT2 are obtained, and the input current supplied from the terminal VREF is binary-weighted by an R-2R ladder network as shown in the figure, and the output terminal OUT1 or the output terminal is output by the changeover switches SD1 to SD6. It flows to the terminal OUT2.

When the logic of the digital input applied to the terminals T1 to T6 is 1, the current flowing to the resistor 2R flows to the output terminal OUT1, and when the digital input is logic 0, the current flowing to the resistor 2R is the output terminal OUT1. OUT2. Therefore, assuming that the output terminals OUT1 and OUT2 are at the ground potential, the input resistance seen from the terminal VREF is constant regardless of the switching positions of the changeover switches SD1 to SD6.

The output current i of the multiplying D / A converter as described above is obtained by changing the externally applied reference voltages to VREF and DREF.
Is a digital signal and an integer of 0 ≦ D <2 ^N , and r is a constant of a ladder resistance in the DA converter. In general, an N-bit DA converter is represented by the following equation (3). i = VREF × (D / 2 ^N ) / r (3) Accordingly, the relationship between the input voltage Vi and the output current i of the DA converter is given by the following equation (4).

Vi / i = r × 2 ^N / D (4) In FIG. 3, the terminal VREF of the DA converter shown in FIG.
Is connected to the point E in FIG. 3, and the output terminal O shown in FIG.
UT1 and OUT2 are respectively the operational amplifier OP of FIG.
1 input and ground. In the integration circuit shown in FIG.
Since the converter is connected and the ratio between the input voltage Vi and the output current i shown in the above equation (4) corresponds to the value of the input resistance that determines the integration time constant, it is necessary to change the digital control data D supplied from the outside. As a result, Vi / i can be changed, and the time constant of the integration circuit can be changed.

Then, if R is set as in the following equation (5), R = Vi / i = r × 2 ^N / D (5) Since the integration time constant τ becomes the equation (6), τ = CR = Cr × 2 ^N / D (6) The output ΔEN of the integrating circuit is given by the following equation (7).

ΔEN = k (VN−VN−1) × T × D / Cr × 2 ^N (7) Therefore, the digital control data D is stored in the sample period T
By defining the following equation (8),
The gain of the linear interpolation circuit can be made constant with respect to the sample period. T × D = constant (8) As a disadvantage of the embodiment using the DA converter, in general, the constant r of the ladder resistance widely varies in an inexpensive DA converter (about 1/2 to 2 times the standard value). , The integration time constant can be controlled relatively, but not enough to control with absolute accuracy.
For this reason, in the case of the present embodiment, it is necessary to provide an adjustment unit for individually calibrating the value of the integration time constant for each DA converter.

According to the first and second embodiments of the present invention described above, as the integration circuit 15 shown in FIG. 7, an integration circuit capable of changing the integration time constant τ according to the change of the sample period. Is used, for example, as shown in FIG.
As shown in FIG. 9, when the sampling period is doubled, the integration time constant τ is doubled, and the output F of the integration circuit 15 in FIG.
Can be halved. Therefore, as shown in FIG. 9, even if the sampling period is doubled, the gain can be made the same as in FIG.

FIG. 5 is a diagram showing a third embodiment of the present invention. In the third embodiment of the present invention, the subtraction circuit 14 shown in FIG.
Is changed in accordance with the sample period to compensate for the change in gain due to the sample period. FIG. 5 shows an embodiment of the subtraction circuit 15. In FIG.
OP3 is an operational amplifier, RF1 to RFN, R1 to RN and RI1 and RI2 are resistors, and S1 and S2 are switches.

In the third embodiment of the present invention shown in the figure, an operational amplifier OP3 is provided with a resistor RF provided in a feedback circuit.
1 to RFN and the resistors R1 to RN and RI1 and RI2 provided in the input circuit constitute a differential amplifier, and output the difference between the input terminals C and D to the output terminal E. The switches S1 and S2 are switches that are switched by means such as a relay or a changeover switch that operates in conjunction with each other.
1 to RFN and resistors R1 to RN,
Change the gain of the differential amplifier.

In the subtraction circuit shown in FIG.
Is the input voltage of the input terminal D, Vi1 is the input voltage of the input terminal D, and k is the gain of the differential amplifier.
Is represented by the following equation (9). Vo = k (Vi1−Vi2) (9) The gain k of the differential amplifier is determined by the resistance RF provided in the feedback circuit.
The output voltage Vo is determined by the ratio of the two input signals (Vi1 to VN1), which is determined by the ratio of the four input resistors RF1 to RFN and the resistors R1 to RN and RI1 and RI2 provided in the input circuit.
To change the gain k in proportion to -Vi2), it is necessary to change at least two resistors (the resistors RF1 to RFN and the resistors R1 to RN).

For this reason, the switches S1 and S2 shown in FIG.
Switches the resistors RF1 to RFN and the resistors R1 to RN in conjunction with each other to change the gain k of the differential amplifier.
That is, by setting the gain k of the differential amplifier with respect to the sample period T as in the following equation (10), the gain of the linear interpolation circuit can be made constant with respect to the sample period.

T × k = constant (10) As described above, according to the present embodiment, since the gain of the subtraction circuit 14 shown in FIG. 7 can be changed according to the sampling period T, the linear interpolation circuit Can be kept constant even if the sampling period T changes. In the above embodiment, the number of resistors to be switched is twice as large as that in the embodiment shown in FIG.

In the fourth embodiment of the present invention, a variable gain circuit is separately provided in the linear interpolation circuit shown in FIG. 7, and the gain is changed according to the sample period to compensate for the change in gain due to the sample period. For example, FIG. 6 shows one embodiment of the variable gain circuit. 6, OP4 is an operational amplifier, DA2 is a multiplying DA converter shown in FIG. 4, and RF1 is a resistor. The operational amplifier OP4 forms a variable gain circuit by a resistor RF1 provided in a feedback circuit and a multiplying DA converter DA2 provided in an input circuit.

The DA converter DA2 is a current input type multiplying DA converter shown in FIG. 4. As in the case shown in FIG. 3, the terminal VREF of the DA converter is connected to the point E1 in FIG. , The output terminal OUT1 shown in FIG.
And OUT2 are connected to the input terminal and ground of the operational amplifier OP4 of FIG. 6, respectively. In the present embodiment, the variable gain circuit of FIG. 6 is desirably provided between the subtraction circuit 14 and the integration circuit 15 in FIG. 7, but the output side of the integration circuit 15 or the input side of the sample-and-hold circuit 12 is also provided. , On the output side.

In FIG. 6, since the output current i of the DA converter DA2 is represented by the above-mentioned equation (3), the resistance RF
1 is R, and the input voltage of the DA converter DA2 is V
Assuming that i, the output voltage Vo of the operational amplifier OP4 is expressed by the following equation (11). Vo = −R × i = −Vi × (R / r) × (D / 2 ^N ) (11) As described above, the value of the ladder resistance of the DA converter varies, but the feedback resistance RF of the operational amplifier OP4.
By using a resistor (a resistor having one end connected to the output terminal OUT1 and the other end output as an external terminal in FIG. 4) built in the DA converter DA2 as 1, the variation in the value of the ladder resistance is offset. be able to.

That is, since the resistor built in the DA converter is manufactured under the same conditions as the ladder resistor, the variation between the built-in resistor and the ladder resistor is very small, and the ladder resistance value from the standard value is small. The deviation can be offset by the deviation of the internal resistance value from the standard value. Since the resistance value of the resistor built in the DA converter is equal to the constant r of the ladder resistance in the DA converter, when the resistor built in the DA converter DA2 is used as the feedback resistor RF1, the output voltage of the operational amplifier OP4 is used. Vo is given by the following equation (1)
It is represented by 2).

Vo = −Vi × (D / 2 ^N ) (12) Here, assuming that the gain of the variable gain circuit shown in FIG.
The gain G is represented by the following equation (13). G = Vo / Vi =-(D / ^2N ) (13) When a variable gain circuit having the above-mentioned gain G is added to the linear interpolation circuit shown in FIG. 7, the output .DELTA.EN of the entire linear interpolation circuit becomes the following equation (14). It is represented by

ΔEN = G × k (VN−VN−1) × T / r = − (D / ^2N ) × k (VN−VN−1) × T / r Therefore, the digital control data D is By determining as in the following equation (15), the gain of the entire linear interpolation circuit can be kept constant even if the sample period changes.

T × D = constant (15) As described above, according to the present embodiment, a variable gain circuit can be added to FIG. 7 to change the gain according to the sample period T. The gain of the linear interpolation circuit can be kept constant even when the sampling period T changes. Further, since it is not necessary to use a switch for switching the resistance value as shown in the first and third embodiments, the configuration can be simplified.

Further, since a resistor built in a D / A converter can be used as a feedback resistance of the operational amplifier OP4, adjustment for individually calibrating the variation of the ladder resistance of each D / A converter as in the second embodiment. There is no need to provide any parts. In the above embodiment, the case where a step-like waveform obtained by sampling an analog signal is interpolated by a line segment has been described. However, the present invention is not limited to the above embodiment. For example, the present invention can be applied to a case where a stepwise changing signal is interpolated.

[0045]

As is apparent from the above description,
According to the present invention, the change in the gain of the linear interpolation circuit due to the change in the sample period is compensated by the gain compensating means, so that the gain of the linear interpolation circuit can be kept constant even when the sample period changes.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic configuration of the present invention.

FIG. 2 is a diagram showing a first embodiment of the present invention.

FIG. 3 is a diagram showing a second embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a multiplying DA converter.

FIG. 5 is a diagram showing a third embodiment of the present invention.

FIG. 6 is a diagram showing a fourth embodiment of the present invention.

FIG. 7 is a diagram showing a conventional linear interpolation circuit which is a premise of the present invention.

FIG. 8 is a diagram showing a time chart of a conventional linear interpolation circuit.

FIG. 9 is a diagram showing a time chart of a conventional linear interpolation circuit.

[Explanation of symbols]

2 Sample / hold circuit 3 Delay circuit 4 Subtraction circuit 5 Variable gain circuit 6 Integrator circuit 7 Gain compensation means OP1, OP2, OP3, OP4 Operational amplifier C1 Capacitor DA1, DA2 Multiplying DA converter R1 ... RN, RF1 ... RFN, RI1, RI2 resistor S1, S2 switch

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 1/00-1/88

Claims (4)

(57) [Claims] A sample-and-hold circuit for sampling an input signal at a constant period and holding a previous sample value until a next sampling time, thereby generating an output that changes discontinuously in a stepwise manner; A delay circuit (3) for delaying the output of the sample-hold circuit (2) by one sample period; and a difference between the outputs of the delay circuit (3) and the sample-hold circuit (2). A subtraction circuit (4) for obtaining a change in the output of (2); and an integration circuit (6) for integrating the output of the subtraction circuit (4). In the linear interpolation method, which converts the time point into a triangular wave signal connected by line segments, a signal that changes stepwise according to the sample period
The gain compensation means for varying the conversion gain when converting the angular wave signal (7) is provided, by the gain compensation means (7), also I by the changes in the sample period, or a signal that changes stepwise
The conversion gain when converting to a triangular wave signal is constant.
Linear interpolation method, characterized by so that compensation. 2. The gain compensation means according to claim 1, wherein a time constant of an integration circuit is variable.
Linear interpolation method. 3. The linear interpolation method according to claim 1, wherein the gain of the subtraction circuit is variable as the gain compensating means . 4. A linear interpolation system according to claim 1, wherein a variable gain circuit (5) is separately added as said gain compensating means .