JP3175752B2 - Pulse generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse generator used in an LSI tester, a pulse generator, and the like, and more particularly to a pulse generator in which a slew rate limiting circuit can be constituted by a transistor of one polarity. It is.

[0002]

2. Description of the Related Art In a conventional pulse generator, a differential amplifier, which receives a differential signal from a differential signal source, converts the signal into a pulse signal of a desired level, and a pulse rate is controlled by a slew rate limiting circuit provided downstream of the differential amplifier. The slew rate of the signal was limited. Such a device is described below. FIG. 3 is a diagram showing a configuration of a conventional pulse generator. In the figure, reference numeral 2 denotes a differential amplifier which receives a differential signal and outputs a pulse signal of a desired level. And the differential amplifier 2
NPN transistors Q5, Q6, constant current source I4, and resistor R
And 3. Reference numeral 3 denotes a slew rate limiting circuit that outputs a pulse signal in which the rise time and fall time of the signal output from the differential amplifier 2 are limited. Then, the slew rate limiting circuit 3 includes NPN transistors Q7 and P7.
It comprises an NP transistor Q8, current sources I5 and I6, and capacitors C3 and C4.

[0003] The operation of such an apparatus will be described below.
First, the operation of the differential amplifier 2 will be described. When the differential signal is at a high level, the NPN transistor Q5 turns on,
The NPN transistor Q6 is turned off, and no current flows through the resistor R3. Voltage VH is output from differential amplifier 2. When the differential signal is at a low level, the NPN transistor Q5 is turned off, the NPN transistor Q6 is turned on, and the current Id of the constant current source I4 flows through the resistor R3. That is, the voltage drop of the resistor R3 due to the change in the collector current becomes the amplitude of the pulse signal. Then, the high level of the pulse signal becomes “VH” and the low level becomes “VH−Rc × I”.
Here, Rc is the resistance value of the resistor R3, and Id is the current value of the constant current source I4.

Next, the operation of the slew rate limiting circuit 3 will be described. When the pulse signal from the differential amplifier 2 rises, a current flows between the collector and the emitter of the NPN transistor Q7, and the capacitor C3 is charged. At this time,
No current flows between the collector and the emitter of the PNP transistor Q8, and the capacitor C4 is charged by the current from the current source I6. As a result, the rise time of the output of the slew rate limiting circuit 2 is delayed. And
When the pulse signal from the differential amplifier 2 falls, NPN
No current flows between the collector and the emitter of the transistor Q7, and current flows from the capacitor C3 to the current source I5 and is discharged. At this time, a current flows between the collector and the emitter of the PNP transistor Q8, and N
A current flows through the PN transistor Q8 and discharges. As a result, the fall time of the output of the slew rate limiting circuit 3 is delayed. Here, the slew rate can be adjusted by adjusting the amount of current of the current sources I5 and I6.

[0005]

In the case of such a configuration, there is a problem that only one transistor of the slew rate limiting circuit 3 needs to use a transistor having a different polarity.

An object of the present invention is to realize a pulse generator in which a slew rate limiting circuit is constituted by transistors of one polarity.

[0007]

According to the present invention, there is provided a driving circuit for inputting a differential signal, and a driving circuit for inputting an output of the driving circuit .
A first differential amplifier , a first capacitor provided between a positive input terminal and a negative output terminal of the first differential amplifier , and charged by the driving circuit based on the differential signal. ,
Wherein provided between the negative input and the positive output terminal of the first differential amplifier, a second capacitor charged on the basis of the differential signal by the drive circuit, the first differential amplification
Input the signal input to the
It is characterized in that a second differential amplifier for generating. When one signal is at a high level, the other signal receives a pair of differential signals at a low level,
In a pulse generator for generating a pulse, a first current source (I1) and a second current source (I2) are respectively connected to an emitter, and a first NPN to which a collector is commonly connected.
The transistor (Q1) and the second NPN transistor (Q
And 2) the provision of driving circuit (10), a third current source (I
3) is connected to the emitter, the first NPN transient <br/> Star, third NPN transistor having an emitter of said second NPN transistor is connected to the base, respectively (Q
3), the fourth provided NPN transistor (Q4) 1
Differential amplifier (11), a first capacitor (C1) provided between the collector and base of the third NPN transistor, and a second capacitor (C1) provided between the collector and base of the fourth NPN transistor. Capacitor (C2)
And a fourth current source (I4) connected to the emitter, and a base connected to the bases of the third NPN transistor and the fourth NPN transistor, respectively.
Connected to the N transistor (Q5) , the sixth NPN transistor (Q6) , and the collector of the sixth NPN transistor
A second differential amplifier (2) having a resistor (R3)
Wherein a pulse is generated from the collector of the sixth NPN transistor. Further, the present invention is characterized in that the magnitude of the current of the drive circuit is made variable to adjust the slew rate of the output pulse.

[0008]

According to the present invention, the differential signal is input to the drive circuit, and the first capacitor or the second capacitor is charged based on the differential signal. With this operation, the signal input to the first differential amplifier changes. And the second
Generates a pulse by using a signal input to the first differential amplifier as a differential signal. Further, by changing the magnitude of the current of the drive circuit , the time for charging the first capacitor and the second capacitor changes. This change in time changes the slew rate of the output pulse.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a configuration diagram showing one embodiment of the present invention. In the figure,
Reference numeral 1 denotes a slew rate limiting circuit that inputs a differential signal and outputs a differential signal whose slew rate has been adjusted to the input of the differential amplifier 2. Then, the differential amplifier 2 receives the differential signal from the slew rate limiting circuit 1 and generates a pulse. In the slew rate limiting circuit 1, a driving circuit 10 receives a differential signal. Reference numeral 11 denotes a differential amplifier to which the drive circuit 10 is connected. Then, the signal input to the differential amplifier 11 is output to the differential amplifier 2 as a differential signal. C1 is a first capacitor provided between the positive input terminal and the negative output terminal of the differential amplifier 11. C2 is a second capacitor provided between the negative input terminal and the positive output terminal of the differential amplifier 11. In the drive circuit 10, I1 and I2 are the first and second
, One end of which is connected to the -5 V level, and the current amount can be adjusted. Q1 is a first emitter follower NP
In the N transistor, the other end of the current source I1 is connected to the emitter. Q2 is an NPN transistor which is a second emitter follower, and the other end of the second current source I2 is connected to the emitter. In the differential amplifier 11, the bases of the NPN transistors Q3 and Q4 are used as a positive input terminal and a negative input terminal, respectively, and the emitters of the NPN transistors Q1 and Q2 are connected respectively. The emitter is connected to one end of the constant current source I3, and the collectors are connected to resistors R1 and R2, respectively.
Are connected to form a negative output terminal and a positive output terminal. The other end of the constant current source I3 is connected to the -5V level, and the resistance R
The other end of R1 and R2 is grounded. In the differential amplifier 2, the bases of the NPN transistors Q3 and Q4 are connected to the bases of the NPN transistors Q5 and Q6, respectively, and one end of the constant current source I4 is connected to the emitter. The other end of the constant current source I4 is connected to the -5V level. NPN
The collector of the transistor Q5 is connected to the voltage value VH level, and the collector of the NPN transistor Q6 is connected to the resistor R
3 is connected to one end. The other end of the resistor R3 has a voltage value V
Connected to H level. Then, the output of the collector of the NPN transistor Q6 is output as a pulse.

The operation of such a device will be described below.
FIG. 2 is a timing chart showing the operation of the apparatus shown in FIG. First, the operation of the slew rate limiting circuit 1 will be described. As an initial state, the differential signal is low level (for example,
-1.8 V). At this time, the NPN transistor Q
1 is low and the emitter of the NPN transistor Q2 is high, the base voltage VB3 of the NPN transistor Q3 and the base voltage VB of the NPN transistor Q4.
B4 is VB3 <VB4. That is, the NPN transistor Q3 turns off and the NPN transistor Q4 turns on. As a result, all the current Ic of the constant current source I3 flows between the collector and the emitter of the NPN transistor Q4.

At time t1, it is assumed that the differential signal has transitioned from a low level to a high level (for example, -0.9V). At the cross point of the differential input, the base voltages VB3 and VB4 of the NPN transistors Q3 and Q4 coincide with each other, and the NPN transistors Q3 and Q4 enter the active region and exhibit the function of differential amplification. As a result, the base voltages VB3 and VB4 both have a high-level potential, and both move only slightly. Therefore, the NPN transistor Q1 is turned on, and the current Ia of the current source I1 flows as an emitter current. Then, the NPN transistor Q2 is reverse-biased and turned off, and the current Ib of the current source I2 is entirely supplied to the capacitor C2
And the capacitor C2 is charged. As a result, NP
The collector voltage of N-transistor Q4 rises like a ramp as capacitor C2 charges. At the same time, the collector current IC4 of the NPN transistor Q4 decreases like a ramp. Eventually, when IC4 = 0, charging ends,
The base voltage VB4 of the NPN transistor Q4 starts to decrease toward a low level. Since the operation of the NPN transistor Q3 performs differential amplification with the NPN transistor Q4, the collector current has a relationship of IC3 = Ic-IC4.

Here, assuming that the time when the charging of the capacitor C2 is completed is t2, the charging time P1 is expressed by the following equation from the time t1 to t2. P1 = Cb × ΔV / Ib (1) Cb: Capacitance of the capacitor C2 ΔV is a voltage change of the terminal of the capacitor C2 from time t1 to t2, and is expressed by the following equation. ΔV = (Ic−Ib) × Rb (2) Rb: resistance value of resistor R2 By substituting equation (2) into equation (1), P1 = (Ic−Ib) × Cb × Rb / Ib (3) Become. Equation (3) is an exact equation, but in many cases,
Since the current Ib is sufficiently smaller than the current Ic, the current Ib is handled as approximated by the following equation. P1 ≒ Ic × Cb × Rb / Ib (4)

Similarly, suppose that the differential signal has transitioned from the high level to the low level at time t3. At the cross point of the differential input, NPN transistors Q3 and Q
4, the base voltages VB3 and VB4 coincide with each other, and the NPN transistors Q3 and Q4 enter the active region and exhibit the function of differential amplification. As a result, the base voltages VB3 and VB4 are both at a high level and only slightly move.
Therefore, the NPN transistor Q2 is on and the current source I2
As the emitter current. And NPN
The transistor Q1 is reverse-biased and turned off, and the current source I
All of the current Ia flows through the capacitor C1, and the capacitor C1 is charged. As a result, the NPN transistor Q3
Rises like a ramp as the capacitor C1 is charged. At the same time, the collector current IC3 of the NPN transistor Q3 decreases like a ramp. Eventually, IC3 =
When it becomes 0, the charging ends and the NPN transistor Q
3, the base voltage VB3 starts to decrease toward the low level. In the operation of the NPN transistor Q4, since the differential amplification operation is performed with the NPN transistor Q3, the collector current IC4 = Ic-IC3. At this time,
A current flows from the capacitor C2 to the NPN transistor Q4 and is discharged.

Here, assuming that the time when the charging of the capacitor C1 is completed is t4, the charging time P2 is expressed by the following equation from the time t3 to the time t4. P2 = Ca × ΔV ′ / Ia (5) Ca: Capacity of Capacitor C1 ΔV ′ is a voltage change of the terminal of the capacitor C1 from the time t3 to the time t4, and is expressed by the following equation. ΔV ′ = (Ic−Ia) × Rb (6) Rb: Resistance value of resistor R2 By substituting equation (6) into equation (5), P2 = (Ic−Ia) × Ca × Ra / Ia (7) Becomes Equation (7) is an exact equation, but in many cases,
Since the current Ia is sufficiently smaller than the current Ic, the current Ia is approximately handled as in the following equation. P2 ≒ Ic × Ca × Ra / Ia (8)

Next, the operation of the differential amplifier 2 will be described. N
The bases of the PN transistors Q5 and Q6 are respectively NP
Since they are connected to the bases of N transistors Q3 and Q4, the collector currents have the following relationship. IC6 / IC5 = IC4 / IC3 (9) IC5, IC6: Collector currents of NPN transistors Q5 and Q6 Equation (9) shows that the collector currents of NPN transistors Q5 and Q6 and the collector currents of NPN transistors Q3 and Q4 are similar. It means that it becomes. That is, the waveform output from the differential amplifier 2 has a voltage similar to the collector current IC4 of the NPN transistor Q4, and the signal output from the differential amplifier 2 is limited in slew rate. The rising slew rate S1 and the falling slew rate S2 are as follows. S1 = Id × Rc / P1 (10) S2 = Id × Rc / P2 (11) By substituting equations (4) and (8) for equations (10) and (11), S1 = (Id × Rc / Ic × Rb × Cb) × Ib (12) S2 = (Id × Rc / Ic × Ra × Ca) × Ia (13) From equations (12) and (13), the rising slew rate S1 of the signal output from the differential amplifier 2 is equal to the current source I2
Current Ib and falling slew rate S2 are equal to current source I1
Is determined by the current Ia. That is, the current source I
By adjusting the currents I and I2, the slew rate can be adjusted.

As described above, a slew rate limiting circuit can be constituted by transistors of one polarity. If the slew rate limiting circuit is formed of NPN transistors, it is possible to generate pulses with high speed and good waveform quality. That is, it is possible to eliminate problems such as deterioration of waveform quality such as a long rise time or fall time due to the PNP transistor and occurrence of overshoot.

[0017]

According to the present invention, the following effects can be obtained. According to the first aspect, the slew rate limiting circuit can be constituted by a transistor having one polarity. Claim 2
According to the method, since the pulse generator is constituted by the NPN transistor, it is possible to generate a pulse with high speed and good waveform quality. According to the third aspect, since the magnitude of the current of the drive circuit is made variable, the slew rate of the pulse can be adjusted.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the device of FIG.

FIG. 3 is a diagram showing a configuration of a conventional pulse generator.

[Explanation of symbols]

Reference Signs List 1 slew rate limiting circuit 2, 11 differential amplifier 10 drive circuit C1, C2 capacitor I1, I2 current source I3, I4 constant current source Q1, Q2, Q3, Q4, Q5, Q6 NPN transistor

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 5/12 H03K 5/08 H03K 5/13

Claims (3)

(57) [Claims] 1. A driving circuit for receiving a differential signal , a first differential amplifier receiving an output of the driving circuit as an input, a positive input terminal and a negative output terminal of the first differential amplifier. A first capacitor provided between the first differential amplifier and a negative input terminal and a positive output terminal, the first capacitor being charged based on the differential signal by the drive circuit; A second capacitor charged by the drive circuit based on the differential signal; and a signal input to the first differential amplifier as a differential signal.
Type Te, having a second differential amplifier for generating a pulse
Pulse generator, characterized in that that. 2. A pulse generator for receiving one pair of differential signals having a low level when one signal is at a high level and generating a pulse, wherein the first current source (I1) and the second current source A current source (I2) is connected to the emitter thereof, and a drive circuit (10) including a first NPN transistor (Q1) and a second NPN transistor (Q2) commonly connected to a collector. A third current source (I3) is connected to the emitter;
NPN transistor , and a third NPN in which the emitters of the second NPN transistor are respectively connected to the base.
The transistor (Q3) and the fourth NPN transistor (Q
A first differential amplifier providing a 4) (11), and said third NPN transistor first capacitor provided between the collector and the base of the (C1), the collector and base of said fourth NPN transistor A second capacitor (C2) provided therebetween and a fourth current source (I4) connected to the emitter;
The fifth NPN transistor (Q5) and the sixth NPN transistor (Q5) whose bases are connected to the bases of the NPN transistor , the fourth NPN transistor, respectively.
6) connect to the collector of the sixth NPN transistor
And a second differential amplifier (2) provided with a resistor (R3) , wherein the pulse is generated from the collector of the sixth NPN transistor. 3. The method according to claim 3, wherein the magnitude of the current of the drive circuit is made variable,
3. The pulse generator according to claim 1, wherein a slew rate of the output pulse is adjusted.