JP3175945B2 - Dynamic semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[Object of the Invention]

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a large capacity dynamic semiconductor memory device (DRAM).

[0003]

2. Description of the Related Art DRAMs are most suitable for increasing the capacity of semiconductor memory devices. At present, 4 Mbit DRAMs are mass-produced, and 16 Mbit DRAMs are in the stage of being sampled and shipped.

[0004] The DRAM chip structure generally includes a memory cell array in which dynamic memory cells having a one-transistor / one-capacitor structure are arranged, and a row decoder for selecting a word line connected to the gate of a MIS transistor for selection in the memory cell array. And a core circuit including a sense amplifier for amplifying data read to the bit line by the selection MIS transistor, and a peripheral circuit for controlling and driving the core circuit.

At present, a gate insulating film having a film thickness of 20 nm is used for all MIS transistors constituting circuits of each section of the DRAM, mainly for simplifying the process. When the external power supply potential Vcc is 5 V, the voltage applied to the selected word line is boosted to 7.5 V in order to make the accumulated charge in the memory cell sufficient, that is, to reliably write "1" data. Is done.

In such a large-capacity DRAM, the TDD of the MIS transistor is a factor that degrades the reliability.
B (Time Dependent Dielectric Breakdown) life is a major problem. This deteriorates with time due to an electric field applied to the gate insulating film, and has become apparent as the gate insulating film becomes thinner. 4Mbit DR
In AM, 7.5 V / 2 in the memory cell array section
An electric field of 0 nm = 3.75 MV / cm is applied, and 5 V / 20 nm = 2.50 in the core circuit and the peripheral circuit section.
An electric field of MV / cm is applied.

In particular, the TDDB life of the memory cell array portion to which a large electric field is applied is a problem. Actually 4Mbit D
In a RAM, about 1 to 10 bits become defective due to TDDB during a test. The memory cell array section occupies 60% of the area of the DRAM chip, and 20% of the area is used as a gate.
The life will determine the reliability of the DRAM.

Assuming that the chip area is S and the gate insulating film thickness is Tox, the probability of the memory cell array having a TDDB failure is expressed as (１ ／) × 0.6S exp (power supply voltage / Tox). The probability of the TDDB failure in the peripheral circuit section is expressed as (1/10) × 0.4S exp (selected word line voltage / Tox). Here, the coefficient (1/4) indicates the ratio of the area of the MIS transistor region in the memory cell array region, and (1/10) indicates the ratio of the area of the MIS transistor region in the core circuit and the peripheral circuit portion. ing.

When the capacity of the DRAM is further increased due to the extension of the conventional design method, the MI of the memory cell array section is increased.
The area of the S-transistor increases relative to that of the core circuit and the peripheral circuit section. The gate insulating films of the core circuit portion and the peripheral circuit portion become thinner and thinner for higher performance. Therefore, when the thickness of the gate insulating film of the MIS transistor for selecting a memory cell is reduced together with that of the core circuit and the peripheral circuit, the probability of failure due to the TDDB life of the memory cell array section increases exponentially.

FIG. 3 shows this state. A in FIG. 3 is a probability that the memory cell array becomes defective, and B is a probability that the core circuit and the peripheral circuit become defective. For example, at 4 Gbits, the number of defective bits reaches as much as 1 kbit, and the reliability of the DRAM is significantly reduced.

[0011]

As described above, in a large-capacity DRAM, in particular, the TD in the memory cell array portion
DB life becomes an increasingly big problem.

In view of the above, it is an object of the present invention to provide a DRAM capable of improving reliability without sacrificing high-speed performance.

[Structure of the Invention]

[0014]

SUMMARY OF THE INVENTION A DRAM according to the present invention
Indicates that the maximum electric field applied to the gate insulating film of the selection MIS transistor of the memory cell array is the MI which constitutes the peripheral circuit.
The thickness distribution of the gate insulating film or the voltage of each portion is set so as to be smaller than the maximum electric field applied to the gate insulating film of the S transistor.

[0015]

In the present invention, for example, the gate insulating film thickness of the MIS transistor is the same in the memory cell array section and the peripheral circuit section, and the maximum voltage applied to the gate of the MIS transistor in the memory cell array section is lower than that of the peripheral circuit. To be. Alternatively, when a boosted potential is applied to the gate of the selection MIS transistor in the memory cell array section, the gate insulating film is made thicker than that of the peripheral circuit. By taking such considerations, the high-speed performance mainly determined by the peripheral circuit and the chip reliability mainly determined by the probability of TDDB failure in the memory cell array section are optimized, and the high-speed performance and the reliability improvement of the large capacity DRAM are improved. It is planned.

[0016]

Embodiments of the present invention will be described below.

FIG. 1 shows a main configuration of a DRAM. As shown in the figure, the DRAM has a memory cell array 1 in which memory cells MC of 1 transistor / 1 capacitor are arranged, and a row decoder 2 for selectively driving a word line WL connected to the gate of a selection MIS transistor of the memory cell array 1. (2 1, 2 1,..., 2 n), a sense amplifier 3 (31, 32,..., 3 m) for amplifying data read from the memory cell MC to the bit line pair BL, / BL, a row decoder 2 and a sense amplifier 3 thereof. It comprises a peripheral circuit 4 for controlling and driving the (core circuit).

In such a DRAM configuration, in the first embodiment, the gate insulating film thickness of all the MIS transistors in the chip is constant Tox = 4 nm. The external power supply potential is set to Vcc = 1.5V. The voltage for driving the MIS transistor of the peripheral circuit 4 is Vcc = 1.5 V, and the maximum applied voltage when the selected word line is active is Vcc-VT. The value of VT is determined by the probability of occurrence of a TDDB failure in the memory cell array 1 and the value of TD in the peripheral circuit 4 and the core circuits 2 and 3.
It is set so that the probability of occurrence of a DB defect becomes approximately the same, that is, the following equation (1) is satisfied.

S1 exp (Vcc / Tox) / S2 exp {(Vcc-VT) / Tox} = 1 (1) where S1 is the total transistor area of the peripheral circuit and the core circuit, and S2 is the memory cell array. Is the total transistor area. Specifically, for example, VT = 0.2
V.

If the threshold voltage of the MIS transistor for selection is slightly lowered in response to the reduction of the maximum applied voltage when the word line is active, the sub-threshold characteristic of the MIS transistor becomes a problem. Therefore, when the word line is not selected (at the time of standby), the voltage is lowered to -0.1 V to prevent the sub-threshold characteristic from deteriorating.

The gate insulating film of the MIS transistor is made of a material having a higher dielectric constant than a silicon oxide film or a silicon oxynitride film, for example, Ta2O5, PZT, etc., in order to prevent a decrease in the amount of accumulated charges due to a decrease in the maximum applied voltage. It is preferable to use

The conditions of the DRAM of this embodiment are summarized as follows.
It is shown in Table 1. Table 1 also shows the electric field applied to the gate insulating film of each part.

[0023]

[Table 1]

According to this embodiment, the gate insulating film thickness of the peripheral circuit is set to satisfy the high-speed performance of the DRAM, and the film thickness is used in all other regions. The voltage applied to the gate of the MIS transistor is adjusted, and the maximum electric field applied to the gate insulating film is set smaller than that in the peripheral circuit.
As a result, the TDDB failure in the memory cell array does not become dominant due to the increase in the capacity unlike the related art.

A 'in FIG. 3 is the DRA of this embodiment.
M ′ is the probability of TDDB failure in the memory cell array section at M, and B ′ is the TDDB of the core circuit and the peripheral circuit section.
The probability of failure. As shown in the above equation (1), A ′
= B ', the capacity is increased as is apparent from the relationship between the probability A of the TDDB failure in the memory cell array portion of the DRAM and the probability B of the TDDB failure in the core circuit and the peripheral circuit portion in the conventional method. In this case, high reliability is obtained. Moreover, high speed performance is not sacrificed. Next, a second embodiment will be described. The overall configuration of the DRAM is as shown in FIG. In the second embodiment, the MI of the peripheral circuit
The voltage applied to the gate of the S transistor is Vcc, and the maximum applied voltage when the word line is active is (3/2) Vcc. However, the gate insulating film thickness Toxs of the MIS transistor for selection in the memory cell array portion is made larger than the gate insulating film thickness Toxp of the MIS transistor of the peripheral circuit. Film thickness T
The oxs is obtained by the following equation (2) having the same meaning as the above equation (1).

S1 exp (Vcc / Toxp) / S2 exp {(3/2) Vcc / Toxs} = 1 (2) Specifically, when the power supply potential Vcc = 1.5 V and Toxp
= 4 nm and Toxs = 8 nm.

Table 2 shows the conditions of the DRAM of this embodiment corresponding to Table 1.

[0028]

[Table 2]

According to this embodiment, as in the previous embodiment, the maximum electric field applied to the gate insulating film in the memory cell array is set lower than that in the peripheral circuit and the core circuit, and the memory cell array in the memory capacity is increased. Is effectively suppressed from increasing in the TDDB failure probability.

Next, ECC (Error Check and Corr)
A third embodiment having a (rect) function will be described.

FIG. 2 shows a main configuration of the DRAM of the third embodiment. The difference from FIG. 1 is that an ECC memory cell array 1 ′ as a so-called redundant bit is added to the memory cell array 1.
That is, a CC row decoder 2 'is provided.

As in the first embodiment, the gate insulating film thickness of all MIS transistors in the DRAM chip is T
ox = 4 nm. The external power supply potential is set to Vcc = 1.5V.

When ECC is not used,
(3/2) Vcc is used as the maximum voltage of the selected word line, and Vcc is used for the peripheral circuit and the core circuit. Then, considering the electric field strength, a TDDB failure occurs before the peripheral circuit in the memory cell array portion. At this time, the DRAM chip is rescued by the ECC function. When this ECC is used, the maximum applied voltage of the selected word line and the applied voltage of the peripheral circuit are reduced.

Specifically, when the ECC is used, the voltage applied to the selected word line is changed to Vcc-VT = 1.3 when active.
V, and -0.1 V during standby. The bit line charging voltage is also reduced to Vcc-VT, and the peripheral circuit applied voltage is also Vcc-δ =
Reduce to 1.4V.

Table 3 shows the conditions in this embodiment.

[0036]

[Table 3]

As described above, according to this embodiment, the voltage of each part is selectively used when the ECC is not used and when the ECC is used, and the DR is used.
It is possible to improve the reliability while securing the high-speed performance of the AM.

[0038]

As described above, according to the present invention, it is possible to obtain a highly reliable DRAM by maintaining the high-speed performance and reducing the probability of TDDB failure in the memory cell array when the capacity is increased. be able to.

[Brief description of the drawings]

FIG. 1 is a diagram showing a main configuration of a DRAM.

FIG. 2 is a diagram showing a main configuration of a DRAM with an ECC function.

FIG. 3 is a diagram showing the dependency of the TDDB failure on the degree of integration according to the present invention in comparison with a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Row decoder, 3 ... Sense amplifier, 4 ... Peripheral circuit, MC ... Memory cell, BL, / B
L: bit line, WL: word line.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 11/407

Claims (3)

(57) [Claims] 1. A memory cell array in which dynamic memory cells are arranged in a matrix, a row decoder for selecting a word line connected to a gate of a selection MIS transistor of the memory cell array, and a bit line by the selection MIS transistor. In a dynamic semiconductor memory device including a sense amplifier for amplifying read data and a peripheral circuit for controlling the row decoder and the sense amplifier, a maximum electric field applied to a gate insulating film of a selection MIS transistor of the memory cell array. Is set smaller than the maximum electric field applied to the gate insulating film of the MIS transistor constituting the peripheral circuit , and the dynamic semiconductor memory device has an ECC function.
The memory cell when the ECC function is used.
Applied to the gate of the MIS transistor for selecting
Is the maximum voltage when the ECC function is not used.
A dynamic semiconductor memory device characterized in that the value is set to a value lower than that of (1) . 2. The gate insulating film thickness of the MIS transistor for selecting the memory cell array is set equal to the gate insulating film thickness of the MIS transistor of the peripheral circuit, and is applied to the gate of the MIS transistor for selecting the memory cell array. 2. The dynamic semiconductor memory device according to claim 1, wherein a maximum voltage is set lower than a maximum voltage applied to a gate of the MIS transistor of the peripheral circuit. 3. The dynamic semiconductor memory according to claim 1, wherein the gate insulating film thickness of the MIS transistor for selection of the memory cell array is set to be larger than the gate insulating film thickness of the MIS transistor of the peripheral circuit. apparatus.