JP3175995B2 - Filter circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for making a filter circuit into an IC.

[0002]

2. Description of the Related Art Conventionally, a filter circuit has been difficult to be integrated into an IC because of both elements of a resistor and a capacitor.
Hereinafter, the reason will be described with reference to the drawings. The symbols described in the circuits used hereinafter are used as they are as variables in mathematical expressions described in this specification. For example, in the drawings, when the symbol R is used for the resistance element, the resistance value is also R, and when the symbol I is used for the current source, the current value is also I. The equation for the voltage V generated across the resistance element R when the current flows is described as V = IR.

FIG. 6 shows such a conventional filter circuit.

In FIGS. 1 (a) and 1 (b), the filter circuit shown in FIG. 1 is constituted as an LPF by a conductance amplifier gm1, a passive resistance element R0 and a capacitor C0. The amplifier gm1 is roughly divided into a differential input circuit and an output circuit.

First, the input circuit will be described. Q1,
Q2 is an NPN transistor as a differential pair, and an input signal vin is applied between their bases. I1 is a current source for biasing both Q1 and Q2, and a passive resistance element R1 is inserted between the transistors Q1 and Q2 and the current source I1.

The output circuit comprises a current mirror circuit. A collector of the transistor Q1 is connected to a current mirror circuit comprising PNP transistors Q9 and Q12 as an active load. A collector of the transistor Q2 is also a PNP type transistor as an active load. Transistors Q10, Q11
And a current mirror circuit composed of NPN transistors Q13 and Q14. The collectors of the transistors Q12 and Q14, which are the output terminals of the output currents of the differential pairs Q1 and Q2, are connected to each other, and the connection point is connected to the passive resistance element R0 and the capacitor C0.

The operation of the filter circuit configured as described above is as follows. First, when the input signal vin is not in an alternating manner, that is, when vin = 0, the transistors Q1,
Q2 is turned on to the same extent, and the transistors Q1, Q
2, a current flows by I1 / 2. The collector current of the transistor Q1 is output to the collector of the transistor Q12 via the current mirror of the transistors Q9 and Q12, and the collector current of the transistor Q2 is supplied to the collector of the transistor Q14 via the current mirror of the transistors Q10 and Q11 and the current mirror of the transistors Q13 and Q14. Is output to Now, the collector current Ic (Q12) of the transistor Q12 and the collector current Ic (Q14) of the transistor Q14 are expressed as Ic (Q12) =
Since Ic (Q14), iout = 0, and vout is maintained at a constant value in an ideal state.

Next, when the AC input signal vin> 0,
Since the transistor Q1 is turned on more than the transistor Q2, the collector current Ic (Q
1) and the collector current Ic (Q2) of transistor Q2 is Ic
(Q1)> Ic (Q2), and Ic (Q12)> Ic (Q14) → iout
> 0. Thus, the capacitor C0 is charged and its potential rises, and vout rises.

When the AC input signal vin <0, the transistor Q2 is larger than the transistor Q1 by o
Since the state becomes n, Ic (Q2)> Ic (Q1) → Ic (Q14)> I
c (Q12) → output current iout = Ic (Q12) −Ic (Q14) <0. Therefore, the capacitor C0 is discharged, and the output voltage vout falls.

By analogy, the output current iout and the voltage vout when the voltage vin is input to the input terminal can be expressed by the following equations. iout = gm1 · vin (1) vout = iout · (1 / ((1 / R0) + S · C0)) (2) By substituting equation (1) into equation (2), the following is obtained. = Gm1.vin. (1 / (1 / R0) + S.C0) = gm1.vin.R0 / (S.C0.R0 + 1) (3) Therefore, the alternating impedance vout / vin is vout / vin = gm1 · R0 / (S · C0 · R0 + 1) (4) Therefore, if S = jω, the frequency characteristic becomes as shown in FIG. 6C when graphed on a logarithmic axis. /
The characteristic is such that the gain decreases at (R0 * C0).

Here, it is considered that an external capacitor is built in an IC. To do so, the capacitance C0 must be reduced to a smaller value C0 '. That is, when expressed by the equation, C0 '= (1 / N) · C0 (5) In order to obtain the same characteristics as those described above, the resistance R0 must be set to a larger value R0 '.
That is, R0 '= N · C0 (6)

Therefore, when the capacitor C0 is to be incorporated, the resistance R0 must be increased, and the high resistance requires a large area on the chip. Element R0
It is difficult to incorporate both of them, and in the current technology, when comparing the resistance element and the capacitor, the former requires only a smaller area, so it is customary to incorporate only the resistor and externally attach the capacitor. It has become.

[0013]

As described above, in the conventional filter circuit, it is necessary to externally connect only a capacitor in the case of an IC.

The present invention has been made in view of such a problem, and an object of the present invention is to provide a filter circuit capable of reducing the area occupied by a built-in element on a chip when implementing an IC. It is in.

More specifically, firstly, it is an object of the present invention to reduce the size of a capacitive impedance circuit and to enable the capacitive impedance circuit to be built on a chip.

Second, the object is to reduce the size of the resistance impedance circuit and reduce the area occupied on the chip.

The ultimate object of the present invention is to reduce the size of the impedance circuit for both the capacitance and the resistance and to eliminate any external elements.

[0018]

A filter circuit according to the present invention converts an input voltage signal provided as a differential input into a current signal, and outputs the current signal to an intermediate node. A compression circuit formed by an active resistance circuit that converts the signal into a voltage signal obtained by compressing the input voltage signal, and a current signal obtained by expanding an output signal of a compression circuit given by differential input, and converting the signal into a current signal. A decompression circuit that outputs a current signal to an output node; a charge / discharge controlled by the current signal of the output node; the potential of which is a filter output voltage signal; And a resistance impedance circuit for determining the frequency characteristic of

At this time, it is desirable that the resistance impedance circuit is formed by an output feedback circuit that converts a filter output voltage signal provided as a differential input into a current signal and outputs the current signal to an intermediate node.

Further, the filter circuit of the present invention converts an input voltage signal provided as a differential input into a current signal, and outputs the current signal to an output node. A charge / discharge-controlled capacitor impedance circuit whose potential is used as a filter output voltage signal, and an output that converts a filter output voltage signal given as a differential input into a current signal and outputs this current signal to an intermediate node A compression circuit formed by a feedback circuit, an active resistance circuit that converts the current signal at the intermediate node into a voltage signal obtained by compressing the voltage signal to be processed, and an output signal of the compression circuit provided as a differential input. And a decompression circuit for converting the current signal to an output node.

[0021]

According to the present invention, it is possible to eliminate external elements by miniaturizing both impedance circuits of capacitance and resistance.

That is, the output current signal of the input circuit to be processed is subjected to compression / expansion processing to obtain a current signal having a proportional relationship with the current signal, thereby controlling charging and discharging of the capacitive impedance circuit. Accordingly, the current for controlling the capacitive impedance circuit can be reduced depending on the setting of the ratio of the current signals having the proportional relationship, and the capacitance value of the capacitive impedance circuit can be reduced accordingly. Therefore, the provision of the capacitance impedance miniaturizing means makes it possible to incorporate a capacitance impedance circuit.

Further, the filter output voltage signal is differentially input, converted into a current signal, and subjected to the compression / expansion processing, thereby reducing the resistance value of the resistance impedance circuit depending on the setting of the current signal ratio. Therefore, if the resistance impedance miniaturizing means is provided, the area occupied by the resistance impedance circuit on the chip can be reduced.

Therefore, if both the former means for reducing the capacitance impedance and the latter means for reducing the resistive impedance are combined, a filter circuit which does not have any external elements when integrated into an IC is realized.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a filter circuit according to one embodiment of the present invention. The filter circuit shown in this figure has three conductance amplifiers gm1, gm2, gm
3, a capacitor C1 and resistance circuits rD1 and rD2. In the circuit shown in FIG. 6, the amplifier gm1 is expressed in a form including a differential input circuit and an output circuit. The output circuit is represented by a form included in the amplifier gm2, which is constituted only by the one corresponding to the differential input circuit.

Accordingly, the amplifier gm1 needlessly be described in detail. The NPN type transistors Q1 and Q2 as a differential pair, the current source I1 for biasing their emitters, the emitters of the transistors Q1 and Q2 and the current source I1
And a passive resistance element R1 inserted between them.

Next, the amplifier gm2 is connected to an NPN
Type transistors Q7 and Q8 and a current source I2 for biasing their emitters. The base of the transistor Q7 is connected to the collector of the transistor Q2, and the base of the transistor Q8 is connected to the collector of the transistor Q1. The output circuit is connected to the collectors of these transistors Q7 and Q8. That is, the PNP transistor Q9 is connected to the collector of the transistor Q7.
, Q12 is connected to the collector of the transistor Q8, and a current mirror circuit also consisting of PNP transistors Q10, Q11 and a current mirror circuit consisting of NPN transistors Q13, Q14.

The capacitor C1 is connected to the collectors of the transistors Q12 and Q14, which are output terminals of the entire filter circuit.

The amplifier gm3 comprises NPN transistors Q5 and Q6 forming a differential pair, a current source I3 for biasing their emitters, and a passive resistor inserted between the emitters of the transistors Q5 and Q6 and the current source I3. And an element R3. A constant voltage is applied to the base of the transistor Q5 by the voltage source Vbias1.
The output signal vout is applied to the base 6. The collectors of the transistors Q5 and Q6 are connected to the amplifier gm3.
2 is connected to the bases of the transistors Q7 and Q8 so as to be connected in parallel with the amplifier gm1.

Q3 and Q4 are resistance circuits rD1 and rD2, respectively.
A constant voltage is applied to their bases in common by a voltage source Vbias2, the collectors of the transistors Q3 and Q4 are connected to a power supply Vcc, and the emitter of the transistor Q3 is connected to the transistor Q3.
1 and the emitter of the transistor Q4 is connected to the collector of the transistor Q2. The transistors Q3 and Q4 function as diodes for the output currents of the amplifiers gm1 and gm3.

Therefore, when the output currents of the amplifiers gm1 and gm3 flow through the transistors Q3 and Q4,
7, the base potential of Q8 is determined. Therefore, in short, an amplifier gm2 is composed of a resistor circuit including the transistors Q3 and Q4 and an amplifier gm2 including the transistors Q7 and Q8.
A compression / expansion circuit utilizing the non-linear characteristics of the diode with respect to the output currents of 1 and gm3 is formed.
Is proportional to the output current of the amplifier gm2.

Here, paying attention only to the amplifiers gm1 and gm2 and ignoring the amplifier gm3, a mathematical analysis of the compression / decompression circuit is performed. First, the AC emitter resistance re of the transistor is given by re = VT / Ic = k T / (q · Ic) (7) Here, VT is the thermal voltage, k is the Boltzmann constant, q is the elementary charge, and T is the absolute temperature.

Therefore, the emitter resistances of the transistors Q3 and Q4, that is, rD1 and rD2 are changed to re1 and the transistor Q7
, Q8, the emitter resistance is represented by re2, respectively: re1 = 2 · VT / I1 (8) re2 = 2 · VT / I2 (9) Also, the base potential vin and the output current of the transistors Q7 and Q8 The AC component iout can be represented by the following equation using the resistors re1 and re2. vin = 2 · re1 · i1 (10) iout = vin / (2 · re2) (11) When these equations (8) to (11) are solved for iout, iout = (re1 / re2) · i1 = (I2 / I1) .i1 (12) is derived. As is clear from this equation, the current iout
Is proportional to the current i1, and the proportionality constant is determined by iout / i1 = I2 / I1 (13).

Referring now to FIG. FIG. 2 is an explanatory view of the process from the exterior of the capacitor to the internal one. FIG. 2 (a) is equivalent to the circuit shown in FIG. 6 (b) except that the passive resistance element R0 is omitted. FIG. 2 (b) shows a circuit when the circuit is replaced with C1.

The amount of charge q stored in the capacitor can be generally expressed as q = CV = it (14), based on the capacitance C, voltage V, current I, and time t.

That is, assuming that the voltage V and the time t are constant, the capacitance C and the current i are in a proportional relationship.

Therefore, if the output current of the circuit shown in FIG. 2 is reduced, the capacitance C0 can be reduced, and the capacitance C0 can be reduced.
The possibility of the built-in becomes visible.

If the current source I1 is reduced, the current i can be reduced without changing the circuit structure. However, if such a measure is adopted, there is a problem that the dynamic range is narrowed.

Therefore, in the circuit shown in FIG. 2B, a compression circuit including transistors Q3 and Q4 and a transistor Q7 are provided in order to provide a means for reducing the current i in equation (14) while keeping the current source I1 as it is. , Q8 are inserted between input and output.

The relationship between the currents i1 and iout and the currents I1 and I2 by the compression / expansion circuit is as described above, and is expressed by equation (13).
As is apparent from the above, if I2 is set to be smaller at a fixed ratio to I1, iout corresponding to i in equation (14) can be reduced without reducing I1. For example, if it is desired to reduce C in equation (14) to 1/500, i out of transistors Q7 and Q8 is i1 /
It suffices to set the ratio between I1 and I2 so as to obtain 500. As a result, it is possible to incorporate a capacitor while maintaining the same dynamic range as before.
Note that this description that the ratio of I1 and I2 should be set simply ignores the amplifier gm3 for the sake of simplicity, and the analysis when the amplifier gm3 is also taken into account will be performed later.

By the way, as described above, the capacitance of the capacitor is C1 = (I2 / I1) .C0 (for example, C0 / 50
0), the same frequency characteristics as when the capacitance of the capacitor was C0 (that is, 1 / (CR))
= Constant), R0 is set to I1 / I2 (for example, 50
0 times). However, such a high resistance makes it difficult to incorporate the device and requires an external device, which is contrary to the purpose of the present application. Therefore, a means for realizing this high resistance by using a resistor that is used in a normal degree has been devised. FIGS. 3 to 5 are explanatory views of a process for realizing the high resistance with a resistance that is normally used.

When the output of the conductance amplifier gm is fed back as shown in FIG.
As shown in (b), the equivalent resistance viewed from the output end is 1 / gm
Becomes For example, the conductance amplifier g shown in FIG.
In the case of m, the equivalent resistance is re.

The equivalent resistance re can be increased by reducing the bias current, but the conductance amplifier gm of FIG. 3C has a very narrow dynamic range. FIG. 4A shows the case where the dynamic range is infinite, FIG. 4B shows the case of the circuit shown in FIG. 3C without the resistor Ra, and FIG. 3C shows the circuit shown in FIG. In the case of the circuit shown in FIG. 4, the respective dynamic range characteristics are shown. As is clear from FIG. 4B, the circuit shown in FIG. Is narrow.

It is also conceivable that the conductance amplifier gm shown in FIG. 3D is used, and the dynamic range is wide as Ra.Ia as shown in FIG. 4C.
However, since re <Ra is usually used, re + Ra
Is almost equal to Ra, and Ra is high in realizing an equivalent high resistance, which is not realistic.

Therefore, in the present invention, a conductance amplifier as shown in FIG. 3 (e) has been constructed using the concept of current compression / expansion.

That is, a constant bias voltage Vbias is applied to one base of transistors Q5 and Q6 forming a differential pair.
By applying 1 and feeding back the output voltage vout to the other base, the conductance amplifiers gm3 and gm22 operate equivalently as resistors. As a result, the dynamic range can be widened to R3 · I3, and the equivalent resistance is R3 · I3 / I2. By taking a large value of I3 / I2, even if R3 is selected to a resistance value that is normally used, it is equivalent to R3 · I3 / I2. High resistance can be realized.

Therefore, the resistance R0 of the circuit shown in FIG. 5A incorporating a capacitor by the circuit means shown in FIG.
Is as shown in FIG. 5B by the circuit means shown in FIG. From this, it can be seen that the parts except for the conductance amplifiers gm1 and gm3 have the same circuit configuration.

Therefore, the conductance amplifiers gm1, gm
FIG. 1B shows a state in which a portion except for m3 is formed by a common circuit.

Here, a comprehensive mathematical analysis of this circuit including the amplifier gm3 will be performed.

First, the amplifiers gm1 and g constituting the input stage
The output currents i1 and i3 of m3 are: i1 = gm1 · vin (15) i3 = gm3 · vout (16) The input voltage v2 of the amplifier gm2 constituting the output stage is
Assuming that rD1 = rD2, the output current iout and the output voltage vout are: v2 = 2 · rD1 · (i1−i3) (17) iout = gm2 · v2 (18) vout = iout · (1 / SC1) (18) 19) When v2 and iout are eliminated from these equations, vout = (1 / (S · C1)) · gm2 · 2 · rD1 · (gm1 · vin−gm3 · vout) (20) ∴vout / vin = ( 2 · rD1 · gm1 · gm2) / (S · C1 + 2 · rD1 · gm2 · gm3) (21) The conductances gm1, gm2, and gm3 are gm1 = 1 / (2 · R1) (22) gm2 = 1 / re2 = I2 / (2 · VT) (23) gm3 = 1 / (2 · R3) (24) Since the resistance rD1 is rD1 = 2 · VT / (I1 + I3) (25) By substituting equations (22) to (25) into equation (21), vout / vin = 2 · (2 · VT / (I1 I3)) · (1 / (2 · R1)) · (I2 / 2 · VT)) ÷ (S · C1 + 2 · (2 · VT / (I1 + I3)) · I2 / (2 · VT) · (1 / (2 · R3)) = (I2 / (I1 + I3)) · (1 / R1) ÷ (S · C1 + (I2 / (I1 + I3)) · (1 / R3)) = (R3 / R1) ) · (1 / (S · C1 · R3 · ((I1 + I3) / I2) +1)) (26) Here, when equations (4) and (26) are described together, equation (4) becomes vout / vin = (R0 / R1). (1 / (S.C0.R0 + 1)) Expression (26) is as follows: vout / vin = (R3 / R1). (1 / (S.C1.R3. (( I1 + I3) / I2) +1)), and comparing and comparing the terms forming both equations, the following can be found.

One is that the ratio of I1 + I3 to I2 is (I1 + I3).
By taking the value of + I3) / I2 to be large, C1 can be reduced.

In addition, R3 = R0, and a characteristic high resistance is not required to obtain a predetermined frequency characteristic.

As a whole, a circuit very suitable for the implementation of an IC is constructed. As described above, the output current signal i1 of the amplifier gm1 is subjected to compression / expansion processing by the active resistance circuits rD1, rD2 and the amplifier gm2 to obtain a current signal iout proportional to the current signal i1. Since the charging and discharging of the capacitor C1 serving as an impedance circuit is controlled, the current iout for controlling the capacitor C1 can be reduced depending on the setting of the proportional current signal ratio iout / i1 (= I1 / I2). Accordingly, the capacitance value of the capacitor C1 can be reduced.

Also, the filter output voltage signal vout is differentially input by the amplifier gm3 and converted into a current signal i3, which is subjected to compression / expansion processing by the active resistance circuits rD1 and rD2 and the amplifier gm2, thereby obtaining the current signal. Ratio iout / i1
Depending on the setting of (= I3 / I2), the resistance value of the resistance impedance circuit can be reduced.

Thus, according to the above-described embodiment, a filter circuit having no external elements when integrated into an IC can be realized.

[0056]

As described above, according to the present invention, it is possible to reduce the size of a capacitive impedance circuit or a resistive impedance circuit. The former can be built in an IC, and the latter can be implemented on a chip. Occupied area can be reduced. Since both the capacitance and resistance impedance circuits can be miniaturized, an IC filter circuit having no external elements can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a filter circuit according to one embodiment of the present invention.

FIG. 2 is a circuit diagram for theoretically describing a means for reducing the capacitance impedance of the filter circuit shown in FIG. 1;

FIG. 3 is a circuit diagram for theoretically explaining a resistance impedance miniaturizing means of the filter circuit shown in FIG. 1;

FIG. 4 is a characteristic curve diagram showing a relationship between a passive resistance element and a dynamic range in a conductance amplifier serving as a resistance impedance miniaturization unit shown in FIG. 3;

FIG. 5 is a circuit diagram for explaining a theoretical process until the circuit shown in FIG. 1 is constructed by combining the impedance miniaturizing means shown in FIGS. 2 and 3;

FIG. 6 is a circuit diagram ((a) and (b)) showing a configuration of a conventional filter circuit and a characteristic curve diagram ((c)) showing its frequency characteristics.

[Explanation of symbols]

gm1 Conductance amplifiers Q1 and Q2 as processing target signal input circuits Differential pair transistors R1 Passive resistance elements I1 Current sources rD1 and rD2 Active resistance circuits as compression circuits Q3 and Q4 Diode-connected transistors Vbias2 DC bias voltage sources gm2 Expansion circuits Conductance amplifier Q7, Q8 Differential pair transistor I2 Current source Q9, Q12 + side current mirror connection transistor Q10, Q11-side first stage current mirror connection transistor Q13, Q14-side second stage current mirror connection transistor gm3 as feedback circuit Conductance amplifier Q5, Q6 Differential pair transistor R3 Passive resistance element I3 Current source Vbias1 DC bias voltage source C1 Capacitor as capacitive impedance circuit Vin Voltage signal to be processed v2 Intermediate node voltage signal vout Filter output voltage signal i1 m1 output current signal i3 gm3 output current signal iout gm2 output current signal of the

Claims (3)

(57) [Claims] An input circuit for converting an input voltage signal provided as a differential input into a current signal and supplying the current signal to an intermediate node; and a voltage signal obtained by compressing the input voltage signal from the intermediate node current signal. A compression circuit formed by an active resistance circuit for converting the current into a differential signal and expanding the differential output signal of the compression circuit into a current signal, and supplying the current signal to an output node Charge / discharge is controlled by a current signal of the output node, a capacitive impedance circuit having one end connected to the output node, and a resistance value according to a ratio of a current flowing through the output node to an output current of the input circuit. And a resistive impedance circuit connected to the output node. 2. The resistance impedance circuit includes an output feedback circuit that converts a voltage signal at the output node into a current signal and supplies the current signal to an intermediate node, and supplies the current signal to the intermediate node by the output feedback circuit. 2. The filter circuit according to claim 1, wherein the converted current signal is converted into a voltage signal by the compression circuit, then converted into a current signal by the expansion circuit, and supplied to the output node. 3. An input circuit to be processed, which converts an input voltage signal provided as a differential input into a current signal and supplies the current signal to an output node; and charging / discharging is controlled by the current signal at the output node. A capacitive impedance circuit whose potential is a filter output voltage signal; an output feedback circuit that converts the filter output voltage signal into a current signal and outputs the current signal to an intermediate node; A compression circuit formed by an active resistance circuit that converts a signal into a compressed voltage signal; and a current signal obtained by expanding an output signal of the compression circuit provided as a differential input, and converting the current signal into the output node. And a decompression circuit for outputting the signal to the filter circuit.