JP3180367B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a word line structure suitable for application to a highly integrated semiconductor memory device and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a highly integrated semiconductor memory device, the size of a memory cell for storing one bit of information is small, and a large number of the memory cells are arranged in a matrix. Therefore, a word line for selecting a specific memory cell from a large number of memory cells has a very narrow width and a long interval with a small interval. Further, since the word line is connected to the gate electrode of the selection transistor of the memory cell, its capacity is large. Under these circumstances, in a conventional highly integrated semiconductor memory device, an aluminum film or the like having a low resistance has been used in a word line with a small and narrow interval in order to speed up the selection operation. However, it is difficult to finely process a material having a low resistance, such as an aluminum film, so that it is difficult to further increase the degree of integration of a highly integrated semiconductor memory cell device.

As a method of overcoming the difficulty of processing a word line using a low-resistance material with a narrow width and a narrow interval,
The following double word line structure has been proposed. For example, IEE Journal of Solid State Circuits (IEEE Journal)
l of Solid-State Circuit
s) Shizuo Chou (Vol. 24)
o Chou) et al., “A.60
"Nanosecond 16 megabits dilam with a minimized sensing delay reduced by bitline stray capacitance" (A60-
ns 16-Mbit DRAMwitha Mini
Mized Sensing Delay Cause
dbyBit-Line Stray Capasit
ance) (p. 1176). In this memory device, one aluminum word line is wired for every four silicide word lines, and the two are connected through switches at several places in the memory cell array. By doing so, the sum of the width and the interval of the aluminum film can be increased to four memory cells, and the resistance of the word line is reduced.
A selection signal is supplied to the above-described switch to determine which of the four silicide word lines is to be connected to the aluminum word line.

Further, in the conventional semiconductor memory device, aluminum or the like, which can only be processed at a low temperature in order to reduce the resistance of the word line, is used as the material. Must. Therefore, when the gate electrode of the switching transistor of the memory cell is formed of a material other than the aluminum film, it and the aluminum wiring for lowering its resistance must be separately formed in the lower layer portion and the upper layer portion of the semiconductor memory cell. Was. In this case, it is necessary to separately form wirings in two layers and connect them.

[0005]

In a conventional highly integrated semiconductor memory device, it is necessary to perform a difficult process of forming a thin aluminum film or the like having a low resistance on word lines at small and narrow intervals. A heavy word line structure had to be adopted. In the former case,
When the gate electrode of the switching transistor of the memory cell is formed of a material other than aluminum, the word line is
It was necessary to form them separately in one layer and connect them. In the latter case, it takes time to process the word line twice, and a place for connecting both word lines through a switch is required, so that the manufacturing method is complicated and the area is large. There was a problem.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory having a word line configuration capable of high-speed operation without using a low-resistance material for a word line and requiring only one processing of a word line in a fine memory cell portion. The purpose of the present invention is to provide an apparatus and a method of manufacturing the same.

[0007]

A semiconductor memory device according to the present invention comprises a plurality of memory cell arrays, sub-word lines provided for each of the memory cell arrays, and an interlayer insulating film provided on the sub-word lines. A main word line; and a buffer amplifier for amplifying a signal of the main word line and transmitting the amplified signal to the sub word line.

Further, according to a method of manufacturing a semiconductor memory device of the present invention, a step of forming a first conductive film on a semiconductor chip provided with a plurality of memory cell array portions; Removing a portion between the cell array portions into a predetermined shape, forming an interlayer insulating film and then forming a second conductive film, and forming the first conductive film, the interlayer insulating film and the second conductive film. By processing the stack of body films into a predetermined shape, a sub-word line composed of a first conductive film divided for each memory cell array portion and the second word line provided thereon via the interlayer insulating film Forming a main word line made of a conductive film.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic diagram showing the structure of a semiconductor memory device according to one embodiment of the present invention. For convenience, the word line portion is shown in a perspective view, but the other portions are shown in a simplified manner. In this figure, 2i and 2j are regions (memory cell array portions) in which memory cells are arranged in a matrix, Wii and Wij are sub-word lines made of a first conductive film, and Wi is a word line made of a second conductive film. 3 is an interlayer insulating film, 5 is a power supply line, 6
Is a ground line, and 4 is a buffer amplifier. For convenience,
Although only one set of Wi / Wij is shown, actually a plurality of sets having the same configuration are provided in parallel on the memory cell array unit.

In the semiconductor memory device of this embodiment, the first conductor film and the second conductor film are each a tungsten silicide film which is easy to be finely processed, the interlayer insulating film 3 is a silicon dioxide film, and the buffer amplifier 4 is CMOS inverter circuit 2
It is assumed that each of the stages is configured. Further, it is assumed that about 100 memory cells are arranged in the memory cell array section in the direction along the word line. In this case, the resistance of the main word line Wi is about 100 times larger than that of the case where the material is aluminum. The number of transistors connected to the main word line Wi is smaller than that in the case where the word line Wi is directly connected to the selection transistor of the memory cell.
When the load capacity is reduced to about 1/100, the load capacity is also reduced to about 1/100. However, it is assumed that there are 100 memory cell array units. Therefore, the signal propagation speed of the main word line Wi is:
This is similar to the case where the aluminum word line is directly connected to the select transistor of the memory cell.

The sub-word lines 2i, 2
The speed at which a signal is transmitted to the select transistor of the memory cell through j is as small as about 100 select transistors of the memory cell connected to each sub-word line. Can be made substantially the same as the signal propagation speed when the aluminum line is directly connected to the select transistor of the memory cell. In this case, since the power supply line 5 and the ground line 6 can be made of aluminum wiring, signal delay in these wirings does not matter.

Although the case where the number of sub-word lines driven by the output of one buffer amplifier 4 is two is shown, the number may be one or two or more, for example, ten. Good.

The semiconductor memory device shown in FIG. 1 can be manufactured as follows. This is one embodiment of the method for manufacturing a semiconductor memory device according to the present invention.

First, as shown in FIG. 2, a semiconductor chip having an appropriate base is prepared. For example, a field oxide film is used to form a memory cell array forming region (shown by the same reference numeral as the memory cell array unit) or the CMOS inverter unit 7.
(Provided that an appropriate well is provided), and a gate oxide film is formed. Next, a tungsten silicide film is deposited and patterned to form a CMOS gate electrode,
Is formed. The first conductor film 8 is divided for each memory cell array formation region.

Next, a silicon dioxide film is deposited as an interlayer insulating film (3 in FIG. 1), a tungsten silicide film is deposited, and is patterned as shown in FIG.
To form The second conductive film is not provided on the end 11 of the first conductive film 9 on the side of the CMOS inverter 7.

Next, after forming a resist film 12 as shown in FIG. 4, using the mask as a mask, the second conductive film, the interlayer insulating film and the first conductive film are etched to have a shape shown in FIG. Get a pattern.

Next, ion implantation is performed to form source / drain regions of the MOS transistor.
Wiring such as a ground line, a power supply line, and a connection line between a word line and a peripheral circuit is formed. In this wiring step, the connection end 13 of the sub-word line is connected to the output end of the CMOS inverter forming the buffer amplifier.

Both the sub-word line and the main word line are formed of tungsten silicide, which is easily processed finely, and the width of the word line can be etched once in the memory cell array region. Therefore, a fine word line can be formed.

[0020]

As described above, according to the present invention, in a semiconductor memory device, a sub-word line is provided for each of a plurality of memory cell arrays, and a signal from a main word line is supplied to each sub-word line via a buffer amplifier. By doing
The load on the main word line is reduced. Therefore, even if the word line is formed of a material suitable for fine processing even if the resistance is relatively high, high-speed operation can be performed.

Further, according to the method of manufacturing a semiconductor memory device of the present invention, the width of the word line in the memory cell array portion is determined by one etching step. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a schematic perspective view showing one embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a plan view used for describing one embodiment of a method for manufacturing a semiconductor memory device of the present invention.

FIG. 3 is a plan view used for describing one embodiment of a method for manufacturing a semiconductor memory device of the present invention.

FIG. 4 is a plan view used for describing one embodiment of a method for manufacturing a semiconductor memory device of the present invention.

FIG. 5 is a plan view used for describing one embodiment of a method for manufacturing a semiconductor memory device of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2i, 2j Memory cell array part 3 Interlayer insulating film 4 Buffer amplifier 5 Power supply line 6 Ground line 7 CMOS inverter part 8 First conductor film 9 CMOS gate electrode 10 Second conductor film 11 First conductor End of film 12 Resist film 13 Connection end of sub word line

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/108 G11C 11/407 H01L 21/8242

Claims (1)

(57) [Claims] A plurality of memory cell arrays; a sub-word line provided for each of the memory cell arrays; a sub-word line; and a main word line provided on the sub-word line via an interlayer insulating film. And a buffer amplifier for amplifying the signal of the main word line and transmitting the amplified signal to the sub word line.