JP3182758B2 - Thin film transistor memory - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor memory that can be electrically written and erased using a thin film transistor.

[Prior Art] EEPROMs that can be electrically written and erased include an MNOS type structure and a floating gate type structure. In each case, the tunnel effect is used for writing / erasing, so that the writing / erasing current is extremely small. Therefore, this EE
When a PROM is used as a data memory in an electronic device such as an electronic organizer, a multifunctional electronic device such as simultaneous erasure of all bits and writing / erasing of a page unit can be developed.

The MNOS type memory cell is an FET in which the gate oxide film of the MOSFET is replaced with a double-layer structure of an extremely thin oxide film (up to 20 mm) and a nitride film (up to 500 mm), and a metal-nitride-oxide-semiconductor (MNOS) ) Structure FET. Fig. 12 shows n-channel MNOS
FIG. 3 is a diagram illustrating a cross-sectional structure of a memory cell. As shown in FIG. 12, in the MNOS memory 1, for example, boron (B) is deposited on an n-type Si substrate 2 and then thermally diffused to form a p-well 3, and then phosphorus (P) is implanted to become a source and a drain. The n ⁺ diffusion layers 4 and 5 are formed. Thereafter, a thin SiO ₂ oxide film 6 is deposited thereon by, for example, thermal oxidation, and is removed while leaving just below a control gate 12 (described later). Next, the insulating layer 7,
A selection gate 8, an isolation gate 9, an insulating layer 10, a silicon nitride film 11, and a memory gate (control gate) 12 are formed.

Writing of data in the MNOS memory 1 is performed by the n ⁺ diffusion layer 4
This is performed by sending electrons (or holes) through the thin oxide film 6 to the nitride film 11 by tunneling.
Of the electrons transferred to the nitride film 11, deep energy levels (traps) existing at the oxide film-nitride film interface and in the nitride film 11
What contributes to data retention. It is known that not only traps for electrons but also traps for holes exist in the nitride film 11, and writing can be performed by tunneling holes by setting the voltage of the selection gate 8 to negative. Note that a voltage pulse of about 25 V (up to 10 msec) is applied for writing. In this way,
The written MNOS memory 1 has a high threshold voltage.

On the other hand, erasure of data in the MNOS memory 1 is performed by applying a voltage pulse having a polarity opposite to that of writing to the selection gate 8. Since it is necessary to drive out the electrons captured at the energy level, it is necessary to apply a pulse (for example, −30 V, 100 msec) higher in voltage and wider than the write pulse.

FIG. 13 is a diagram showing a write / erase driving method of the MNOS memory 1 using the p-well 3, and FIG. 13 (A) shows an equivalent circuit of the MNOS memory 1 of FIG. In the drawing, assuming that Vp indicates a write / erase voltage and Vo _N indicates a voltage at which a select gate opens, a write / erase control as shown in FIGS. Is realized.

[Problem to be solved by the invention] However, in such a conventional EEPROM,
Since a p-well 3 is formed in the Si substrate 2 and an nch transistor having a memory gate 12 having an MNOS structure is formed thereon to constitute a memory transistor, this is only an extension of the MOS transistor manufacturing process technology. , P-
Since it is necessary to form a diffusion region such as well3, it is difficult to increase the area.

As a driving method at the time of writing / erasing, as shown in FIG. 13, in addition to the source / drain and the selection gate 8 and the memory gate 12, the potential of the p-well 3 is also used, so that the number of electrodes is large and control is also performed. There was a problem that it was complicated.

The present invention has been made in view of the above circumstances,
It is an object of the present invention to provide a thin film transistor memory formed of a thin film semiconductor having a large area and capable of writing and erasing effectively.

Means for Solving the Problems In order to achieve the above object, a thin film transistor memory according to the present invention has a first select gate electrode, a select gate insulating film located above the first select gate electrode, and the select gate. A first selection thin film transistor comprising a source electrode and an intermediate source electrode respectively provided above an insulating film, and a semiconductor layer provided between the source electrode and the intermediate source electrode, for selecting and deselecting writing A second select gate electrode, the select gate insulating film located above the second select gate electrode, a drain electrode and an intermediate drain electrode respectively provided above the select gate insulating film, A semiconductor layer provided between the drain electrode and the intermediate drain electrode,
A second selection thin film transistor for performing selection and non-selection of writing, and the intermediate source electrode, the intermediate drain electrode, and the intermediate source electrode which are located between the first selection thin film transistor and the second selection thin film transistor; A semiconductor layer provided between the intermediate drain electrode, a memory gate insulating film provided above the semiconductor layer, and a memory gate electrode provided above the memory gate insulating film, And a memory transistor for writing and erasing.

That is, the thin film transistor according to the present invention is configured such that a memory transistor is provided via an intermediate source electrode and an intermediate drain electrode in response to a high potential and a low potential applied to a source electrode of a first selection thin film transistor and a drain electrode of a second selection thin film transistor. Since the method of injecting electrons or holes into the memory gate insulating film of (1), it is possible to efficiently inject carriers on the opposite side during writing and erasing, thereby enabling a large area. . In this case, in the present invention, since the p-well potential is not required, driving becomes simple.

Examples Hereinafter, the present invention will be described with reference to the drawings.

1 to 11 are views showing a first embodiment of a thin film transistor memory according to the present invention, and FIGS. 1 to 5 are manufacturing process diagrams of the thin film transistor memory.

First, as shown in FIG. 1, a conductive layer made of, for example, chromium (Cr) is deposited on an insulating substrate 21 made of glass or the like by sputtering or the like, and is patterned to form a first selection gate of the selection transistor Tr11. An electrode 22 and a second select gate electrode 23 are formed.

Next, as shown in FIG. 2, the first selection gate electrode
Insulating substrate on which 22 and second select gate electrode 23 are formed
A selective gate insulating film 24 made of stoichiometric silicon nitride (Si ₃ N ₄ ) is deposited over the entire surface of 21 by a plasma CVD method or the like, and then, for example, chromium (Cr) or the like is formed on the selective gate insulating film 24. And an n-type ohmic contact semiconductor layer made of polysilicon (poly-Si) doped with an impurity such as phosphorus (P).
By patterning, a source electrode 25, a drain electrode 27, an intermediate source electrode 29 and an intermediate drain electrode 30 are formed, and n-type ohmic contact layers 26, 28, 31, and 3 are formed on the respective electrodes.
Form 2.

Next, as shown in FIG. 3, amorphous silicon (a-type) is formed on the select gate insulating film 24 on which the drain electrode 25, the source electrode 27 and the intermediate source / drain electrodes 29, 30 are formed.
After depositing Si), the semiconductor layer 33 is formed by patterning. In this case, phosphorus-doped polysilicon (poly-S
When i) is used as the ohmic contact layers 26, 28, 31, and 32, the write / erase operation of the memory can be performed for both the p-channel operation and the n-channel operation, which are the operation characteristics of the transistor. is there.

Thereafter, silicon nitride (Si ₁ N ₁ ) having a charge storage function is deposited thinly (about 100 °) on the semiconductor layer 33, and then, as shown in FIG. 4, silicon nitride (Si ₁ N ₁ ) is formed on the intermediate source / drain electrodes 29 and 30. The memory nitride film 34 is formed by etching Si ₁ N ₁ ) so as to leave only a portion facing a memory gate electrode 36 described later. The memory nitride film 34 is formed of silicon nitride in which the composition ratio Si / N of silicon atoms Si and nitride atoms N is larger than the stoichiometric ratio of the select gate insulating film 24.

Next, as shown in FIG. 5, a memory gate insulating film 35 made of silicon nitride having the same stoichiometric ratio as the select gate insulating film 24 is formed over the entire surface of the semiconductor layer 33 by a plasma CVD method or the like. After depositing a conductive layer of chromium or the like thereon, patterning is performed, and a memory gate electrode 36 of the memory transistor Tr10 is formed at a position facing the memory nitride film 34 to complete the thin film transistor.

Thin film transistor memory manufactured as described above
Reference numeral 20 denotes a source electrode 25 and a drain electrode 27 in which one memory cell is electrically connected to the semiconductor layer 33;
Floating source / drain electrodes 29 and 30 formed between the first and second selection gate electrodes 22 and 30 to which a selection voltage for controlling writing selection / non-selection is applied. A gate electrode 23 and a memory gate electrode to which a gate voltage for moving a predetermined carrier is applied
36, the first select gate electrode 22, the select gate insulating film 24, the source electrode 25, the intermediate source electrode 29, and the semiconductor layer 33 are combined with the first select transistor Tr11.
The second select gate electrode 23, the select gate insulating film
24, drain electrode 27, intermediate drain electrode 30, and semiconductor layer
33, a second selection transistor Tr12 is formed, and the memory gate electrode 36, the memory nitride film 34, the intermediate source / drain electrodes 29, 30 and the semiconductor layer 33 form a memory transistor Tr10. That is, the thin film transistor memory 20 includes a first selection transistor Tr11, a memory transistor Tr10,
The second selection transistor Tr12 has a structure in which three transistors are arranged in series. The first selection transistor Tr11 and the second selection Tr operate in one channel, and the memory transistor Tr10 operates in both channels. It is configured.

6 and 7 show V _G − of the thin film transistor memory 20.
FIG. 9 is a diagram showing _ID (gate voltage-drain current) characteristics;
Figure 6 is a V _G -I _D characteristic of the first selection transistor Tr11 and a second selection transistor Tr11, FIG. 7 shows respectively the V _G -I _D characteristic of the memory transistor Tr10. First selection transistor Tr11 and second selection transistor Tr12
6 operates on the n-channel side as shown in FIG. 6, and the p-channel side has a characteristic of easily cutting off such that no current flows. As a result, the selection transistors Tr11, Tr12
Have a characteristic that a selection / non-selection operation can be easily performed.

On the other hand, the memory transistor Tr10 has a memory gate electrode 36 and intermediate source / drain electrodes 29, 30 as shown in FIG.
Both holes and electrons can be used as carriers depending on the direction of the electric field between them, so that both the n-channel side and the p-channel side operate. In this case, since phosphorus-doped polysilicon (poly-Si) is used for the ohmic contact layers 26, 28, 31, 32 between the metal film for the metal electrode and the semiconductor layer 33,
Neither the p-channel nor the n-channel conduction is a barrier that hinders writing / erasing of the memory. Therefore, when an appropriate bias is applied to the memory gate electrode 36, the source electrode 25, and the drain electrode 27 as described below, data erasing / writing is realized.

8 to 11 show the erasing / writing of the thin film transistor memory 20.
FIG. 4 is a diagram showing a write operation.

Although FIGS. 8 to 11 show one thin film transistor memory 20, a plurality of thin film memories 20 are actually formed in a matrix.

The memory nitride film 34 shown in FIG.
It is assumed that the thickness and the like of the memory nitride film 34 and the gate insulating film 35 are formed so that holes h ⁺ or electrons e ⁻ are trapped when Vp is applied to perform erasing / writing.

Erasing (injection of holes h ⁺ into the memory nitride film 34) is performed by applying a negative bias (ground level in this embodiment) to the memory gate electrode 36 as shown in FIG. By applying a positive bias to the electrode 27 and applying a positive bias to the floating intermediate source / drain electrodes 29 and 30, holes (see FIG. 8 h ⁺ ) are trapped in the memory nitride film 34. Do. Now, grounding the memory gate electrode 36, source electrode 25 and drain electrode 27 of the memory Vp, when the first selection gate electrode 22 and the second select gate electrode 23 at the time of erasing selected partial pressure Vo _N -Er The first selection transistor Tr11 and the second selection transistor Tr12 bias the intermediate source / drain electrodes 29, 30 of the memory to Vp in one-channel (n-channel) operation.
As a result, the potential of the intermediate source / drain electrodes 29 and 30 of the memory transistor Tr10 becomes higher than the potential of the memory gate electrode 36 by Vp. The holes h ⁺ are emitted toward the film 34. Therefore, as shown in FIG. 8, the holes h ⁺ are trapped in the memory nitride film 34.
Erasure is performed in 1-bit units.

Erasing not selected For thin film transistor memory that you do not want to erase,
As shown in FIG. 9, when the first selection gate electrode 22 and the second selection gate electrode 23 are set to the non-selection voltage Voff-Er, the first selection transistor Tr11 and the second selection transistor Tr12.
Since the channel portion of the memory transistor Tr1 is in a high impedance state, a potential difference substantially equal to Vp applied to the source electrode 25 and the drain electrode 27 between the intermediate source / drain electrodes 29 and 30 of the floating memory transistor Tr10 is generated. Arises
Since the potential difference hardly appears at both ends of the memory nitride film 34, the state inside the memory nitride film 34 is maintained. in this case,
Select gate electrode to keep data in the previous state
The erase pulse application time to be applied to 22, 23 is the time during which data can be sufficiently rewritten at the time of selection, and the application is completed before a large potential difference occurs at both ends of the memory during the non-selection time. It is necessary to design a memory cell in advance.

Writing Next, writing will be described.

In writing (electron e ^- injection into the memory nitride film 34), when the cell is selected at the time of writing, a positive bias is applied to the memory gate electrode 36 and the source electrode 25 and the drain electrode 27 are applied as shown in FIG. A negative bias (ground level in this embodiment) is applied. Then, the selection / non-selection of writing of the thin film transistor memory is determined by the thin film transistors Tr11 and Tr1.
2 n-channel ON / OFF operation (first select gate electrode 2
(2, ON / OFF of the second selection gate electrode 23) to control the flow of electrons e ⁻ . Now, as shown in FIG.
When Vp is applied to the memory gate electrode 36 and the source electrode 25 and the drain electrode 27 are grounded, the potential difference Vp between the floating intermediate source / drain electrodes 29 and 30 and the memory gate electrode 36 is determined by the memory transistor. Tr10 intermediate source / drain electrodes 29, 30 and memory gate electrode 36
Between the two ends of the memory nitride film 34.
Vp is applied and the intermediate source of the memory transistor Tr10
Electrons e ⁻ are injected and written from the drain electrodes 29 and 30. Accordingly, electrons e as shown in FIG. 10 ^- a memory nitride film
Flows to 34, the memory nitride film 34 electrons e ^- is the charge
Writing is performed in 1-bit units.

Write non-selection When write is not selected, as shown in FIG. 11, when the first select gate electrode 22 and the second select gate electrode 23 are set to the write non-select voltage Voff-Wr, the first select transistor Tr11 and the select transistor Tr12 Since the channel section is in a high impedance state, the intermediate source / drain electrodes 29, 30 of the memory transistor Tr10 are set for a short write pulse application time.
, Vp approximately equal to Vp applied to the memory gate electrode 36 appears, and a potential difference hardly appears at both ends of the memory nitride film 34. Therefore, the state inside the memory nitride film 34 is maintained. However,
In order for this to be true, the memory cell is connected to the input impedance of the memory transistor Tr10 and the selection transistor Tr1.
1. It is necessary to design the output impedance when Tr12 is not selected in accordance with the write pulse application time.

As described above, while the select transistors Tr11 and Tr12 operate only in the n-channel mode, a bias is applied to the intermediate source / drain electrodes 29 and 30 of the memory transistor Tr10 that operates in both the p-channel and the n-channel directions. e ⁻ and holes h ⁺ can be efficiently supplied to the interface of the memory nitride film 34 at the time of erasing. As described above, in this embodiment, the thin film transistor 20 has a structure in which three transistors, the first selection transistor Tr11, the memory transistor Tr10, and the second selection transistor Tr12, are arranged in series in the channel direction. Select transistor Tr11 and second select transistor Tr12 perform one-channel operation, and
Since Tr10 is configured to operate on both channels,
On the transistor Tr11 and Tr12 side, it is possible to prevent data from fluctuating when not selected, and on the memory transistor Tr10 side, since both channels operate, the reverse carrier injection can be performed efficiently. Also, the source electrode 2
5, it is possible to electrically selectively write / erase the inside of the memory array only with the four terminals of the drain electrode 27, the select gate electrodes 22 and 23, and the memory gate electrode 36.

In particular, performs selection / non-selection of the write and erase the selection transistors Tr11, Tr12 to operate single-channel (n-channel), when writing from the intermediate source and drain electrodes 29, 30 of the memory transistor Tr10 electron e ^- the injection of, Hole h when erasing
^{Since the +} implantation is performed in the direction of the electric field between the intermediate source / drain electrodes 29 and 30 and the memory gate electrode 36,
The speed can be increased as compared with a memory having a conventional structure in which p-channel erasing / n-channel writing cannot be performed. Further, even if the structure is such that the p-channel erase / n-channel write is possible, if the select transistors Tr11 and Tr12 are used for performing both channel operations, the select transistors Tr11 and Tr1
The non-selection voltage of 2 has a width, and the working voltage also needs to be greater than the threshold voltage Vthp, Vthn of the transistor Tr11.However, the thin film transistor of the present invention only needs to satisfy nth channel Vth. Has a small amplitude.

Further, since the memory gate portion and the selection gate portion are completely separated as a transistor, a photolithography step for separating a memory nitride film for a memory transistor as a region is not required. Even if the film 34 covers the entire plane, it does not affect the memory characteristics.

Furthermore, the selection transistor Tr is included in one memory cell.
Since the transistor Tr11 and the memory transistor Tr10 are integrated, the manufacturing process can be greatly simplified, and high integration and large area can be realized by integrating them. it can.

[Effects of the Invention] According to the present invention, the memory of the memory transistor is connected via the intermediate source electrode and the intermediate drain electrode in response to the high potential and the low potential applied to the source electrode and the drain electrode of the first selection transistor. Since electrons or holes are injected into the gate insulating film for use, carriers on the opposite side can be efficiently injected in writing and erasing, thereby increasing the area. In this case, in the present invention, since the p-well potential is not required, driving becomes simple.

[Brief description of the drawings]

Figure 1 - FIG. 11 is a diagram showing an embodiment of a thin film transistor memory according to the present invention, FIG. 1-FIG. 5 is a manufacturing process view of the thin film transistor memory, FIG. 6 is V _G -I selection transistor _D characteristic diagram, FIG. 7 is a memory transistor V _G -
I _D characteristic diagram, drawing for Figure 8 is for explaining the movement of the carrier at the time of erasing, FIG. 9 is a diagram for explaining an operating state during erase unselected, Fig. 10 move at the time of writing career FIG. 11 is a diagram for explaining an operation state when writing is not selected, FIG. 12 is a diagram showing a cross-sectional structure of a conventional thin film transistor memory, and FIG. 13 is a driving of the conventional thin film transistor memory It is a figure showing a method. Tr10: memory transistor, Tr11: selection transistor, Tr12: second selection transistor, 20: thin film transistor memory, 21: insulating substrate, 22: first selection gate electrode, 23: second Select gate electrode, 24 ... Select gate insulating film, 25 ... Source electrode, 27 ... Drain electrode, 29, 30 ... Intermediate source / drain electrode, 33 ... Semiconductor layer, 34 ... Memory nitride film, 35 ... ... memory gate insulating film, 36 ... memory gate electrode.

Continuation of the front page (51) Int.Cl. ⁷ Identification symbol FI H01L 29/792 (56) References JP-A-2-114570 (JP, A) JP-A-4-61282 (JP, A) JP-A-4 -61281 (JP, A) JP-A-62-14473 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8247 G11C 17/00 H01L 27/115 H01L 29/786 H01L 29/788 H01L 29/792

Claims (1)

(57) [Claims] A first selection gate electrode, a selection gate insulating film located above the first selection gate electrode, a source electrode and an intermediate source electrode provided above the selection gate insulating film, respectively. A first selection thin film transistor, comprising: a semiconductor layer provided between the source electrode and the intermediate source electrode, for selecting and deselecting writing; a second selection gate electrode; and the second selection gate The select gate insulating film located above an electrode, a drain electrode and an intermediate drain electrode respectively provided above the select gate insulating film, and a semiconductor layer provided between the drain electrode and the intermediate drain electrode. A second selection thin film transistor for selecting and deselecting a write, and the first selection thin film transistor and the second selection thin film Located between the transistors, and the intermediate source electrode,
The intermediate drain electrode, a semiconductor layer provided between the intermediate source electrode and the intermediate drain electrode, a memory gate insulating film provided above the semiconductor layer, and a memory gate insulating film provided above the memory gate insulating film. And a memory transistor for writing and erasing, comprising: a memory gate electrode provided;