JP3182811B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a technique for precharging a data input / output line for transmitting data on a bit line.

[0002]

2. Description of the Related Art First, the structure of a conventional semiconductor memory device will be described with reference to FIG. FIG. 5 shows only a pair of bit lines B0 and B1 and one memory cell CL for simplicity.

In FIG. 5, a pair of bit lines B0 and B1 are connected to a sense amplifier SA for amplifying the potential difference.
The bit line pair B0, B1 is connected to data input / output lines I / O0, I / O1 for transmitting a potential difference between bit lines via N-channel MOS transistors Q1, Q2.

[0006] φ1 is an N-channel MOS transistor Q
1, a signal for controlling ON / OFF of Q2, and φ2, φ3 are activation signals of the sense amplifier SA. φ4 is a control signal for turning on / off the connection between the memory cell CL and the bit line.

[0005] N-channel MOS transistors Q1, Q2
Is connected to a pair of bit lines B0, B1 and data input / output lines I / O0, I / O1 for transmitting a difference potential therebetween, and the data input / output lines I / O0, I / O1 are supplied with the precharge potential. A P-channel MOS transistor Q3 functioning as a balancer 3 for equalizing, P-channel MOS transistors Q4 and Q5 forming a precharge control circuit 4,
A data amplifier DA for amplifying a difference potential generated between the data input / output lines I / O0 and I / O1 is connected.

[0006] φ5 is an activation signal of the data amplifier DA, φ
6, φ7 are output signals of the data amplifier DA, and signals for controlling precharge of the φ8 data input / output line.

An N-channel MOS transistor, Q6,
Q7 and Q8 constitute a power supply circuit 5 for supplying power to the precharge control circuit 4 of the data input / output line.

Next, the operation of the conventional example will be described. 6 and 7
6 is a timing chart showing an outline of the operation of the conventional example shown in FIG. First, a case where the conventional example is in an inactive state will be described. The control signal φ4 is at a low potential, and the memory cell CL and the bit line B1 are off. The activation signals φ2 and φ3 are intermediate potentials between the power supply potential VCC [V] and the ground potential (VCC / 2).
[V], and the sense amplifier circuit SA is in an inactive state. The bit line pair B0, B1 maintains the intermediate potential. Since the control signal φ1 maintains the low potential, the bit line pair B0, B
1 and the data input / output lines I / O0 and I / O1 are off.

Since the control signal φ8 is at a low potential and the P-channel MOS transistors Q4 and Q5 are on, the data input / output lines I / Oo and I / O1 are supplied by the precharge power supply circuit 5 to (VCC-VTQ6). ) [V] is precharged. Here, VTQ6 is the threshold voltage of the N-channel MOS transistor Q6. P channel MOS transistor Q3 is also on, and data input / output line I /
O0 and I / O1 are connected and the data input / output line I / O0
And I / O1 are compensated for.

The control signal φ5 is at a low potential, the data amplifier DA is inactive, and the output of the data amplifier DA is at an intermediate potential.

Next, when the semiconductor memory device is activated, the control signal φ4 changes to a high potential at time 61 to turn on the connection between the memory cell CL and the bit line B1, and the potential of B1 is set by the potential of CL. Changes to the bit line B0.
And B1 produce a small potential difference. Here, it is assumed that the memory cell CL is set to a low potential.

After a potential difference occurs between the bit lines B0 and B1, at time t2, the activation signal φ2 changes from the intermediate potential to a high potential, the activation signal φ3 changes from the intermediate potential to a low potential, and the sense amplifier circuit SA It is activated, and the small potential difference between B0 and B1 is amplified.

Thereafter, the control signal φ1 becomes high, the N-channel MOS transistors Q1 and Q2 turn on, and the bit lines B0 and B1 are connected to the data input / output lines I / O0 and I / O1 (time t3). . Next, the control signal φ8 goes high at time t4, and the P-channel MOS transistors Q4, Q5,
When Q6 turns off and the pre-charging and balance of the data input / output lines I / O0 and I / O1 are completed, the bit lines B0,
The data input / output lines I / O0 and I / O1 correspond to the potential of B1.
Changes.

After the potentials of data input / output lines I / O0 and I / O1 change, at time t5 activation signal φ5 goes high,
When the data amplifier DA is activated, the data input / output line I
The differential potential on / O0 and I / O1 is amplified and the output signal φ6,
φ7 changes at time t6.

When the semiconductor memory device is deactivated again, φ1, φ4, φ5, φ8 have a low potential, and φ2, φ3 have an intermediate potential.

Precharging of the data input / output lines I / O0 and I / O1 is started when the control signal φ8 becomes low potential (time t8). This precharging is performed when the semiconductor memory device is activated. , Φ1 change from a low potential to a high potential, and the potentials of the bit lines B0, B1 are
The current drive capability of the N-channel MOS transistor Q6 is set large with a margin since it must be completed before it is transmitted to / O0 and I / O1.

Even when the power supply potential fluctuates during the data input / output line precharge period, especially when the power supply potential decreases, the precharge potential of the data input / output line is set to (VCC-VTQ6) [V].
Therefore, the capacity of the N-channel MOS transistors Q7 and Q8 needs to be set with a margin so that the potential of the data input / output line also decreases in accordance with the decrease of the power supply potential.

[0018]

The above-mentioned conventional semiconductor memory device has a power supply circuit 5 for precharging data input / output lines. As described above, the semiconductor memory device is designed to cope with fluctuations in power supply potential. Regardless of the active or inactive period,
There is a disadvantage that a steady current flows from the N-channel MOS transistor Q6 through the N-channel MOS transistors Q7 and Q8. In particular, the current drive capability of the N-channel MOS transistors Q6 to Q8 cannot be reduced in order to stabilize the precharge potential, and it is difficult to reduce the steady-state current.

Furthermore, in the conventional semiconductor memory device, the data input / output lines I / O
0, to reduce the potential of I / O1
The current driving capabilities of the S transistors Q7 and Q8 also need to be set in consideration of the fluctuation amount of the power supply potential and the current capability of the N-channel MOS transistor Q6, and have a drawback that it is difficult to set an optimum value.

[0020]

SUMMARY OF THE INVENTION The means for solving the problem] includes a plurality of memory cells, and connected bit line pair in the memory cell, the data input and output line pair connected to said bit line pair via a transfer transistor And the data input / output line pair
Is connected to a data line amplifier for amplifying a potential difference on the data output line pair, in a semiconductor memory device having a precharge circuit for precharging the data output line pair to the precharge potential, the precharge Means are
Wherein a first control circuit connected to the data output line pair to shift the potential of the data output line pair upon deactivation to the power supply potential, the potential of the data input and output line pairs upon activation pre
The data input for lowering to a predetermined potential lower than the charge potential.
A second control circuit connected to the output line pair, said data input and
Data potential force line pair to shift the potential of the data output line pair after reduced to a predetermined potential to the precharge potential input
And a third control circuit connected to the output line pair .

[0021]

When the semiconductor memory device is inactive, the first
When the control circuit fixes the data input / output line pair to the power supply line and is activated, the third control circuit, together with the second control circuit, once lowers the potential of the data input / output line pair once the second control circuit lowers the potential. The data input / output line pair is shifted to the precharge potential.

[0022]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In FIG. 1, B0 and B1 are bit line pairs, and the bit line pair B0 and B1 is a memory cell CL and bit lines B0 and B0.
It is connected to a sense amplifier circuit SA for amplifying a difference potential between B1 and sources of N-channel MOS transistors Q1 and Q2 for transmitting data input / output lines I / O0 and I / O1 on a bit line pair.

A control signal φ1 controls on / off of N-channel MOS transistors Q1 and Q2, and an activation signal φ
2 and φ3 activate the sense amplifier circuit SA. The control signal φ4 turns on / off the connection between the memory cell CL and the bit line.

N channel MOS transistors Q1, Q2
Are connected to data input / output lines I / O0 and I / O1, and the data input / output lines I / O0 and I / O1 function as balancers 3 for equalizing the precharge potentials of both data input / output lines. P-channel MOS transistor Q
3, and P-channel MOS transistors Q4A, Q4A, for making the data input / output lines I / O0, I / O1 equal to the power supply potential.
Q4B (precharge control circuit 4) and data input / output line I
N-channel MOS transistors Q6A and Q6B (precharge control circuit 6) for lowering the potentials of / O0 and I / O1 to predetermined potentials, and for setting data input / output lines I / O0 and I / O1 to a precharge potential. N-channel MOS transistors Q5A and Q5B (precharge control circuit 5)
It is connected to an input of a data amplifier circuit DA for amplifying a difference potential generated between data input / output lines I / O0 and I / O1.

Φ8, φ9, φ10, φ11 are N-channel MOS transistors Q6A, Q6B, Q5A, Q5B, Q4, respectively.
A control signal for controlling ON / OFF of A, Q4B, Q3,
The activation signal φ5 activates the data amplifier. φ6 and φ7 are outputs of the data amplifier DA.

Next, the operation of the first embodiment will be described. Figure 2
FIG. 3 is a timing chart showing an outline of the operation of the first embodiment.

When the semiconductor memory device according to the first embodiment is in an inactive state, the control signal φ4 is at a low potential, and the memory cell CL and the bit line B1 are off. The activation signals φ2 and φ3 maintain the intermediate potential (VCC / 2) [V],
The sense amplifier circuit SA is in an inactive state. The bit line pair B0, B1 is also precharged at the intermediate potential. Also,
The control signal φ1 is at a low potential, and the N-channel MOS transistors Q1 and Q2 are off. The control signals φ8 and φ9 are at a low potential, and Q6A, Q6B, Q5A and Q5B are off. On the other hand, the control signals φ10 and φ11 are at a low potential and the P-channel MOS transistors Q4A, Q4B and Q3 are on, so that the data input / output lines I / O0 and I / O1 are equal to the power supply potential. The activation signal φ5 is at a low potential,
Data amplifier DA is inactive. Therefore, the outputs φ6 and φ7 are at the intermediate potential.

When the semiconductor memory device is activated, φ
10 becomes high potential at time t11, the P-channel MOS transistors Q4A and Q4B are turned off, and the control signal φ8 at time t12.
Becomes high potential, the N-channel MOS transistor Q6
When A and Q6B are turned on, the data input / output lines I / O0 and I / O
The potential of / O1 is gradually lowered from the power supply potential to a predetermined potential. In the first embodiment, the predetermined potential is (VCC-V
TQ5) The potential is equal to or lower than [V]. Here, VCC is the power supply potential VTQ5 and the threshold voltage of the N-channel MOS transistors Q5A and Q5B.

Thereafter, at time t15, the control signal φ8 goes low, the N-channel MOS transistors Q6A, Q6B turn off, and at time t16, the control signal φ9 goes high, turning on the N-channel MOS transistors Q5A, Q5B. As a result, the potential of the data input / output lines I / O0 and I / O1 lowered to the predetermined potential is raised to (VCC-VTQ5) [V], and the data input / output lines I / O0 and I / O1 are precharged. The operation is completed.

In parallel with the series of precharge operations, at time t13, the control signal φ4 becomes high potential, the memory cell CL is connected to the bit line B1, and the potential of the bit line B1 is changed by the potential of the memory cell CL. Change and the bit lines B, B1
, A small difference potential is generated. At time t14, the activation signal φ2
Becomes high potential and the activation signal φ3 becomes low potential, so that the sense amplifier circuit SA is activated and the minute difference potential is amplified.

The precharge of the data input / output lines I / O0 and I / O1 is set to be completed before the difference potential on the bit lines B0 and B1 is amplified.

Thereafter, at time t17, the control signal φ1 goes high, turning on the N-channel MOS transistors Q1, Q2. In advance, when the control signal φ9 becomes low potential,
N-channel MOS transistors Q5A and Q5B turn off,
Since the control signal φ11 has a high potential and the P-channel MOS transistor Q3 is off, the potentials of the bit lines B0 and B1 are transmitted to the data input / output lines I / O0 and I / O1, and the data input / output lines I / O0, The potential on I / O1 changes.

When the activation signal φ5 becomes high potential at time t18 and the data amplifier DA is activated, the potentials of the data input / output lines I / O0 and I / O1 are amplified and output as outputs φ6 and φ7. You.

When the semiconductor memory device is deactivated again, the control signals φ1, φ4, φ5, φ10, φ11 become low potential,
The activation signals φ2 and φ3 have an intermediate potential. Control signal φ10,
When φ11 becomes low potential, the data input line I / O
0 and I / O1 become equal to the power supply potential. Therefore, in the first embodiment, during the inactive period of the semiconductor memory device,
The configuration is such that the data input / output line potential is set equal to the power supply potential for any power supply potential fluctuation.

FIG. 4 is a block diagram showing a second embodiment of the present invention. In the second embodiment, a plurality of data input / output line pairs I
/ O0 to I / O3 are connected to the data amplifier 2 through the selectors 7A and 7B. In FIG. 4, B0 to B3 are bit line pairs, CL1 and CL2 are memory cells, S
A1 and 2 are sense amplifier circuits for amplifying a minute difference potential generated between the bit lines B0 / B1, B2 / B3, Q1A, Q2A, Q1B,
Q2B is an N-channel MOS transistor for controlling on / off of the connection between the bit line and the data input / output line.

The control signal φ4 turns on / off the connection between the memory cells CL1,2 and the bit lines B1,3, and the activation signal φ2,
φ3 activates the sense amplifier circuits SA1 and SA2. The control signal φ1 includes N-channel MOS transistors Q1A, Q2
Controls ON / OFF of A, Q1B and Q2B.

Q3A and Q3B are data input / output lines I /
It is a P-channel MOS transistor for equalizing the precharge potentials of O0, I / O1, I / O2 and I / O3, and receives a control signal φ11. Q4 is a data input / output line I / O0 to I / O3 when the semiconductor memory device is inactive.
And a power supply, and is controlled by a control signal φ10. Q6 is an N-channel MOS transistor for once lowering the data input / output line potential to a predetermined potential when the semiconductor memory device is activated, and is controlled by a control signal φ8. Q7A, Q8
A, Q7B and Q8B are P-channel MOS transistors for turning on / off the connection between the common drain of the MOS transistors Q4 and Q6 and the data input / output lines I / O0 to I / O3, and are controlled by a control signal φ12. You. N-channel MOS transistors Q5A, Q6A, Q5B, and Q6B control the potential of data input / output lines I / O0-I / O3, which have been lowered from a power supply potential to a predetermined potential when the semiconductor memory device is activated, to a precharge potential. Constituting the circuits 5A and 5B,
These are controlled by control signals φ9 and φ9 ', respectively. MOS
Transistors Q9A, Q10A, Q9B, Q10B constitute selector circuits 7A, 7B, and have data input / output lines I / O0, I / O1.
Alternatively, the potential of either I / O2 or I / O3 is transmitted to the input of the data amplifier 2. Control signal φ1
3, φ14 are select signals, and an activation signal φ5 activates the data amplifier.

As described above, according to the second embodiment of the present invention, when the semiconductor memory device is constituted by a plurality of data input / output line pairs, the data input / output lines are set equal to the power supply potential when the semiconductor memory device is inactive. P channel MO to do
The S transistor Q4 and the N-channel MOS transistor Q6 for once lowering the data input / output line to a predetermined potential when the semiconductor memory device is activated are shared by a plurality of data input / output line pairs. The outline of the operation of the second embodiment is the same as that of the first embodiment, and a description thereof will be omitted.

FIGS. 8 and 9 show the conventional circuit and the potential change of the data input / output lines I / O0 and I / O1 when the power supply potential fluctuates in this embodiment.

FIG. 8 shows the case where the variation of the power supply potential is relatively small, and FIG. 9 shows the potential change of the data input / output lines I / O0 and I / O1 when the variation of the power supply potential is relatively large. . 8 and 9, reference numeral 1 denotes a power supply potential, and reference numerals 2 and 3 denote first to first power supply potentials.
The potentials of the data input / output lines I / O0 and I / O1, 4 and 5 shown in the second embodiment are the data input / output lines I / O0 and I / O of the conventional circuit.
The potential change of O1 is shown. 8 and 9, a
Is the activation time of the semiconductor memory device, b is the completion time of the precharge operation of the data input / output lines I / O0 and I / O1 in the first and second embodiments, and c is the data input / output line in the conventional circuit in FIG. The precharge operation completion time of I / O0 and I / O1 is indicated by d, and the precharge operation end time in FIG. 9 is indicated. Reference numeral 6 denotes N-channel MOS transistors Q5A and Q5B of the first embodiment, and MOS transistors Q5A and Q5A of the second embodiment.
9 shows threshold voltages of Q5B, Q6A, Q6B and a MOS transistor Q6 in the conventional example. As apparent from FIGS. 8 and 9, in the semiconductor memory device according to the present invention,
Since the precharge operation of the data input / output lines I / O0 and I / O1 can be performed with reference to the power supply potential at the activation time of the semiconductor memory device, the conventional circuit shown in FIGS.
The data input / output line precharge completion time hardly fluctuates due to the fluctuation amount of the power supply potential indicated by c and d, and a stable precharge operation can be performed with respect to the power supply potential fluctuation.

[0042]

As described above, according to the present invention, the potential of the data input / output line is set to the power supply potential when the semiconductor memory is inactive.
When the semiconductor memory is activated, the potential is once reduced to a predetermined potential and then set to the precharge potential, so that there is an effect that a through current during deactivation can be prevented.

Further, in the present invention, when the semiconductor memory device is inactive, the data input / output line is always set to the power supply potential, and the precharge operation of the data input / output line is set based on this power supply potential. It is possible to obtain an effect that the design becomes easy.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the first embodiment of the present invention.

FIG. 3 is a timing chart showing the operation of the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a conventional example.

FIG. 6 is a timing chart showing the operation of the conventional example.

FIG. 7 is a timing chart showing the operation of the conventional example.

FIG. 8 is a graph showing a voltage change according to an embodiment of the present invention and a conventional example.

FIG. 9 is a graph showing voltage changes according to an embodiment of the present invention and a conventional example.

[Explanation of symbols]

 B0, B1 bit line pair CL memory cell SA sense amplifier I / O0 to I / O1 data input / output line pair 3, 4 control circuit (first control circuit) 6 control circuit (second control circuit) 5 control circuit (third Control circuit) 2 Data amplifier

Claims (2)

(57) [Claims] [1 claim: a plurality of memory cells, and connected bit line pair in the memory cell, and data input and output line pair connected to said bit line pair via a transfer transistor, before
Is connected to the serial data input and output line pair, a data line amplifier for amplifying a potential difference on the data output line pair, said data input and
In the semiconductor memory device having a precharge circuit for precharging the force line pair to the precharge potential, the flop <br/> recharge means, the data output line pair upon deactivation
Connected to the data input / output line pair that shifts the potential to the power supply potential.
A first control circuit, the data output line pair when activated
A second control circuit connected to the data input / output line pair for lowering the potential of the data input / output line pair to a predetermined potential lower than the precharge potential, and the potential of the data input / output line pair dropped to the predetermined potential.
The semiconductor memory device, wherein a potential of the data output line pair and a third control circuit coupled to said data input and output line pair to shift to the precharge voltage after. Wherein said first control circuit is composed of the balancing transistor connecting the one-to-charging transistor of which is provided between said power line said data input and output line to said data input and output line pairs is, the second control circuit is constituted by a pair of discharge transistor provided between the ground line the data output line pair, said third control circuit and the power supply line the data output line pair 2. The semiconductor memory device according to claim 1, comprising a pair of charging transistors provided between the first and second transistors.