JP3185207B2 - Data processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing system, and more particularly, to a data processing system for operating a microprocessor and an external device with maximum performance.

[0002]

2. Description of the Related Art Generally, a data processing system includes a microprocessor (MPU) and a ROM (read only memory) containing a program for operating the microprocessor and a RAM (random access memory) for storing data to be processed.
And peripheral devices including other hard disks and communication devices. A data processing system exchanges data between a microprocessor and a peripheral device (external device) via an address bus or a data bus connected to the microprocessor (these buses are also collectively referred to as a system bus). To perform a desired process.

Conventionally, a microprocessor and a peripheral device exchange data with the same clock signal of about several tens of MHz. However, in recent years, there has been a remarkable increase in the speed of the MPU, and its operation clock frequency is several hundred MHz.
z has been reached. On the other hand, peripheral devices that operate at the same clock frequency as the MPU are not always developed. For this reason, the data processing system has to be designed with reference to the peripheral device having a low clock frequency, and the performance of the MPU cannot be sufficiently exhibited.

Normally, a microprocessor is divided into a plurality of stages to improve the processing performance, and has a so-called pipeline configuration so that each stage can execute an instruction. The pipeline of a microprocessor is designed so that one stage of processing is completed in one clock, and on average one instruction can be processed in one clock. Therefore, increasing the clock frequency of a microprocessor improves its processing capability.

[0005] The clock frequency of the microprocessor is
In order to solve the problem of being limited by the guaranteed maximum operation clock frequency of the peripheral device, a method of making the frequency of the operation clock inside the microprocessor an integral multiple of the clock frequency of the external bus is conventionally known. . Here, the guaranteed maximum operation clock frequency is not the ultimate clock frequency at which the device operates, but the maximum clock frequency at which the supplier of the device guarantees the operation of the device.

This microprocessor has a phase lock loop (PLL) circuit therein, and generates an internal clock having an integral multiple of the clock frequency of an external bus by using a PLL circuit. It is possible to operate with an internal clock having a higher frequency than the external clock.

[0007] The microprocessor has an input / output interface for exchanging data between an internal circuit and a peripheral device. The input / output interface generally transmits and receives data in synchronization with an external clock, and further exchanges data with an internal circuit in synchronization with an internal clock of the microprocessor. Internal clock and external clock are PLL
Synchronization is achieved by the circuit, and the rising timings coincide at certain intervals, so that signals can be transmitted and received without any problem.

[0008]

Heretofore, the frequency of the operation clock in the microprocessor has been an integral multiple of the external bus frequency. However, the guaranteed maximum clock frequency at which the microprocessor can operate is not always an integral multiple of the guaranteed maximum clock frequency of the peripheral device. For example, if the guaranteed maximum clock frequency of a peripheral device is 10
At 0MHz, the microprocessor's is 250MHz
Assume that In the data processing system described above, the microprocessor will operate at 200 MHz. However, in this case, the microprocessor
While having the ability to operate at Hz, it is not possible to maximize its ability.

Now, if the clock frequency of the peripheral device is assumed to be 10
Consider a case where the frequency is 0 MHz and the clock frequency of the microprocessor is 250 MHz. Normally, the input interface fetches data at the timing of the rising edge of the internal clock and passes the data to the inside of the microprocessor.

FIG. 16 is a timing chart for explaining the data transfer. 2A shows an external clock signal CLOCK, FIG. 2B shows data DATA, and FIG. 2C shows an internal clock PH1. Here, it is assumed that the external clock CLOCK has a cycle 2.5 times as long as the internal clock PH1, and one cycle of the external clock CLOCK is 10 ns. The data signal DATA is synchronized with the external clock signal CLOCK, and the value of the data DATA is determined at the time when the external clock CLOCK rises.

Here, the time from when the data signal DATA becomes valid to when the external clock signal CLOCK rises is called a setup time, and the time from when the external clock signal CLOCK falls to when the data signal DATA becomes invalid is set up. Called hold time. In the example of FIG. 16, the setup time is 1 ns and the hold time is 0.5 ns. In addition, the peripheral device has a time of 8.5 ns from the output of the data signal DATA (D0) to the output of the next data signal DATA (D1), during which time necessary processing is performed.

The operation of the input interface will be described with reference to FIG. The peripheral device outputs data D1 between times t5 and t6, and when the external clock CLOCK rises at time t6, the internal clock PH1 also rises in synchronization with this. The input interface fetches the data output from the peripheral circuit into the microprocessor at the rising edge of the internal clock PH1, so that the processing can be performed without any problem.

On the other hand, between time t0 and t1, the peripheral device outputs data D0, and at time t1, the external clock CLOCK is output.
Stand up. However, at time t1, the internal clock PH
Since 1 falls, the input interface cannot take in data, and waits until the next rise of the internal clock PH1 to take in data. The rise of the internal clock PH1 at time t2 is delayed by 2 ns from the rise of the external clock CLOCK at time t1. On the other hand, the hold time of the data DATA (D0) is only 0.5 ns as described above. Therefore, the microprocessor cannot take in the data DATA (D0).

To solve this problem, if the design of the peripheral device is changed so that the hold time is set to 2 ns or more, the data DATA can be fetched without any problem.
However, the peripheral device outputs 7n after outputting the data.
The processing for outputting the next data DATA must be completed during s (= 10-2-1). That is, the peripheral device must speed up the internal processing by 1.5 ns (= 8.5-7).

The above-mentioned problem arises because the peripheral device is not operated at high speed, and solving the problem by increasing the speed of the peripheral device contradicts this problem.

As described above, there is a demand that the external system and the inside of the MPU be operated at the highest performance, that is, at the highest frequency, so as to obtain the highest performance of the entire system. In order to realize this, it is highly desirable that the data signal can be correctly transmitted and received between the external system and the MPU even when the ratio of the external clock to the internal clock is a non-integer multiple.

[0017] In view of the above, the present invention has been made to solve the above problem even when the multiplication rate between the external clock and the internal clock is a non-integer multiple.
By absorbing the asynchrony between the U internal clock and the external clock, and properly transmitting and receiving signals between the MPU and the external, the MPU operates at the highest performance inside and outside the MPU, that is, at the highest frequency. An object of the present invention is to provide a data processing system capable of maximizing the performance of a data processing system.

[0018]

[0019]

[0020]

[0021]

[0022]

[0023]

In order to achieve the above object, a data processing system according to the present invention provides a data processing system in which input data sent from an external device in synchronization with an external clock is operated by an internal clock including an asynchronous cycle. A data processing system to be input to a processor, comprising: an input / output unit that captures the input data in synchronization with the external clock and outputs the input data in synchronization with the internal clock. A holding means for holding the input data until a predetermined timing that can be latched by the internal clock and inputting the data to the microprocessor is provided.

In the data processing system of the present invention, for example, even when the multiplication rate between the internal clock and the external clock is a non-integer multiple, the microprocessor is operated at the highest performance inside and outside the microprocessor, that is, at the highest frequency, and the whole system is The best performance can be obtained. For example, when the operating frequency by the internal clock has a ratio of a non-integer multiple of the external clock, a timing delay cycle occurs such that input data is latched every other clock of the external clock,
In some cases, the hold time of the input data is shortened, which may cause a problem in signal capture. However, since the holding unit holds the input data, the input data can be properly latched even in an asynchronous cycle in which the latch timing is delayed.

Further, the apparatus further comprises an input interface for receiving input data from the external device, and a timing generation circuit for generating a timing signal for adjusting a latch timing in the input interface. It is preferable to include an input holding register that latches in response to a timing signal, and an input latch that latches an output of the input holding register in response to a change in the level of the internal clock. In this case, the present data processing system can be obtained by a simple circuit configuration in which an input holding register is provided before the input latch.

More preferably, the input interface includes a plurality of first latch circuits for respectively latching input data sequentially input in synchronization with the external clock, and the plurality of first latch circuits operating in response to the internal clock. A second latch circuit for latching the output of the first latch circuit in the order of input of the original input data. This makes it possible to easily realize a circuit configuration corresponding to a clock whose multiplication factor is a non-integer multiple.

Preferably, a clock generation circuit is provided for generating an M-divided clock by dividing the external clock by M and further multiplying the M-divided clock by N to generate the internal clock. A circuit fetches the M-divided clock and the internal clock from the clock generation circuit, respectively, and generates an external synchronization latch clock, an internal synchronization latch clock, and an internal data synchronization clock, respectively. According to this configuration, each timing signal for operating the input interface with high accuracy can be generated.

Further, a cache memory is further provided, wherein when the frequency of the internal clock is higher than the frequency of the external clock, the cache memory is used when the input data synchronized with the external clock is emptied. To perform a process of accessing data and addresses necessary for the operation. Thereby, each process in the microprocessor can be effectively executed.

[0029]

A data processing system according to the present invention is a data processing system in which internal data sent from a microprocessor in synchronization with an internal clock is output to an external device operated by an external clock. Input / output means for capturing the internal data and outputting the internal data in synchronization with the external clock, wherein the input / output means holds the internal data until a predetermined timing which can be latched by the external clock. It is characterized by comprising a holding means for outputting to the external device.

In the data processing system of the present invention, for example, even when the multiplication rate between the internal clock and the external clock is a non-integer multiple, the microprocessor is operated at the highest performance inside and outside the microprocessor, that is, at the highest frequency, and the entire system is operated. The best performance can be obtained. For example, when the operating frequency of the internal clock has a ratio of a non-integer multiple of the external clock, the holding means holds the internal data, so that the internal data can be properly latched even in an asynchronous cycle in which the latch timing does not match. it can.

The output interface for taking in internal data of the microprocessor, and timing generating means for generating a timing signal for adjusting a latch timing in the output interface, wherein the holding means stores the internal data in accordance with the timing It is preferable to include an output holding register that latches in response to a signal, and output means for outputting an output of the output holding register in response to a level change of the external clock.

More preferably, the output interface includes a plurality of latch circuits for respectively latching output data sequentially output in synchronization with the internal clock, and operates in response to the external clock. A configuration is provided in which the outputs of one latch circuit are output in the output order of the original internal data. In this case, a circuit configuration corresponding to a clock whose multiplication rate is a non-integer multiple can be easily realized.

[0034]

The present invention will be described in more detail with reference to the drawings. FIG. 1 is a block diagram showing a data processing system according to the first embodiment of the present invention. The data processing system 11 includes a microprocessor (MPU)
15, a peripheral device 12 connected to the microprocessor 15 via a system bus (external bus) 40, and an oscillation circuit 13 for supplying a clock to each of the microprocessor 15 and the peripheral device 12.

The microprocessor 15 has an input interface 16, a timing generation circuit 17, a clock generation (Phase Lock Loop: PLL) circuit 19, and an output interface 20, and the peripheral device (external device) 1
It operates at a frequency higher than frequency 2. In this data processing system, the peripheral device 12 and the microprocessor 15
The ratio of the clock frequency to the internal clock is not an integer, but a non-integer value close to the ratio between the clock frequency of the guaranteed maximum speed of the peripheral device 12 and the clock frequency of the guaranteed maximum speed of the microprocessor 15.

Therefore, the internal clock is phase-synchronized with the external clock in a predetermined frequency relationship, but includes an asynchronous cycle. Here, the asynchronous cycle means that when data is output from the peripheral device and the external clock CLOCK rises as shown at time t1 in FIG.
It means a cycle in which H1 does not rise. On the other hand, the synchronization cycle means a cycle in which when the external clock CLOCK rises, the internal clock PH1 also rises as at time t6 in FIG.

The microprocessor 15 is divided into five pipeline stages for pipeline processing, that is, an IF (Instruction Fetch) stage and an RF stage.
(Register Fetch) stage, EX (Execute) stage,
It has a DF (Data Fetch) stage and a WB (Write Back) stage.

The IF (instruction / fetch) stage is a program counter generation section 22 for generating a branch destination address (instruction fetch address) when there is a branch instruction or the like.
And a program counter (PC) 18 and an instruction cache 23 for outputting an address instruction indicated by the program counter 18 (for transmitting and receiving an instruction code).

At the IF stage, an instruction is read from the instruction cache 23 or an instruction memory (ROM, not shown) using an address (hereinafter, referred to as a PC address) indicated by the program counter 18, and an RF pipeline described later is used. -Written to the register 24. program·
The PC address of the counter 18 is incremented,
Prepare for the next instruction fetch cycle.

The RF (register fetch) stage is
A pipeline control unit 25, a register file 26,
RF pipeline register 2 adjacent to IF stage
And 4.

The RF pipeline register 24 has a PC latch 35 for latching an output from the program counter 18 and an instruction code latch 36 for latching an instruction code output from the instruction cache 23. These latches 35 and 36 respectively hold and operate in synchronization with the pipe clock signal (internal clock) PH1. The register file 26 includes a plurality of registers to which register numbers are assigned. When a register number is input as an access key, the contents of the register are read / written. For example, it is composed of a read / write decoder and a register in which flip-flops are arranged.

In the register file 26, the state is not changed at all when the register is read, and the data stored in the register can be obtained only by specifying the register number as an input. At the time of writing to the register of the register file 26, for example, three inputs of a register number, data to be written, and a clock signal for controlling writing are required. Further, the pipeline control unit 25 reads an instruction code from the instruction code latch 36, decodes the instruction code, and controls the operation in the pipeline processing as a whole. Although the pipeline control unit 25 is illustrated in the RF stage for convenience in FIG. 1, it does not belong only to the RF stage but relates to all stages.

The EX (Execute) stage includes an arithmetic operation unit (ALU) 27 and an EX pipeline register 28.
And the EX pipeline register 28 has
It has latches 31, 32, and 33 for latching each processing data. Arithmetic operation section 27 operates on the data fetched via latches 31 and 32, and sends the operation result to the DF stage.

In the EX stage, the decoded instruction is executed. For example, the contents of the register and the sign-extended value are read from the EX pipeline register 28 by a load instruction and added by the arithmetic operation unit 27,
The result of the addition is stored in the DF pipeline register.
In this stage, it is necessary to set each signal in the latches 31 and 32. According to the set signal, the operation of the ALU 27 and the selection of which of the register and the sign-extended value to input to the ALU 27 are respectively selected. Is done.

The DF (data fetch) stage includes a data cache 34 and a DF pipeline register 3
And 5. The DF pipeline register 35 includes a latch 36 for latching data from the arithmetic operation unit 27,
Latch 37 for latching write data from latch 33
And

The data cache 34 receives the data from the latch 36 and the write data from the latch 39 at the subsequent stage, and sends and receives necessary cache data to and from the internal bus 21. SYNC
Is high, the data DATA from the peripheral device 12
Take in. If there is a miss hit, data cache 3
4 issues a read bus cycle to an external bus control unit (not shown). Further, the read data output from the data cache 34 and the write data output from the latch 37 are input to the selector 14, and one of the data is selected by a read / write control signal R / W (not shown). Output to the latch 39.

In the DF stage which is an access stage to the peripheral device 12 and the like, data is read from the peripheral device 12 and the like. When a miss occurs in the data cache 34 due to the load instruction, data is read from a RAM (random access memory) or the like that stores data to be processed and stored in a WB pipeline register 38 described later.

The last stage, WB (Write Back), has a WB pipeline register 38. W
The B pipeline register 38 stores the data cache 3
Latch 3 for selecting and latching one of read data from latch 4 and write data from latch 37 by selector 14
9 is provided.

In the WB stage, data is written to the peripheral device 12 or the like. In the load instruction,
Data is read from the WB pipeline register 38 and the data is written to the register file 26. In the store instruction, when a hit occurs in the data cache 34, the data is written into the data cache 34, and when a miss occurs, a write bus cycle is issued to the outside.
Write data to an AM (not shown) or the like.

In the data processing system 11 having the above configuration,
An external clock from the oscillation circuit 13 is supplied to the peripheral device 12, the timing generation circuit 17, and the clock generation circuit 19, respectively.

The clock generating circuit 19 has a function of dividing the external clock CLOCK supplied from the oscillation circuit 13 by M and then multiplying it by N. The signal CLK2 obtained by dividing the external clock CLOCK by M and a later-described signal CLK2 are provided. VCO (voltage controlled oscillator) 53
Operates so that the phase (frequency) of the output signal of the second clock signal becomes the same as that of a signal obtained by dividing the output by N to generate a pipeline clock PH1 (internal clock). That is, PH1 = ((CLOCK /
M) × N).

The timing generation circuit 17 includes the oscillation circuit 13
, The second clock CLK2 generated by the clock generation circuit 19, and the pipeline clock.
PH1 is fetched, and a clock for generating timing between clocks is generated. Timing generation circuit 17
The SYNC signal connected to the pipeline control unit 25 from
This signal indicates whether data DATA from the peripheral device 12 is valid or invalid.
Incorporate TA as valid.

Data DATA from the peripheral device 12 is supplied to an external bus 40 in synchronization with an external clock CLOCK, and is taken in via an input interface 16 in synchronization with a clock, which will be described later, generated by a timing generation circuit 17. It is supplied to the bus 21.

The output interface 20 is connected to the internal bus 21 in synchronization with the pipeline clock PH1 (internal clock).
While the internal data supplied to the external bus 4 is fetched in synchronization with the clock generated by the timing generation circuit 17.
Supply 0. The microprocessor 15 operates in synchronization with the pipeline clock PH1 generated by the clock generation circuit 19, and supplies processing data to the internal bus 21.

FIG. 2 is a circuit diagram showing a main part of the internal configuration of the input interface 16. Input interface 16
Is an input buffer 42 having a CMOS structure, an input holding register 43 and an input latch 46 each comprising a D-flip-flop, and an input holding register 43 and an input latch 4
6 and an inverter 45 inserted between them.

The input holding register 43 has a data input terminal D, a data output terminal QB for inverting and outputting an input,
It has a clock terminal CLK and a latch enable terminal CE, and each terminal has an output of the input buffer 42, data DATA sent via the inverter 45, and an external synchronous latch clock CL.
K_REG and a synchronous latch clock SYNC_REG, respectively. The input holding register 43 stores the synchronous latch clock SY
When NC_REG is at a high level and the external synchronization latch clock CLK_REG rises, the input buffer 4
2 latches the data DATA sent via. When the synchronous latch clock SYNC_REG is at a low level, the input holding register 43 does not latch the data DATA sent via the input buffer 42 even if the external synchronous latch clock CLK_REG rises. The output from the input holding register 43 is inverted via an inverter 45 and sent to an input latch 46.

The input latch 46 is connected to the input holding register 43.
And latches the output of the inverter 45 when the internal data synchronization clock SYNC is at a high level and the pipeline clock PH1 rises. The output from the input latch 46 is connected to an inverter 47,
48 and the internal bus 21 as internal data DATA_IN.
(FIG. 1).

The input interface 16 having such a configuration responds to the timing signal from the timing generation circuit 17 by the input holding register 43 to store the data DA.
TA is latched, and the output of the input holding register 43 is latched by the input latch 46 in response to the level change of the pipeline clock PH1 (internal clock). Therefore, even if the data DATA is in an asynchronous cycle, the hold time of the data DATA can be extended by the input holding register 43, so that the MPU can reliably capture the data DATA.

FIG. 3 is a timing chart showing the output timing of each signal in the input interface 16 shown in FIGS. In FIG. 3, an external clock
The clock and the pipeline clock PH1 (internal clock) are phase-synchronized with each other in a predetermined frequency relationship. The figure shows a pipeline clock generated by the clock generation circuit 19.
A case where the multiplication rate of the external clock CLOCK of PH1 is a non-integer multiple of 2.5 is shown.

In FIG. 3, the horizontal direction indicates a time axis based on the pipeline clock PH1, and the vertical direction indicates a signal line axis. FIGS. 7A to 7G show the external clock CLOCK, the external synchronous latch clock CLK_REG, and the internal synchronous latch clock SYN.
C_REG, pipeline clock PH1, internal data synchronization clock SYNC, data DATA, and internal data DATA_IN are shown, respectively.

In the figure, since the multiplication rate of the pipeline clock PH1 with respect to the external clock CLOCK is a non-integer multiple, the synchronous latch cycle 49 and the asynchronous latch cycle 5
Data DATA of 0 is generated. In the synchronous latch cycle 49, when the peripheral device outputs data, the external clock CL is output.
The rising edge of both the OCK and the pipeline clock PH1 match, and the data DATA (DATA
2) can be latched by the clock Ph1 of the pipeline clock PH1.

However, in the asynchronous latch cycle 50,
The data DATA (DATA1) is valid when the external clock CLOCK rises. At this time, since the pipeline clock PH1 falls, the input interface of the related art cannot latch with the clock Ph1 of the pipeline clock PH1. Absent. Prior art input interfaces are:
The data is latched at the next rising edge of the clock Ph1, but at this time, the hold time of the data DATA (DATA1) has already passed and cannot be latched.

The input interface 16 of this embodiment
Latches data DATA sent from the peripheral device 12 in synchronization with the external clock CLOCK in synchronization with the external clock CLOCK, and latches the latched data in the pipeline clock PH1.
So that it is taken into the microprocessor 15.
Even in an asynchronous cycle, data DATA can be accurately taken.

Hereinafter, the operations of the input interface 16 and the clock generation circuit 19 shown in FIG. 2 will be described in detail with reference to the timing chart shown in FIG.

FIG. 3A shows the external clock CLOCK. The external clock CLOCK has one cycle from time t0 to t4 and repeats the same waveform after time t5. The internal clock PH1 in FIG. 3D determines the latch timing of the input latch 46, and takes in the data DATA input at the rising edge of this clock. The internal clock PH1 has a period from time t0 to time t1 and repeats the same waveform after time t2. Further, the internal clock PH1 has a frequency 2.5 times that of the external clock CLOCK, and the rising phases coincide at every two cycles of the external clock CLOCK, that is, at times t0, t10,.

The external synchronization latch clock CLK_ shown in FIG.
REG is a signal that determines the latch timing of the input holding register 43, and latches the data DATA at the rising edge of this clock. External synchronous latch clock CL
K_REG has the same cycle as the external clock CLOCK, rises at the same timing (t0, t5, t10,...), And the high-level period is １ ／ cycle of the internal clock PH1.

The internal synchronization latch clock SYNC shown in FIG.
_REG is a signal for enabling the latch of the input holding register 43. When this signal is at a high level, the latch is enabled, and when it is at a low level, the latch is not performed. The internal synchronization latch clock SYNC_REG has the same cycle as the external clock CLOCK and rises at the same timing (t0,
t5, t10,...), the high level period is one cycle of the internal clock PH1. In this embodiment, an example is shown in which the internal synchronization latch clock SYNC_REG goes to a high level every time the external clock CLOCK rises. Is also good.

The internal data synchronization clock SYNC shown in FIG.
Provides permission to latch the input latch 46. When this signal is at a high level, the latch is permitted, and when the signal is at a low level, the latch is not performed. The internal data synchronization clock SYNC rises at the rising edge of the internal clock PH1 (t0, t6, t1) after the data DATA becomes valid.
0,...), The high level period is one cycle of the internal clock PH1. In the present embodiment, the internal data synchronization clock
SYNC indicates an example in which the same level as the external clock CLOCK is set to the high level.
The high level may be set only for the read cycle.

The input interface 16 of this embodiment is
Two clocks of the external clock CLOCK, that is, the internal clock P
The same operation is repeated with five cycles of H1 (time t0-t9) as one cycle. Therefore, here, at time t4−t1
Operation 3 will be described.

Between time t4 and time t5, the peripheral circuit 12
The data DATA1 is output (FIG. 3 (f)), and DATA1 is input to the input buffer 42 via the input terminal 41. The input buffer 42 inverts the data DATA1 and inputs the inverted data DATA1 to the input holding register 43.

At time t5, the internal synchronization latch clock SY
NC_REG goes high (FIG. 3C), and the input holding register 43 can be latched. At the same time, the external synchronous latch clock CLK_REG rises (see FIG. 3).
(B)), the input holding register 43 latches the data DATA1 at the rising edge, and outputs an inverted signal thereof from the output terminal QB. This output is inverted by the inverter 45 and input to the input latch 46. Note that the latched data DATA1 is output to the next external synchronization latch clock CLK_
It is held until REG rises (t10) (not shown).

On the other hand, in the input latch 46, since the pipeline clock PH1 falls (FIG. 3D) and the internal data synchronization clock SYNC maintains the low level (FIG. 3D).
(E)), the data DATA (DATA1) cannot be latched.

At time t6, internal data synchronous clock SY
NC goes high (FIG. 3 (e)) and the input latch 46
Can latch the input signal. At the same time, since the pipeline clock PH1 rises (FIG. 3D), the input latch 46 sets the data in synchronization with the rising edge.
DATA1 is latched and its inverted signal is output from the output terminal QB. This output is amplified by inverters 47 and 48 and output to internal bus 21 as internal data DATA_IN (FIG. 3 (g)).

As described above, in the asynchronous cycle 50, the input holding register 43 sets the data DATA1 in response to the external synchronous latch clock CLK_REG from the timing generation circuit 17.
Is latched once, and the next external synchronization latch clock CLK_REG
Hold until the rise of. The input latch 46 can latch the data (DATA1) of (f) output from the input holding register 43 with a sufficient hold time at the next rising edge of the pipeline clock PH1. Therefore, even if the hold time is short, there is no possibility that the input data cannot be taken in synchronization with the internal clock PH1 as in the related art.

At time t7, the external clock CLOCK maintains the high level (a), and both the external synchronous latch clock CLK_REG and the internal synchronous latch clock SYNC_REG go low (b) and (c). PH1 becomes low level (d), and the internal data synchronization clock SYNC maintains high level (e).

The external clock CLOCK goes to a low level at an intermediate point between times t7 and t8 (a). At time t8, the external clock CLOCK maintains the low level (a), and the external synchronous latch clock CLK_REG and the internal synchronous latch clock SYNC_
Both REGs maintain the low level (b), (c), at the same time, the pipeline clock PH1 goes high (d), and the internal data synchronization clock SYNC goes low (e).

At time t9, the external clock CLOCK maintains the low level (a), and both the external synchronization latch clock CLK_REG and the internal synchronization latch clock SYNC_REG maintain the low level (b) and (c), and simultaneously, the pipeline clock PH1 becomes low level (d), and the internal data synchronization clock SYNC maintains low level (e).

Further, between time t9 and t10, the peripheral device 12 outputs the next data DATA2. Data DATA2
Are inverted and amplified by the input buffer 42 and input to the input holding register 43.

At time t10, the internal synchronization latch clock SY
NC_REG goes high (FIG. 3C), and the input holding register 43 can be latched. At the same time, the external synchronous latch clock CLK_REG rises (see FIG. 3).
(B)), the input holding register 43 latches the data DATA2 in synchronization with the rising edge, and outputs an inverted signal thereof from the output terminal QB. This output is connected to inverter 4
It is inverted at 5 and input to the input latch 46. In addition,
The latched data DATA1 is held until the next external synchronization latch clock CLK_REG rises (t15) (not shown).

Further, the internal data synchronization clock SYNC becomes high level (FIG. 3E), and the input latch 46 can latch the input signal. At the same time, since the pipeline clock PH1 rises (FIG. 3D), the input latch 46 outputs the data DA in synchronization with the rising edge.
Latch TA2 and output its inverted signal from output terminal QB. This output is amplified by inverters 47 and 48,
The data is output to the internal bus 21 as internal data DATA_IN (FIG. 3 (g)).

As described above, in the synchronization cycle 49, the input holding register 43 latches the data DATA2 in response to the external synchronization latch clock CLK_REG from the timing generation circuit 17, and at the same time, the input latch 46 sets the pipeline clock PH1. , The data DATA (DATA2) of (f), which is the output of the input holding register 43, can be latched and output to the internal bus 21.

At this time, since the rising edges of both the external clock CLOCK and the pipeline clock PH1 coincide with each other, the pipeline clock PH1 receives the data DATA (f) of (f) inputted in synchronization with the external clock CLOCK. DATA
2) can be latched at the same timing as before. Note that the latched data DATA2 is held until time t16 when the next data is latched.

In the present embodiment, an example is shown in which a latch circuit having a latch enable terminal CE is used as the input holding register 43 and an external synchronous latch clock CLK_REG having a short pulse width is used for latch timing. Alternatively, a latch circuit using the external clock CLOCK and not having the latch permission terminal CE may be used. Further, the inverters 45, 47, and 48 may be appropriately deleted according to the logic.

FIG. 4 is a block diagram showing the internal configuration of the clock generation circuit 19. The clock generation circuit 19 includes a frequency divider 51 that divides the external clock CLOCK by two and a PLL circuit 19a. The frequency divider 51 receives an external clock.
The second clock CLK2 is generated by dividing the clock by two. PL
The L circuit 19a includes a PD (phase comparator) 52, a VCO (voltage controlled oscillator) 53, and a frequency divider 54 having a frequency division number of 5, and the PD 52 is configured to divide the input signal by two to obtain a second frequency. The clock CLK2 is compared with a signal obtained by dividing the output of the VCO 53 by five, and the oscillation phase of the VCO 53 is controlled so that the phase difference is eliminated. The second clock CLK2 and the pipeline clock PH1 are output from the clock generation circuit 19 having this configuration. Therefore, the output of the VCO 53 becomes a clock PH1 having a frequency that is five times the frequency of the signal divided by two.
Therefore, the frequency of the clock PH1 is equal to the external clock CLOCK.
Clock PH1 and external clock CLOC
The frequency ratio with K is a non-integer.

FIG. 5 is a block diagram showing the internal configuration of the timing generation circuit 17. Timing generation circuit 17
Has latches 55 to 59, a two-input AND gate 60, a two-input NOR gate 61, two-input OR gates 62 and 63, and inverters 64 and 65.

At the rising edge of the inverted signal PH1B of the pipeline clock PH1 passed through the inverter 65, the latch 55 takes in the level of the inverted signal of the second clock CLK2, which is the frequency-divided clock M passed through the inverter 64, and outputs The signal C1 is output. As a result, the output signal C1
Is a signal obtained by delaying the rising timing of the second clock CLK2 by ク ロ ッ ク clock of the clock PH1, and falling at the same timing.

The two-input AND gate 60 takes in the output signal C1 of the latch 55 and the second clock CLK2, respectively, and
The logical product of both is output as the output signal C2. As a result, the output signal C2 goes high in synchronization with the rise of the second clock CLK2, and becomes a signal that goes high only for a half clock period of the clock PH1.

The latch 56 is connected to the pipeline clock PH1.
At the rising edge of the second
An inverted signal of the clock CLK2 is taken in, and an output signal C3 is output. As a result, the output signal C3 becomes the second clock CL
The falling timing of K2 is １ ／ of clock PH1.
The signal is delayed by the clock, and the rising edge has the same timing.

The two-input NOR gate 61 receives the output signal C3 of the latch 56 and the second clock CLK2, respectively.
An output signal C4 that goes high when both signals go low is output. As a result, the output signal C4
Becomes a high level in synchronization with the fall of the second clock CLK2, and becomes a high level signal for a half clock period of the clock PH1.

The two-input OR gate 62 takes in the output signal C2 and the output signal C4, respectively, and outputs the logical sum of both as the external synchronization latch clock CLK_REG. As a result, the external synchronous latch clock CLK_REG becomes the external clock C
It becomes a high level in synchronization with the rise of LOCK, and becomes a high level signal for a period of １ ／ clock of the clock PH1.

The latch 57 is connected to the pipeline clock PH1.
At the rising edge of, the external synchronous latch clock CLK_REG from the two-input OR gate 62 is fetched and the output signal C5 is output. As a result, the output signal C5 goes high in synchronization with the rise of the second clock CLK2, and becomes a signal that goes high only for one clock period of the clock PH1.

The latch 58 is connected to the pipeline clock PH1.
At the rising edge of the inverted signal PH1B, the external synchronous latch clock CLK_REG from the two-input OR gate 62 is fetched and the output signal C6 is output. As a result, the output signal C
The signal 6 goes high in synchronization with the fall of the second clock CLK2, and becomes a signal that goes high only for one clock period of the clock PH1.

The two-input OR gate 63 takes in the output signals C5 and C6, respectively, and outputs the logical sum of both as the internal synchronization latch clock SYNC_REG. As a result,
The internal synchronization latch clock SYNC_REG is connected to the external clock CLOC
It goes high in synchronization with the rise of K, and the clock P
The signal becomes a high level only for one clock period of H1.

The latch 59 is connected to the pipeline clock PH1.
Rising edge of the internal synchronization latch clock SYNC_R
It takes in the EG and outputs the internal data synchronization clock SYNC. As a result, the internal data synchronous clock SYNC is the same as the internal synchronous latch clock SYNC_REG in the synchronous cycle, and the internal synchronous latch clock SYNC in the asynchronous cycle.
_REG is a signal delayed by a half clock period of clock PH1.

FIG. 6 is a timing chart showing the timing of each signal in the timing generation circuit 17.
The horizontal axis in the figure shows the time based on the pipeline clock PH1, and (a) to (m) respectively show the external clock CLOC.
K, the second clock CLK2, the pipeline clock PH1, the inverted signal PH1B of the pipeline clock PH1, the output signal C1,
C2, C3, C4, external synchronization latch clock CLK_REG,
Output signals C5 and C6, internal synchronization latch clock SYNC_RE
G and the internal data synchronization clock SYNC.

Timing generation circuit 17 having the above configuration
The second clock CLK2 (FIG. 6B) obtained by dividing the external clock CLOCK (FIG. 6A) by 2 and the pipeline clock P
H1 (FIG. 6C) is input from the clock generation circuit 19.

At time t0, the external clock CLOCK goes high (FIG. 6 (a)), the second clock CLK2 (FIG. 6 (b)), and the pipeline clock PH1 (FIG. 6 (c)), respectively. . Since the latch 56 takes in the inverted signal of the second clock CLK2 at the timing of the rising edge of the pipeline clock PH1, the output signal C3 goes low (FIG. 6).
(g)). However, since the second clock CLK2 is at the high level, the output signal C4 of the two-input NOR gate 61 maintains the low level (FIG. 6 (h)).

Since the clock terminal PH1B falls, the state of the latch 55 does not change, and the output signal C1 maintains the high level (FIG. 6 (e)), and both the output signal C1 and the second clock CLK2 are high. Level, the output signal C2 of the two-input AND gate 60 goes high (FIG. 6 (f)).
Accordingly, the 2-input OR gate 62 sets the external synchronization latch clock CLK_REG to the high level because the output signal C2 is at the high level (FIG. 6 (i)).

The latch 58 has an inverted pipeline clock.
Since PH1B falls (FIG. 6 (d)), the output signal C6 maintains the low level (FIG. 6 (k)). Since the latch 57 takes in the external synchronization latch clock CLK_REG at the timing of the rise of the pipeline clock PH1, the output signal C
5 becomes high level (FIG. 6 (j)). As a result, the 2-input OR gate 63 sets the internal synchronization latch clock SYNC_REG to high level because the output signal C5 is at high level (FIG. 6 (l)).

The latch 59 is connected to the pipeline clock PH1.
The internal synchronization latch clock SYNC
_REG is taken in, and the internal data synchronization clock SYNC is set to a high level (FIG. 6 (m)).

At time t1, both the external clock CLOCK and the second clock CLK2 maintain the high level (a), (b),
The pipeline clock PH1 becomes low level (c). Since the latch 55 captures the inverted second clock CLK2B at the rising timing of the inverted pipeline clock PH1B, the output signal C1 becomes low level (e). Output signal C
Since both the first and second clocks CLK2B are at low level, 2
The output signal C2 of the input AND gate 60 goes low (f). Since the pipeline clock PH1 falls, the latch 56 does not change its holding state and maintains the output signal C3 at low level (g). However, since the second clock CLK2 is at the high level, the two-input NOR gate 61 maintains the output signal C4 at the low level (h). As a result, the two-input OR gate 62 sets the external synchronization latch clock CLK_REG to low level (i) because the output signals C2 and C4 are both low level.

In the latch 58, since the inverted pipeline clock PH1B rises (d), the low-level external synchronous latch clock CLK_REG is latched, and the output signal C6 is maintained at the low level (k). Since the pipeline clock PH1 falls, the latch 57 keeps the output signal C5 at a high level without changing its holding state. As a result, since the output signal C5 is at the high level, the two-input OR gate 63 maintains the internal synchronization latch clock SYNC_REG at the high level (l).

In the latch 59, the pipeline clock PH
Since 1 rises, the internal synchronization latch clock SYNC_REG, which is at a high level, is latched and the internal data synchronization clock is latched.
Keep SYNC high (m).

At time t2, the external clock CLOCK and the second clock
Both clocks CLK2 maintain the high level (a), (b), the pipeline clock PH1 goes high (c), and PH1B goes low (d). Therefore, the latch 55 and the latch 5
The eight output signals C1 and C6 remain at the low level without change (e), (k), and the output signal C2 of the two-input AND gate 60 also maintains the low level (f).

The latch 56 is connected to the pipeline clock PH1.
, The inverted second clock CLK2B is taken in at the rising edge of, so that the output signal C3 is maintained at the low level.
(g). Since the second clock CLK2 is at a high level, two inputs N
The OR gate 61 maintains the output signal C4 at low level (h). Accordingly, the two-input OR gate 62 maintains the external synchronization latch clock CLK_REG at the low level because the output signals C2 and C4 are at the low level (i).

The latch 57 is connected to the pipeline clock PH1.
When the signal rises, the external synchronization latch clock CLK_REG that is at a low level is latched, and the output signal C5 goes to a low level. Thus, the two-input OR gate 63 sets the internal synchronization latch clock SYNC_REG to low level (l) because both the output signal C5 and the output signal C6 are low level. When the latch 59 rises, the pipeline clock PH1 rises.
The low-level internal synchronization latch clock SYNC_REG is latched, and the output of the internal data synchronization clock SYNC is output.
To low level (m).

From time t3 to t4, the external synchronization latch clock CLK_REG (i) and the internal synchronization latch clock SYNC_REG
(l) and each output signal of the internal data synchronization clock SYNC (m) do not change, and therefore description thereof is omitted.

At time t5, the external clock CLOCK goes high (a), the second clock CLK2 goes low (b), the pipeline clock PH1 falls (c), and the inverted pipeline clock PH1B rises ( d). As a result, the latches 56, 57 and 59 do not change, and the output signals C3 and C5 and the internal data synchronization clock SYNC do not change.
(g), (j), (m).

The latch 55 has an inverted pipeline clock.
When PH1B rises, the inverted second clock CLK2 which is at a high level is latched and the output signal C1 is set to a high level (e). However, since the second clock CLK2 is at a low level, the output signal C2 of the two-input AND gate 60 is output. Maintains the low level (f). Since the output signal C3 of the latch 56 is maintained at the low level (g) and the second clock CLK2 is also at the low level, the 2-input NOR gate 61 sets the output signal C4 to the high level.
(h). As a result, since the output signal C4 is at a high level,
The two-input OR gate 62 outputs the external synchronous latch clock CLK_
REG is set to high level (i).

The latch 57 keeps the output signal C5 at low level (j), and the latch 58 takes in the external synchronization latch clock CLK_REG at the rising timing of the inverted pipeline clock PH1B, so that the output signal C6 goes high. (k). Thereby, the two-input OR gate 63 outputs the internal synchronization latch clock SY in accordance with the output signals C5 and C6.
Set NC_REG to high level (l). The latch 59 maintains the internal data synchronization clock SYNC at low level (m).

At time t6, the external clock CLOCK maintains the high level (a), the second clock CLK2 maintains the low level (b), and the pipeline clock PH1 changes to the high level (c). Since the inverted pipeline clock PH1B falls, the latches 55, 58 do not change, and the output signals C1, C6
Is maintained at a high level (e), (j).

The latch 56 is connected to the pipeline clock PH1.
Becomes high level, the inverted second clock CLK2B which is high level is latched, and the output signal C3 is made high level (g). Therefore, the 2-input NOR gate 61 sets the output signal C4 to low level (h) because the output signal C3 is low level. The two-input OR gate 62 outputs the output signal C
Since both C2 and C4 are low level, the external synchronization latch clock CLK_REG is set to low level (i).

The latch 57 is connected to the pipeline clock PH1.
Becomes high level, the external synchronization latch clock CLK_REG at low level is latched, and the output signal C5 is maintained at low level. In the latch 58, the output signal C6 maintains the high level (k). Accordingly, the 2-input OR gate 63 sets the internal synchronization latch clock SYNC_REG to high level (l) because the output signal C6 is at high level. The latch 59 outputs a high-level internal synchronous latch clock SY at the rising timing of the pipeline clock PH1.
Since the NC_REG is taken in, the internal data synchronization clock SYNC which is the output thereof is set to the high level (m).

At time t7, the external clock CLOCK goes low (a), the second clock CLK2 remains low (b), and the inverted pipeline clock PH1B goes high (d). Since the pipeline clock PH1 falls, the latches 56, 57 and 59 do not change, and the output signals C3 and C5 and the internal data synchronization clock SYNC do not change.

The latch 55 has an inverted pipeline clock.
When PH1B rises, the inverted second clock CLK2B, which is at a high level, is latched and the output signal C1 is maintained at a high level (e). Since the second clock CLK2 is also at a high level, the output signal C2 of the two-input AND gate 60 is output. Maintain at low level (f). The latch 56 maintains the output signal C3 at a high level (g). Therefore, the 2-input NOR gate 61 maintains the output signal C4 at low level because both the output signal C3 and the second clock CLK2 are at high level (h). As a result, the two-input OR gate 62 outputs the external synchronization latch clock CLK_RE since the output signals C2 and C4 are both at the low level.
G is maintained at a low level (i).

The latch 57 maintains the output signal C5 at a low level. Latch 58 is an inverted pipeline clock.
Since the external synchronization latch clock CLK_REG, which is at the low level, is taken in at the rising timing of PH1B, the output signal C6 becomes the low level (k). Thereby, the two-input OR
The gate 63 sets the internal synchronization latch clock SYNC_REG to low level (l) because the output signals C5 and C6 are both low level. The latch 59 has an internal data synchronization clock SYNC
Is maintained at a high level (m).

At time t8, both the external clock CLOCK and the second clock CLK2 maintain the low level (a), (b),
The pipeline clock PH1 becomes high level (c). Since the inverted pipeline clock PH1B falls, the latch 5
5 and 58 do not change, and the output signals C1 and C6 do not change.

Since the output signal C1 of the latch 55 is maintained at the high level (e) and the second clock CLK2 is at the low level, 2
The output signal C2 of the input AND gate 60 maintains the low level (f). The latch 56 captures the high-level inverted second clock CLK2B at the rising timing of the pipeline clock PH1, so that the output signal C3 is maintained at the high level (g). Therefore, the two-input NOR gate 61
Maintains the output signal C4 at low level because the output signal C3 is at high level (h). As a result, the two-input OR gate 62 maintains the external synchronization latch clock CLK_REG at the low level because the output signals C2 and C4 are both at the low level (i). The latch 57 captures the low-level external synchronization latch clock CLK_REG at the timing of the rise of the pipeline clock PH1, so that the output signal C5 is maintained at the low level (j).

The latch 58 maintains the output signal C6 at low level (k). Thereby, the two-input OR gate 63
Maintains the internal synchronization latch clock SYNC_REG at a low level because the output signals C5 and C6 are both at a low level.
(l). The latch 59 takes in the low-level internal synchronization latch clock SYNC_REG at the rising timing of the pipeline clock PH1, so that the internal data synchronization clock SYNC goes low (m).

At time t9, external synchronization latch clock CL
Since the output signals of K_REG (i), the internal synchronization latch clock SYNC_REG (l), and the internal data synchronization clock SYNC (m) do not change, the description is omitted. After time t10, times t0 to t9 are repeated.

As described above, the timing generation circuit 17
Can generate a signal for controlling the input interface 16 based on the clock signal generated by the clock generation circuit 19.

As described above, in the data processing system of the present embodiment, the input holding register 43 is provided at a stage preceding the input latch 46 in the input interface 16.
Further, by supplying the internal data synchronization clock SYNC and the pipeline clock PH1 to the input latch 46 that latches the output of the input holding register 43, the data DATA can be held. Therefore, the peripheral device 12 and the MPU
Even when the ratio between the internal clock frequencies is not an integer and an asynchronous latch cycle in which the latch timing is delayed occurs, a correct input signal can be reliably latched.

When operating at the guaranteed maximum clock frequency possessed by both the peripheral device and the microprocessor 15, for example, when input data input at a frequency of 100 MHz is operated at an internal clock of 250 MHz, In the conventional technology, the peripheral device is set to 100 MHz.
Operating near the guaranteed maximum speed of the microprocessor 1
5 near 250MHz guaranteed maximum speed,
Data could not be imported correctly. But,
In the data processing system of the present embodiment, 100 MHz
Asynchronous input data input at 25
It can be correctly captured at 0 MHz. That is, even when the multiplication rate between the external clock CLOCK and the pipeline clock PH1 (internal clock) is a non-integer multiple, the asynchronousness between the pipeline clock PH1 and the external clock CLOCK is absorbed inside the input interface 16. Since signals can be properly transmitted and received between the inside and outside of the MPU, the MPU can be operated at the highest performance inside and outside the MPU, that is, at the highest frequency, and the highest performance of the entire system can be obtained.

[Second Embodiment] Next, a second embodiment of the present invention will be described. In this embodiment, the basic configuration other than the input interface 16 described with reference to FIG. 1 is the same as that of the first embodiment. In addition, external clock CLOCK
The case where the frequency ratio between the internal clock PH1 and the internal clock PH1 is 3: 4 will be described as an example.

FIG. 7 is a circuit diagram showing an input interface according to this embodiment. The input interface 16 includes a latch L having a plurality of ring-connected inverters.
1 to L3 (input holding register), input latch L4,
External counter 66 to which an external clock CLOCK is supplied
, An internal counter 67 to which a pipeline synchronization clock SYNC_P is supplied, and inverters 68 and 69.
A selection signal generation circuit 97 having an AND gate is provided at a stage preceding the internal counter 67. The selection signal generation circuit 97 outputs a logical product of the input pipeline clock PH1 and the internal data synchronization clock SYNC to the internal counter 67 as a synchronization latch clock SYNC_P.

In this embodiment, as in the first embodiment, the internal data synchronization clock SYNC is used as a latch enable signal for the latch 46 and a signal indicating that the data DATA is valid. However, as in the present embodiment, the ratio between the external clock CLOCK and the internal clock PH1 is 2 or less (4/4).
In the case of 3), the internal data synchronization clock SYNC maintains the high level without interruption between the adjacent data DATA (from t4 to t10 in FIG. 10). Even if this is input to the internal counter 67, it does not match the number of data DATA to be input. That is, referring to FIG. 10 described below,
During the same cycle period, the external clock CLOCK (FIG. 10)
(a)) is a pipeline clock PH1 (FIG. 10) for three cycles.
(b)) has four cycles, and a pipeline synchronization clock SYNC_P is generated to match the number of pipeline clocks PH1 with the external clock CLOCK.

One end and the other end of the current path of the selecting MOS transistor T1 are connected between the inverter 68 to which the data DATA is input and the latch L1, and the selecting MOS transistor is connected between the inverter 68 and the latch L2. One end and the other end of the current path of T2 are connected, and one end and the other end of the current path of the selecting MOS transistor T3 are connected between the inverter 68 and the latch L3. An external counter unit 6 is provided at each gate of the selection MOS transistors T1 to T3.
6 drive signals C11 to C13 are respectively connected.

One end and the other end of the current path of the selection MOS transistor T4 are connected between the latch L1 and the input latch L4, and the current of the selection MOS transistor T5 is connected between the latch L2 and the latch L4. One end and the other end of the path are connected, and one end and the other end of the current path of the selecting MOS transistor T6 are connected between the latch L3 and the input latch L4. The output signals C21 to C2 of the internal counter 67 are provided to the gates of the selection MOS transistors T4 to T6, respectively.
3 are connected respectively.

Data DATA input from peripheral device 12
Is inverted and amplified by the inverter 68 and then input to the transistors T1 to T3. Transistors T1 to T3
Are sequentially turned on at the timing when the drive signals C11 to C13 become high level, and the inverted data DATA is latched L1 to L13.
Supply to L3. The latches L1 to L3 invert and hold this, and output it to the transistors T4 to T6.
The transistors T4 to T6 are sequentially turned on at the timing when the drive signals C11 to C13 become high level, and supply the latched data to the latch L4. The latch L4 holds the supplied data DATA and stores the data DA on the internal bus 21.
Output as TA_IN.

FIG. 8 is a circuit diagram showing the internal configuration of the external counter section 66. The internal configuration of the internal counter 67 is the same as that of the external counter 66, but the output timing of the drive signals C21 to C23 is different as described later. Here, the configuration and operation of the external counter section 66 will be described as a representative, and the description of the internal counter section 67 will be omitted.

The external counter 66 includes a ternary counter 70
, Two-input NOR gate 71 and two-input AND gate 7
2 to 74. The ternary counter 70 receives an external clock
CLOCK and reset signal RESET are input and output signal A1
And A0, respectively. The output signals (A1, A0) are
Each time the external clock CLOCK rises, the count value is changed from (0,0) → (0,1) → (1,1) → (0,0) →.
Is output repeatedly in the order of.

The external clock CLOCK is input to one input terminal of each of the two-input AND gates 72 to 74. The output signal A1 is input to one input terminal of the two-input NOR gate 71 and is input to the other input terminal of the two-input AND gate 72. The output signal A0 is input to the other input terminal of the two-input NOR gate 71 and is input to the other input terminal of the two-input AND gate 73. The output signal C14 of the two-input NOR gate 71 is a two-input AND
The signal is input to the other input terminal of the gate 74. 2-input AN
From the D gates 72 to 74, the respective drive signals C11 to C1
3 is output.

By connecting in this way, a two-input NOR
The gate 71 sets the count value of the ternary counter 70 to (0,
0), a high level is output, and the two-input AND gate 74 outputs the high-level signal only while the external clock CLOCK is at the high level.
The drive signal C11 which becomes high level is output. Similarly, when the count value of the ternary counter 70 is (0, 1), the two-input AND gate 73 outputs the external clock CLOCK.
Is high level only during the high level period.
12 is output. When the count value of the ternary counter 70 is (1, 0), the two-input AND gate 72 outputs the drive signal C13 that goes high only while the external clock CLOCK is high.

FIG. 9 is a timing chart showing the timing of each signal in the external counter section 66. In the figure, the horizontal direction shows the time axis based on the external clock CLOCK, and the vertical direction shows the signal line axis. (A) to (g) in FIG.
Are the external clock CLOCK, the output signals A1 and A0 of the ternary counter 70, the output signal C14 of the 2-input NOR gate 71, and the drive signals C11 and 2 of the 2-input AND gate 74, respectively.
A drive signal C12 of the input AND gate 73 and a drive signal C13 of the two-input AND gate 72 are shown.

It is assumed that a reset signal (not shown) is input to the ternary counter 70 immediately before time t0, and the count value becomes (0, 0) at time t0. At time t0, the external clock CLOCK goes high (FIG. 9A), and the output signal A
1 goes low (FIG. 9 (b)) and the output signal A0 maintains the low level (FIG. 9 (c)), so that the output signal C14 of the two-input NOR gate 71 goes high (FIG. 9).
(d)). As a result, the two-input AND gate 74 sets the drive signal C11 to a high level in accordance with the high-level external clock CLOCK and the output signal C14 (FIG. 9E).
Further, the two-input AND gate 73 outputs the high-level external clock CLOCK and the low-level output signal A0 according to
The drive signal C12 is maintained at a low level (FIG. 9 (f)).
Further, the two-input AND gate 72 outputs a high-level external clock CLOCK and a low-level output signal A1 according to the output signal A1.
The drive signal C13 is maintained at a low level (FIG. 9 (g)).

At time t1, the external clock CLOCK goes low (a), and the output signal A1 maintains the low level.
(b) Since the output signal A0 maintains the low level (c), 2
The output signal C14 of the input NOR gate 71 maintains the high level (d). Thereby, the two-input AND gate 74
Changes the drive signal C11 to low level according to the low-level external clock CLOCK and the high-level output signal C14 (e). Further, the two-input AND gate 73 outputs the low-level external clock CLOCK and the output signal A0 according to the output signal A0.
The drive signal C12 is maintained at a low level (f). Furthermore, 2
The input AND gate 72 outputs the low level external clock CLOC.
According to K and the output signal A1, the drive signal C13 is maintained at a low level (g).

At time t2, the external clock CLOCK goes high (a), and the output signal A1 maintains the low level.
(b), the output signal A0 goes high (c), so that the output signal C14 of the two-input NOR gate 71 goes low.
(d). As a result, the two-input AND gate 74 outputs the high-level external clock CLOCK and the low-level output signal C
According to 14, the drive signal C11 is maintained at the low level.
(e). Further, the two-input AND gate 73 sets the drive signal C12 to the high level in accordance with the high-level external clock CLOCK and the output signal A0 (f). Furthermore, a 2-input AND
The gate 72 maintains the drive signal C13 at a low level according to the high-level external clock CLOCK and the low-level output signal A1 (g).

At time t3, the external clock CLOCK goes low (a), and the output signal A1 maintains the low level.
(b) Since the output signal A0 maintains the high level (c), 2
The output signal C14 of the input NOR gate 71 maintains the low level (d). Thereby, the two-input AND gate 74
Is the low level external clock CLOCK and the output signal C1.
According to No. 4, the drive signal C11 is maintained at the low level.
(e). Further, the two-input AND gate 73 changes the drive signal C12 to low level according to the low-level external clock CLOCK and the high-level output signal A0 (f). Furthermore,
A two-input AND gate 72 outputs a low-level external clock.
According to the clock and the output signal A1, the drive signal C13 is maintained at a low level (g).

At time t4, the external clock CLOCK goes high (a), and the output signal A1 goes high.
(b), since the output signal A0 goes low (c), the output signal C14 of the two-input NOR gate 71 maintains the low level (d). As a result, the two-input AND gate 74 maintains the drive signal C11 at the low level according to the high-level external clock CLOCK and the low-level output signal C14 (e). The two-input AND gate 73 outputs a high-level external clock CLOCK and a low-level output signal A0.
, The drive signal C12 is maintained at the low level.
(f). Further, the two-input AND gate 72 sets the drive signal C13 to a high level in accordance with the high-level external clock CLOCK and the output signal A1 (g).

At time t5, the external clock CLOCK goes low (a), and the output signal A1 maintains the high level.
(b) Since the output signal A0 maintains the low level (c), 2
The output signal C14 of the input NOR gate 71 maintains the low level (d). Thereby, the two-input AND gate 74
Is the low level external clock CLOCK and the output signal C1.
According to No. 4, the drive signal C11 is maintained at the low level.
(e). In addition, the two-input AND gate 73 maintains the drive signal C12 at a low level according to the low-level external clock CLOCK and the output signal A0 (f). In addition, two inputs A
The ND gate 72 drives the driving signal C13 in accordance with the low level external clock CLOCK and the high level output signal A1.
Is maintained at a low level (g). After time t6, the external counter unit 66 repeats the operation from time t0 to t5.

FIG. 10 is a timing chart showing the timing of each signal of the entire input interface 16.
In the figure, the horizontal direction shows the time axis based on the pipeline clock PH1, and the vertical direction shows the signal line axis. (A) to (o) of FIG. 3 respectively show an external clock CLOCK, a pipeline clock PH1, drive signals C11, C12, C13, an internal data synchronous clock SYNC, and a pipeline synchronous clock.
SYNC_P, drive signals C21, C22, C23, data DAT
A, the signal L1OUT of the latch L1, the signal L2OUT of the latch L2,
The signal L3OUT of the latch L3 and the internal data DATA_IN are shown.

Although the multiplication rate of the pipeline clock PH1 with respect to the external clock CLOCK is a non-integer multiple in FIG.
Even in a synchronous latch cycle in which the rising of both the external clock CLOCK and the pipeline clock PH1 match, or in an asynchronous latch cycle in which the external clock CLOCK rises and the pipeline clock PH1 falls, the external clock CLOCK
Can be latched by the pipeline clock PH1. That is, the pipeline clock PH1 fetches the data DATA sent from the peripheral device 12 in synchronization with the external clock CLOCK to the microprocessor 15 which operates in synchronization with the pipeline clock PH1 including an asynchronous cycle.

Immediately before time t0, the peripheral device 12 outputs data DATA (D0) to the external bus 40 (FIG. 1).
0 (k)). At time t0, the external clock CLOCK becomes high level (FIG. 10A), so that the external counter 66
The drive signal C11 is set to the high level (FIG. 10C), and both the drive signals C12 and C13 are maintained at the low level (FIG. 10D). Thereby, the selection MOS transistor T
1 turns on, passes D0 of data DATA, and latch L1 holds D0 (FIG. 10 (l)).

Further, the pipeline clock PH1 goes high (FIG. 10 (b)), and the internal data synchronization clock SYN
Since C maintains the high level (FIG. 10 (f)), the pipeline synchronization clock SYNC_P becomes the high level (g). Thus, the internal counter 67 sets the drive signal C21 to high level (FIG. 10 (h)), and maintains both the drive signals C22 and C23 at low level (FIG. 10 (i), (j)). As a result, the selection MOS transistor T4 is turned on and passes the data D0, so that the input latch L4
0 and latch the internal data DATA via the inverter 69.
_IN to the internal bus 21 (FIG. 1) (FIG. 10).
(o)).

At time t1, since the external clock CLOCK maintains the high level (a), the external counter 66 maintains the drive signal C11 at the high level (c), and the drive signal C1 is maintained.
2. Both C13 are maintained at low level (d) and (e). As a result, the selection MOS transistor T1 is kept on, and the selection MOS transistors T2 and T3 are kept off. Further, since the pipeline clock PH1 goes low (b) and the internal data synchronization clock SYNC maintains the high level (f), the pipeline synchronization clock SYNC_P goes low (g). Thereby, the internal counter 67
Make the drive signals C21 to C23 all low level, so that (h), (i), (j), the selection MOS transistors T4 to T6
Are all turned off.

Between the time t1 and the time t2, since the external clock CLOCK is at the low level (a), the external counter 6
6 sets the drive signal C11 to low level (c), and maintains both drive signals C12 and C13 at low level (d),
(e). As a result, the selection MOS transistor T1 is turned off, and the selection MOS transistors T2 and T3 are kept off.

At time t2, the pipeline clock PH1
Goes high (b) and the internal data synchronization clock SYNC
Becomes low level (f), the pipeline synchronization clock SYNC_P maintains low level (g). As a result, the internal counter 67 maintains the drive signals C21 to C23 at the low level, respectively, so that (h), (i), and (j) keep the selection MOS transistors T4 to T6 off.

At the rise of the pipeline clock PH1 at time t2, since the peripheral device 12 has not output the next data, the timing generation circuit 17 sets the internal data synchronization clock SYNC so as not to take in the data DATA at this timing. Set to low level. The timing at which the signal is set to the low level is preset in the timing generation circuit 17.

Since the external clock CLOCK goes high between time t2 and time t3 (a), the external counter 6
6, the drive signal C11 is maintained at a low level (c), the drive signal C12 is maintained at a high level (d), and the drive signal C13 is maintained at a low level (e). As a result, the selection MOS transistor T1 is kept off, the selection MOS transistor T2 is turned on, and the selection MOS transistor T3 is turned on.
Keep off. Therefore, the selecting MOS transistor T2 passes the data DATA D1 (k), and the latch L2
Holds D1 (m).

At time t3, the pipeline clock PH1
Goes low (b) and the internal data synchronization clock SYNC
Maintain the low level (f), the pipeline synchronization clock SYNC_P maintains the low level (g). As a result, the internal counter 67 maintains the drive signals C21 to C23 at the low level, respectively, so that (h), (i), (j), the selection MO
Each of the S transistors T4 to T6 keeps off.

At time t4, since the external clock CLOCK goes low (a), the external counter 66 keeps the drive signal C11 low (c), sets the drive signal C12 low (d), and sets the drive signal C13 Is maintained at a low level (e). Thereby, the selection MOS transistor T
1 and T3 are kept off, and the selecting MOS transistor T2 is turned off. Also, the pipeline clock PH1
Goes high (b) and the internal data synchronization clock SYNC
Becomes high level (f), the pipeline synchronization clock SYNC_P becomes high level (g). As a result, the internal counter 67 sets the drive signal C22 to the high level (i) while maintaining the drive signals C21 and C23 at the low level (h) and (j). Therefore, the selection MOS transistors T4 and T6 each maintain the off state, and the selection MOS transistor T5 is turned on. Therefore, the selection MOS transistor T5 is turned on and the data DATA D1 is passed, so that the input latch L4 latches D1 and the internal bus 21 as the internal data DATA_IN via the inverter 69.
(Fig. 1) (o).

At time t5, the pipeline clock PH1
Goes low (b) and the internal data synchronization clock SYNC
Maintain the high level (f), the pipeline synchronization clock SYNC_P goes low (g). As a result, the internal counter 67 sets all the drive signals C21 to C23 to low level, so that (h), (i), and (j), all the selection MOS transistors T4 to T6 are turned off.

Since the external clock CLOCK is at the high level between the time t5 and the time t6 (a), the external counter 66 maintains the drive signals C11 and C12 at the low level, respectively (c) and (d). , The drive signal C13 is set to the high level (e).
As a result, the selection MOS transistors T1 and T2 are kept off, and the selection MOS transistor T3 is turned on. Therefore, the selection MOS transistor T3 is
Data passes through D2 (k), and latch L2 holds D2 (m).

At time t6, the pipeline clock PH1
Goes high (b) and the internal data synchronization clock SYNC
Maintain the high level (f), the pipeline synchronization clock SYNC_P becomes the high level (g). Accordingly, the internal counter 67 maintains the drive signals C21 and C22 at low level (h) and (i), and sets the drive signal C23 to high level (j), so that the selection MOS transistors T4 and T5
Are kept off, and the selecting MOS transistor T6 is turned on. Therefore, the selection MOS transistor T6
Passes through the data D2, the input latch L4
Latches D2 and stores the internal data via inverter 69.
It is supplied as DATA_IN to the internal bus 21 (FIG. 1) (o).

Between the time t6 and the time t7, the external clock CLOCK goes low (a),
6 maintains the drive signals C11 and C12 at low levels (c) and (d), and sets the drive signal C13 to low level (e). Thus, the selection MOS transistors T1 and T2 are kept off, and the selection MOS transistor T3 is turned off.

At time t7, the pipeline clock PH1
Goes low (b) and the internal data synchronization clock SYNC
Maintain the high level (f), the pipeline synchronization clock SYNC_P goes low (g). Accordingly, the internal counter 67 maintains the drive signals C21 and C22 at low level (h) and (i), and sets the drive signal C23 to low level (j), so that the selection MOS transistors T4 to T6
Are all turned off. After time t8, the input interface 16 repeats the same operation as at times t0 to t7.

In the above description, an example is shown in which the data DATA is continuously input in synchronization with the external clock CLOCK. However, the data DATA may be discontinuous. Also, the reset signal RESE
T is the microprocessor 1 if the clocks CLOCK and SYMC_P are continuously supplied to the counters 66 and 67.
(5) It may be only necessary to reset once at startup. The reset may be performed each time the microprocessor 15 issues a read instruction. The number of latches L1 to L3 is not limited to three, but can be increased or decreased as appropriate.

As described above, in the input interface 16 of this embodiment, the selection MOS transistors T1 to T3 are sequentially turned on at predetermined time intervals, and the data D0 to D4 in the data DATA are latched L1 to L3.
At the same time, and in response to this, the data D0 to D6 are selected by the selecting MOS transistors T4 to T6 which are sequentially turned on.
4 can be entered in this order.

As described above, according to the data processing system of the present embodiment, even when the multiplication rate between the external clock CLOCK and the pipeline clock PH1 (internal clock) is a non-integer multiple, the input interface 16 As a result, the asynchronousness between the pipeline clock PH1 and the external clock CLOCK can be absorbed, and signals can be properly transmitted and received between the inside and outside of the MPU. Thus, the MPU can be operated at the highest performance inside and outside the MPU, that is, at the highest frequency, and the highest performance of the entire system can be obtained.

[Third Embodiment] Next, a third embodiment of the present invention will be described. FIG. 11 is a circuit diagram illustrating an input interface of the data processing system according to the present embodiment. In the figure, the same reference numerals are given to the same circuit elements as those in the second embodiment described with reference to FIG. In the data processing system of the present embodiment, the basic configuration other than the input interface 16 and the timing generation circuit 17 is the same as that of the data processing system described in FIG. The ratio between the external clock CLOCK and the internal clock PH1 in the embodiment is M: N.
(M and N are positive integers) will be described.

The input interface 16 in the present embodiment includes M latches L1, L2,... LM each having the same configuration as that of FIG. 7, and one input latch L4. The input interface 16 further includes an external synchronous decoder 75, an internal synchronous decoder 76, an inverter 68,
69. Inverter 6 to which data DATA is input
LM and select MOS transistors TA1 to TAM are inserted between the latches L1, L2,... LM, respectively. The drive signals C11 to C1M of the external synchronous decoder 75 are supplied to the gates of the selection MOS transistors TA1 to TAM, respectively. The input latch L4 and each of the latches L1, L2.
..Selection MOS transistors TB1 to TB
BM is inserted respectively. Selection MOS transistor TB
Drive signals C21 to C2M of the internal synchronous decoder 76 are supplied to the gates 1 to TBM, respectively. At reset,
The reset signal RESET is supplied to the external synchronous decoder 75 and the internal synchronous decoder 76, respectively.

The input interface 16 is connected to a timing setting circuit 98 in place of the timing generating circuit 17, and the timing setting circuit 98 includes an external synchronization setting register 77 and an internal synchronization setting register 78. The external synchronization setting register 77 and the internal synchronization setting register 78 relate to signals for driving the selection MOS transistors TA1 to TAM and TB1 to TBM based on a register setting command sent from a ROM (not shown) or the like via the internal bus 21. Information is written.

In the above-described second embodiment, for example, the frequency ratio M: N between the external clock CLOCK and the internal clock PH1 is 3: 4, and the data input corresponding to three cycles of the external clock CLOCK is performed. DATA is the internal clock PH for 4 cycles
It was fetched by three clocks out of one. In order to delete one of PH1 out of four continuous internal clocks in accordance with the internal data synchronization clock SYNC generated by the timing signal generation circuit 17, a selection signal generation circuit 97 is provided to generate the pipeline synchronization clock SYNC_P. . In contrast,
In the third embodiment, the pattern of the internal clock is generated according to the frequency ratio M: N without using the timing signal generation circuit 17 and the selection signal generation circuit 97 which are dedicated circuits.

The external synchronization setting register 77 in this embodiment is for setting the number of selection MOS transistors TA, TB to M. For example, if the ratio between the external clock CLOCK and the internal clock PH1 is M: N =
In the case of 2: 5, the selection MOS transistors TA1 to TA1
The value of M is set in the external synchronization setting register 77 so that the selection up to TA2 is used, and when M: N = 3: 4, the selection MOS transistors TA1 to TA3 are used.

The external synchronizing decoder 75 and the internal synchronizing decoder 76 read the set value M from the external synchronizing setting register 77, and set the external counter and the internal counter (66 in FIG. 7).
67) is set in the M-ary counter. As a result, the external synchronous decoder 75 can sequentially generate the drive signals C11 to C1M in synchronization with the external clock CLOCK.

In the present embodiment, the internal synchronization setting register 78 stores M out of N clocks of the internal clock PH1.
It has a function of selecting a clock and a function of determining which clock is selected or non-selected. For example, in the above-described second embodiment, data DATA is captured by three of the four pipeline clocks PH1 shown in (b) of FIG. At the clock PH1, the data DATA is not fetched and the first, third, fourth
Only the second internal clock PH1 was enabled. To realize this, the internal synchronization setting register 78 stores “101”
A selection pattern such as 1 "is written in advance. This selection pattern is determined by the ratio between the external clock CLOCK and the internal clock PH1, and can be set in a programmable manner.

The internal synchronous decoder 76 reads the selected pattern from the internal synchronous setting register 78, and outputs the selected pattern in synchronization with the internal clock PH1, thereby corresponding to the pipeline synchronous clock SYNC_P (FIG. 10 (g)). A signal can be generated. By inputting the signal corresponding to the pipeline synchronization clock SYNC_P to the counter section shown in FIG. 8, drive signals C21 to C2M can be obtained. As for M, as described above, the internal counter section (corresponding to 67 in FIG. 7) is set to an M-ary counter by the external synchronization setting register 77.

FIG. 12 is a block diagram showing the internal configuration of the clock generation circuit 19 in this embodiment. The clock generation circuit 19 receives a frequency divider 79 that divides the external clock CLOCK by M and outputs a second clock CLK2, and a PLL that receives the second clock CLK2 and generates N times the frequency of the second clock CLK2.
A circuit 19a and a multiplication rate setting register 8 for setting a multiplication rate
And 3.

The PLL circuit 19a includes a PD 80, a VCO 8
1 and a frequency divider 82 of N frequency division. PD8
0 compares the input signal CLK2 with a signal obtained by dividing the frequency of the VCO 81 by N, and controls the oscillation frequency and phase of the VCO 81 with the phase difference output.

The multiplication rate setting register 83 includes a frequency divider 79,
The frequency division numbers M and N of 82 are set, and the multiplication rate of the clock generation circuit 19 is determined. The multiplication rate setting register 83 stores the frequency divider 7 based on a register setting command sent from a ROM (not shown) via the internal bus 21.
The numerical values of the clock numbers M and N of 9, 82 are rewritten.

The clock generation circuit 19 having such a configuration generates an M-divided clock (second clock CLK2) by dividing the external clock CLOCK by M, and further multiplies the M-divided clock by N to obtain an internal clock. Generate a clock (pipeline clock PH1).

The external synchronizing decoder 75 and the internal synchronizing decoder 76 take in the second clock CLK2 and the pipeline clock PH1 output from the clock generation circuit 19, respectively, and drive signals C11 to C1M and C21 to C2M, respectively. Generate.

In this embodiment having the above configuration, the external synchronization setting register 77 and the internal synchronization setting register 78 are provided.
However, the values related to the clock numbers M and N are rewritten based on the register setting command supplied from the internal bus 21. Further, the external synchronous decoder 75 and the internal synchronous decoder 76 receiving the signal from the external synchronous setting register 77
Selection MOS transistors TA1 to TAM, TB1 to T
The number corresponding to the used number M is selected from the BMs and used. Further, the internal synchronous decoder 76 that has received the signal from the internal synchronous setting register 78 sets a built-in selection pattern and determines M clocks among the N internal clocks of the pipeline clock PH1.

As a result, from the external synchronous decoder 75,
The drive signals C11... Corresponding to the selection MOS transistors TA to be used are sequentially output at predetermined time intervals, and the corresponding selection MOS transistors TA1.・
Are held by the latches L1... Corresponding to the selection MOS transistors TA.
...

The internal synchronization decoder 76 outputs a selection M corresponding to the M clock set by the selection pattern.
.. For turning on the OS transistors TB1... Are sequentially output at predetermined time intervals. Thereby, the selected MOS transistor for selection TB1 is selected.
Are sequentially turned on at predetermined time intervals, and are held in latches L1... Corresponding to the selected MOS transistors TA1. Furthermore, latches L1.
From the selection MOS transistor TB1 which is sequentially turned on.
The data DATA sent through the input latch L4
Are input to the microprocessor 15 as input data DATA_IN while latching the input order of the original data D0.

As described above, according to the data processing system of the present embodiment, the latches L1 to LM as input holding registers are provided in the input interface 16 before the input latch L4, and the outputs of the latches L1 to LM are output. Since the data is sequentially latched by the input latch L4,
Even if an asynchronous latch cycle in which the latch timing is delayed occurs, a correct input signal can be reliably latched. That is, the pipeline clock PH1
Asynchronism between the MPU and the external clock CLOCK is absorbed, so that signals can be properly exchanged between the inside and outside of the MPU. Further, since the relationship M: N of the clock frequency between the external clock CLOCK and the pipeline clock PH1 can be set programmably, it is necessary to operate the MPU in a state close to the maximum performance inside and outside the MPU, that is, a state close to the guaranteed maximum frequency. To get the best performance of the whole system.

The reset signal RESET is used to initialize the counters in the external synchronous decoder 75 and the internal synchronous decoder 76. If the clocks CLOCK and PH1 are continuously supplied to the counter, the reset signal RESET is used. Fifteen
It may be just reset once at startup. Alternatively, the counter unit may be reset each time the microprocessor 15 issues a read instruction.

[Fourth Embodiment] Next, a fourth embodiment of the present invention will be described. In the first to third embodiments,
Microprocessor 15 transmits asynchronous input data from outside.
In this example, the internal data in the microprocessor 15 is output to the outside. Also in the present embodiment, the case where the multiplication rate between the external clock CLOCK and the pipeline clock PH1 is a non-integer multiple and the frequency ratio M: N is 4: 7 will be described.

FIG. 13 is a block diagram showing the internal configuration of the output interface in this embodiment. The output interface 20 includes inverters 91 and 92 provided on the input side of the internal data DATA_IN, and latches L1 to L
4, an inverter 89, a 4-input OR gate 90, an external synchronization counter 85, an internal synchronization counter 86,
A comparator 87 that outputs a comparator output based on the outputs of both the external synchronization counter unit 85 and the internal synchronization counter unit 86
And a write synchronization signal generation circuit 88. The latches L1 to L4 have the same configuration as the latches L1 to L4 in the second embodiment described with reference to FIG. 7, and hold the data D0 to D3 in the captured internal data DATA_IN, respectively.

Select MOS transistors T5 to T8 are inserted between the inverter 91 and the latches L1 to L4, respectively. The internal synchronization counter unit 86 applies a write signal W to each gate of the selection MOS transistors T5 to T8.
Drive signals C21 to C24 generated according to R are provided, respectively. Here, the write signal WR is a signal that the microprocessor 15 outputs in synchronization with the write data DATA_IN, and is a signal that rises when the data DATA_IN becomes valid.

The inverter 89 and each of the latches L1 to L
4, selection MOS transistors T1 to T4 are inserted respectively. Selection MOS transistors T1 to T1
The drive signals C11 to C1 generated by the external synchronization counter unit 85 based on the external clock CLOCK are provided to each gate of T4.
4 are each given. At the time of reset of the microprocessor 15 or before the start of writing, a reset signal RESET is supplied to the external synchronization counter unit 85 and the internal synchronization counter unit 86, respectively, and the counter units 85 and 86 are initialized.

The comparator 87 compares the count value of the external synchronization counter unit 85 with the count value of the internal synchronization counter unit 86, and determines that both the count value of the external synchronization counter unit 85 and the count value of the internal synchronization counter unit 86 are correct. It outputs a low level when it is “0”, and outputs a high level when the count value of the external synchronization counter unit 85 is less than or equal to the count value of the internal synchronization counter unit 86. That is, the comparator 87 goes high when the internal synchronization counter 86 starts counting, and when the count value of the external synchronization counter 85 becomes the same as the count value of the internal synchronization counter 86, the next rising of the external clock. It goes low when falling. The output of the comparator 87 is output to the microprocessor 15 as an end signal O_END.
And the microprocessor 15 outputs the end signal O_END
Is detected, it is determined that the next data can be output.

The write synchronization signal generation circuit 88 outputs the write enable signal WE in synchronization with the external clock CLOCK from the rising edge of the external clock CLOCK after the output O_END of the comparator 87 goes high until the output O_END goes low. And outputs a data capture timing signal to the peripheral device 12.

The four-input OR gate 90 outputs the drive signal C11
To C14 are at a high level, and a high level is output. When all the drive signals C11 to C14 are at a low level, a low level is output. This output is output to inverter 8
9 is supplied to the control terminal.

Inverter 89 is an inverter (three-state inverter) having three output states, inverts and amplifies an input signal when the control terminal is at a high level, and outputs the result. When the control terminal is at a low level, the output is floating. State. This prevents the output of the peripheral device 12 connected to the same bus from colliding with the output of the microprocessor 15.

FIG. 14 is a timing chart showing the timing of each signal of the output interface 20 in this embodiment. In the figure, the horizontal direction shows the time axis based on the pipeline clock PH1, and the vertical direction shows the signal line axis. (A) to (m) of the figure respectively show a pipeline clock PH1, an external clock CLOCK, internal data DATA_IN,
A write signal WR that determines the timing of capturing data on the internal bus 21, an output of the latch L1, an output of the latch L2, an output of the latch L3, an output of the latch L4, an output of the external synchronization counter 85, an output of the comparator 87, and reset signal
RESET, data DATA, and write enable signal WE
Is shown.

In the output interface 20, at time t0 after the reset signal RESET is supplied, the pipeline clock PH1 goes high (FIG. 14 (a)), and the write signal WR maintains the low level (FIG. 14 (a)). d)), the internal data DATA_IN sends D0 via the inverters 91 and 92 (FIG. 14 (c)), and the external clock CLOCK goes high (FIG. 14 (b)).

At time t1, the pipeline clock PH1
Becomes low level (a) and the write signal WR becomes high level (d), so that the drive signal C21 becomes high level and the selection MOS transistor T5 is turned on. As a result, the latch L1 latches and holds D0 of the internal data DATA_IN (e). At the same time, the comparator output 87 changes at time t15.
It goes high until it exceeds (j).

Between times t1 and t2, the external clock CL
OCK goes low, and the drive signal C11, which is the output of the external synchronization counter 85, goes high (i).
The selection MOS transistor T1 is turned on, and the latch L
The output D0 of 1 is started to be sent to the outside via the inverter 89.

At time t2, the pipeline clock PH1
Becomes high level (a), and the write signal WR becomes low level (d), the drive signal C21 becomes low level, the selection MOS transistor T5 is turned off, and the transmission of the internal data DATA_IN D0 ends (c). ).

At time t3, pipeline clock PH1
Becomes low level (a), the write signal WR becomes high level (d), the drive signal C22 becomes high level, the selection MOS transistor T6 is turned on, the D1 of the internal data DATA_IN is sent, and the latch L2 is turned on. D1 is latched and held (f).

Between times t3 and t4, the output of the comparator is at the high level (j), the external clock CLOCK is at the high level (b), and the write enable signal WE is at the high level. Latch L sent out between
The output D0 of 1 is supplied to the external bus 40.

At time t4, pipeline clock PH1
Becomes high level (a), and the write signal WR becomes low level (d), the drive signal C22 becomes low level, the selection MOS transistor T6 is turned off, and the transmission of D1 of the internal data DATA_IN ends (c). ).

At time t5, the pipeline clock PH1
Becomes low level (a), and the write signal WR becomes high level (d), the drive signal C23 becomes high level, the selection MOS transistor T7 is turned on, D2 of the internal data DATA_IN is sent, and the latch L3 is turned on. D2 is latched and held (g).

Between time t5 and time t6, the external clock CL
OCK goes low, and the drive signal C11 from the external synchronization counter unit 85 goes low (i), the selection MOS transistor T1 is turned off, and the capture of the output D0 from the latch L1 ends (l). At the same time, the external clock CLOCK goes low and the drive signal C12 goes high, turning on the selecting MOS transistor T2 and starting to send the output D1 of the latch L2 to the inverter 89 to the outside.

At time t6, pipeline clock PH1
Becomes high level (a), and the write signal WR becomes low level (d), the drive signal C23 goes low level, the selection MOS transistor T7 turns off, and the transmission of the internal data DATA_IN D2 ends (c). ).

At time t7, the pipeline clock PH1
Becomes low level (a), the write signal WR becomes high level (d), the drive signal C24 becomes high level, the selection MOS transistor T8 is turned on, D3 of the internal data DATA_IN is sent, and the latch L4 is turned on. D3 is latched and held (f). At the same time, when the comparator output
(j), the external clock CLOCK goes high (b) and the write enable signal WE goes high,
5 and the output D1 of the latch L2 sent out between t6
Is supplied to the external bus 40.

At time t8, the pipeline clock PH1
Becomes high level (a), and the write signal WR becomes low level (d), the drive signal C24 becomes low level, the selection MOS transistor T8 is turned off, and the transmission of the internal data DATA_IN D3 ends (c). ). After the transmission of D3, the microprocessor 15 outputs the next data DATA_B until the external clock CLOCK goes low and the comparator output goes low between times t15 and t16 (b) and (j).
This is the MPU output prohibition period during which IN is not output. The pipeline clock PH1 and the external clock CLOCK match at time 14, but the comparator output is not set to the low level at this time, but is set to the low level after one clock of the external clock CLOCK has elapsed, and the end signal O_END ( 13) is output, the MPU output inhibition period is released.

Between time t8 and t9, the external clock CL
Since OCK becomes low level and the drive signal C12 from the external synchronization counter unit 85 becomes low level (i), the selection MOS transistor T2 is turned off, and the capture of the output D2 from the latch L2 ends (l). At the same time, the external clock CLOCK goes low and the drive signal C13 goes high, turning on the selecting MOS transistor T3 and starting to send the output D2 of the latch L3 to the external bus 40 via the inverter 89. Hereinafter, the process proceeds in the same manner as described above.

In the output interface 20 of the present embodiment driven as described above, after the reset signal RESET is supplied, the drive signals C21 to C24 are transmitted from the internal synchronization counter 86 at predetermined time intervals based on the write signal WR. Are sequentially output, and the selection MOS transistors T5 to T5 are output.
T8 is sequentially turned on at predetermined time intervals, and the internal data DA
TA_IN is sequentially supplied to the latches L1 to L4.

By sequentially turning on selection MOS transistors T1 to T4 at predetermined time intervals in accordance with drive signals C11 to C14 from external synchronization counter unit 85, data D0 to D4 are sequentially read from latches L1 to L4. And output while the comparator 87 outputs the comparator output.

The drive signal C1 from the external synchronization counter 85
While any one of 1 to C14 is outputting high, the 4-input OR gate 90 outputs high, so that the inverter 89
Are ready to output the internal data DATA_IN to the external bus 40. However, when all the outputs of the drive signals C11 to C14 become low level, the 4-input OR gate 90 outputs low, the inverter 89 is floated, and the connection to the external bus 40 is cut off. It should be noted that as a signal for making the inverter 89 floating, FIG.
Can be inputted to the inverter 89.

As described above, in the data processing system of the present embodiment, even if the multiplication rate between the external clock CLOCK and the pipeline clock PH1 is a non-integer multiple, the pipeline clock is output inside the output interface 20. Absorbs the asynchrony between PH1 and external clock CLOCK.
Signals can be properly transmitted and received between the inside and the outside. Thus, the MPU can be operated at the highest performance inside and outside the MPU, that is, at the highest frequency, and the highest performance of the entire system can be obtained.

By the way, in the fourth embodiment, as shown in FIG. 14, the comparator output becomes low level between time t15 and time t16, that is, the latches L1 to L4
Until all the latched data is output, an MPU output prohibition period in which the next internal data DATA_IN is not received any more is provided. On the other hand, if the pointer method is adopted, the next D4, D5,... Can be received continuously to D3 of the internal data DATA_IN without providing the MPU output prohibition period. That is, the function of the comparator 87 may be changed, the write points of the latches L1 to L4 may be constantly compared with the read points, and control may be performed so that the write points do not overtake the read points.

For example, data is stored in all the latches L1 to L4.
It is assumed that DATA_IN is latched and the data DATA of the latch L3 is output to the external peripheral device 12. At this time, the value (second pointer) of the external synchronization counter unit 85 is “02”. Therefore, the comparator 87 checks the count value (first pointer) of the internal synchronization counter unit 86, and if the value is equal to or smaller than "01", the comparator 87 determines that the next data DATA_IN can be written in the latches L1 and L2, and A status signal indicating that writing is possible is output to the processor 15, and the microprocessor 15 detects this and outputs the next data. Here, when data is written up to the latch L2 and the count value of the internal synchronization counter unit 86 becomes "01", the comparator 87 outputs a write-inhibit status signal. This is because when the next data is written to the currently output latch L3, the output data DATA changes, and it becomes difficult to determine whether the peripheral device 12 on the receiving side captures the previous data or the subsequent data. This is to avoid.

As described above, the status of writing / reading for the first and second pointers is constantly checked. Accordingly, in response to the transmission state of the internal data DATA_IN, the point position,.
, The data D0 to D4 of the internal data DATA_IN are sequentially written, and the data D0 to D4 of the point positions,... Of the second pointer on the receiving side are sequentially read later than the first pointer. Here, for example, the second
By recognizing that the pointer of the second pointer is vacant when the pointer value of the pointer becomes larger, it is possible to continue to receive the data following D0 to D4 of the internal data DATA_IN.

[Fifth Embodiment] Next, a fifth embodiment of the present invention will be described. FIG. 15 is a block diagram illustrating the data processing system 93 according to the present embodiment.

Usually, not only one kind of peripheral device 12 but also various kinds of peripheral devices are connected. The guaranteed maximum operating frequencies of these peripheral devices are not uniform, and each has its own guaranteed maximum operating frequency. In the first to fourth embodiments, the peripheral device 12 having the lowest guaranteed maximum operating frequency is
The frequency of the external clock CLOCK was determined in accordance with. Therefore, if a second peripheral device (external device) 96 that operates faster than the lowest peripheral device 12 is connected,
The maximum performance of the peripheral device 96 could not be exhibited. In the present embodiment, even if the peripheral devices 12 and 96 having different guaranteed maximum operating frequencies are connected to the MPU 94, their respective maximum performances can be exhibited.

In this embodiment, the microprocessor 94
In addition to the first peripheral device 12 operating with the first external clock CLOCK connected via the external bus 40,
A second peripheral device (external device) 96 that operates with the external clock CLOCK 2 is connected via the external bus 40.
The second external clock CLOCK2 is supplied to the microprocessor 9
4 may be the same pipeline clock PH1,
It may be an integer ratio of 1: N or a non-integer ratio of M: N. Further, an input / output interface 95 for exchanging data with the peripheral device 96 is provided in the microprocessor 94.

The input / output interface 95 has a different timing from the input interface 16 and the output interface 20. For example, if the guaranteed maximum operating frequency of the microprocessor 94 is 250 MHz and that of the peripheral device 12 is 100 MHz, if the guaranteed maximum operating frequency of the second peripheral device 96 is 200 MHz, the aforementioned M:
N may be set to 4: 5, and if it is 250 MHz, 1:
It should be set to 1.

As described above, the performance of the data processing system can be maximized by operating the microprocessor and the peripheral device at their guaranteed maximum operating frequencies. That is, the number of instructions that can be processed by the microprocessor per unit time can be maximized. Also, since the internal clock frequency is higher than the external clock frequency, the microprocessor has a margin for internal processing, and by using this margin to execute other processing, the performance can be further improved. For example, it is possible to perform processing such as accessing a cache memory or the like to obtain necessary data by using a vacant time from accessing a peripheral device to fetching data.

The present invention has been described based on the preferred embodiment. However, the data processing system of the present invention is not limited to the configuration of the above-described embodiment, and is not limited to the configuration of the above-described embodiment. Various modifications and changes of the data processing system are also included in the scope of the present invention.

[0213]

As described above, according to the data processing system of the present invention, even when the multiplication rate between the external clock and the internal clock is a non-integer multiple, the data processing system between the MPU internal clock and the external clock is not used. By absorbing the asynchronicity and properly transmitting and receiving signals between the inside and outside of the MPU, M
The PU can be operated at the highest performance inside and outside the PU, that is, at the highest frequency, and the highest performance of the whole system can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a data processing system according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a main part of an internal configuration of an input interface.

FIG. 3 is a timing chart showing output timing of each signal in the input interface shown in FIGS. 1 and 2;

FIG. 4 is a block diagram illustrating an internal configuration of a clock generation circuit.

FIG. 5 is a block diagram illustrating an internal configuration of a timing generation circuit.

FIG. 6 is a timing chart showing the timing of each signal in the timing generation circuit.

FIG. 7 is a circuit diagram showing an input interface according to a second embodiment of the present invention.

FIG. 8 is a circuit diagram showing an internal configuration of an external counter unit according to the second embodiment.

FIG. 9 is a timing chart showing the timing of each signal of an external counter unit in the second embodiment.

FIG. 10 is a timing chart showing the timing of each signal of the entire input interface according to the second embodiment.

FIG. 11 is a circuit diagram showing an input interface of a data processing system according to a third embodiment of the present invention.

FIG. 12 is a block diagram illustrating an internal configuration of a clock generation circuit according to a third embodiment;

FIG. 13 is a block diagram showing an internal configuration of an output interface according to a fourth embodiment of the present invention.

FIG. 14 is a timing chart showing the timing of each signal of an output interface in the fourth embodiment.

FIG. 15 is a block diagram showing a data processing system according to a fifth embodiment of the present invention.

FIG. 16 is a timing chart for explaining a restriction in a conventional setup / hold time.

[Explanation of symbols]

 11: MPU 12, 96: Peripheral device 13: Oscillation circuit 15, 94: Microprocessor 16: Input interface 17: Timing generation circuit 19: Clock generation circuit 20, 95: Output interface 21: Internal bus 40: External bus 42: Input Buffer 43: input holding register 46: input latch 66: external counter 67: internal counter 70: ternary counter 77: external synchronization setting register 78: internal synchronization setting register 95: input / output interface L1 to LM: latch T1 to T8: selection MOS transistors for TA1 to TAM: MOS transistors for selection TB1 to TBM: MOS transistors for selection CLOCK: External clock CLK_REG: External synchronous latch clock DATA: Data PH1: Pipeline clock (internal clock) SYNC: Internal data synchronous clock SYNC_RE: Internal Sync Latch clock

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 9/30-9/355 G06F 1/04-1/14

Claims (8)

(57) [Claims] 1. A data processing system wherein input data sent from an external device in synchronization with an external clock is input to a microprocessor operating on an internal clock including an asynchronous cycle, Input / output means for receiving input data and outputting the input data in synchronization with the internal clock, wherein the input / output means holds the input data until a predetermined timing at which the input data can be latched by the internal clock, and A data processing system comprising holding means for inputting data to a processor. 2. An input interface for receiving input data from the external device, and a timing generation circuit for generating a timing signal for adjusting a latch timing in the input interface, wherein the holding unit converts the input data into the input data. 2. The data processing according to claim 1, further comprising: an input holding register that latches in response to a timing signal; and an input latch that latches an output of the input holding register in response to a level change of the internal clock. system. 3. A plurality of first latch circuits each of which latches input data sequentially inputted in synchronization with the external clock, and wherein the plurality of first latch circuits operate in response to the internal clock. 3. The data processing system according to claim 2, further comprising a second latch circuit that latches an output of the latch circuit in the order of input of the original input data. 4. A clock generation circuit for generating an M-divided clock by dividing an external clock by M, and further multiplying the M-divided clock by N to generate the internal clock, wherein the timing generation circuit comprises: Fetching the M-divided clock and the internal clock from the clock generation circuit, respectively,
4. The data processing system according to claim 2, wherein an external synchronization latch clock, an internal synchronization latch clock, and an internal data synchronization clock are generated, respectively. 5. The cache memory according to claim 1, further comprising a cache memory, wherein when the frequency of said internal clock is higher than the frequency of said external clock, said cache memory is emptied by taking in input data synchronized with said external clock. 5. A process for accessing data and an address necessary for the process described in claim 1.
Data processing system according to the item. 6. A data processing system in which internal data sent from a microprocessor in synchronization with an internal clock is output to an external device operating in accordance with an external clock, wherein the internal data is fetched in synchronization with the internal clock. An input / output unit that outputs the internal data in synchronization with the external clock, wherein the input / output unit holds the internal data until a predetermined timing that can be latched by the external clock and outputs the internal data to the external device. A data processing system comprising a holding unit. 7. An output interface for taking in internal data of the microprocessor, and timing generating means for generating a timing signal for adjusting a latch timing in the output interface, wherein the holding means converts the internal data to the timing. 7. An output holding register for latching in response to a signal, and output means for outputting an output of the output holding register in response to a level change of the external clock.
2. A data processing system according to claim 1. 8. The output interface includes a plurality of latch circuits respectively latching output data sequentially output in synchronization with the internal clock, wherein the plurality of first latches operate in response to the external clock. 8. The data processing system according to claim 7, wherein outputs of the circuit are output in the order of output of the original internal data.