JP3186107B2 - Insulated gate field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate field effect transistor in which a drain current is not affected by a temperature fluctuation of a substrate.

[0002]

BACKGROUND OF THE INVENTION showing the relationship between the gate voltage V _G and the drain current I _D of the insulated gate field effect transistor [V _G
− ( _ID ) ^1/2 ] In the characteristic curve, the ZTC point (Zero Te
The term “mpera-ture Coeffcient Point” refers to a point where a curve intersects a point at a temperature change. At this point ZTC, the gate voltage V _G (ZTC) or the drain current I
_D (ZTC). That is, the gate voltage V _G (ZTC)
Has no temperature dependency in the drain current I _D (ZTC). Therefore, if the ZTC point is used as the operating point of the insulated gate field effect transistor, the influence of a temperature change can be reduced.

[0003]

However, the above ZTC
The point is a point uniquely determined by the process conditions of semiconductor manufacturing (impurity concentration, gate oxide film thickness, etc.). FIG. 11 shows a basic form of a digital circuit including a CMOS inverter and a load capacitance. FIG. 11A shows the state of charge of the load capacitance C, and FIG. 11B shows the state of discharge of the load capacitance C. The operation speed of the digital circuit is determined by the charging and discharging time of the load capacitance C. The potential at point B is represented by Q = CV. The time change is dQ / dt = C (dV / dt) (note that the load capacity C is assumed to be substantially constant with time). The current driving capability (drain current _ID ) of the insulated gate field effect transistor decreases as the temperature of the substrate increases (see FIG. 10). This is because the above equation dQ / dt = C (dV /
In dt), dQ / dt is equal to a decrease, and the charge / discharge time is lengthened. Then, the operation speed of the digital circuit decreases. Here, the input voltage V
_{If in} (gate voltage V _G ) is at the ZTC point, the current driving capability (drain current I _D ) of the insulated gate field effect transistor does not change much even if the temperature rises. In general, the input voltage V of the inverter is inside the digital circuit.
_in becomes the power supply voltage V _DD and the ground potential 0 V. Therefore, in order to control the operation speed of such a digital circuit so as not to decrease, a voltage near the ZTC point may be used as the power supply voltage _VDD . But the usual Z
Since the gate voltage V _G at the TC point is as small as 1 to 2 V, which used to supply voltage V _DD is not practical. FIG. 12 is a circuit diagram showing an electrical configuration of a CMOS operational amplifier which is an analog circuit. V _bias is a fixed bias. By using the voltage at the ZTC point for V _bias , an operational amplifier having excellent temperature characteristics can be obtained. However, as described above, the ZTC point is uniquely determined by the process conditions. Therefore, when the ZTC point deviates from the design value due to the semiconductor manufacturing process conditions, there has been no method of adjusting the ZTC point.

[0004] The present invention has been made to solve the above problems, it is an object of the ZTC point that was uniquely determined by the process conditions of the semiconductor manufacturing, the threshold voltage V _T It is an object of the present invention to provide an insulated gate field effect transistor in which the gate voltage at the ZTC point is controlled to increase.

[0005]

According to an embodiment of the present invention, there is provided an insulated gate field effect transistor having a plurality of trimming resistors having different temperature dependencies.
By adding a bias circuit using a resistance , the substrate potential is changed in accordance with the temperature change of the substrate.
Shift the position of the point to the side with higher gate voltage and gate current.
Characterized in that to bets. Insulated gate field effect
In transistors, multiple transistors with different temperature dependencies
Adding a bias circuit using rimmable resistors
Changes the substrate potential in accordance with the substrate temperature fluctuation.
And trimming after manufacturing
Control of the position of the ZTC point by adjusting the resistance
It is characterized by the following .

[0006]

In the case of insulated gate field effect transistor of the operation and effect] n-channel type, the substrate potential is more bias circuit using an additional temperature dependence different trimmable resistor, the temperature rise of the substrate It is raised with. In the case of a p-channel insulated gate field effect transistor, the substrate potential is increased by the bias circuit using a plurality of trimmable resistors having different temperature dependencies. Decreases as the temperature rises. Then, the threshold voltage of the n-channel type and p-channel type insulated gate field effect transistors becomes lower due to the substrate bias effect as the substrate temperature rises. As the temperature increases, the threshold voltage decreases. As a result, the difference between the threshold voltages at the low temperature and the high temperature becomes larger than when the substrate is set to the same potential as the source. As a result, [V _G - (I _D) ^1/2] characteristic intersection of the curves, i.e., ZTC
Point in the direction of the gate voltage V _G is increased, moreover, move in a direction drain current I _D at that time is large (see FIG. 8). Adjustment of trimmable resistance after manufacturing
Thus, the position of the ZTC point can be controlled.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to specific embodiments. FIG. 1 shows the electrical characteristics of a n-channel MOSFET, which is an insulated gate field effect transistor according to the present invention, in which compensation is performed using a diode which is a temperature-dependent element in order to increase the gate voltage V _G (ZTC) at the ZTC point. FIG. 3 is a circuit diagram showing a configuration. A resistor 2 is connected between the positive power supply 4 and the four diodes 1 connected in series, and a resistor 3 is connected between the diode 1 and the ground 5 to form a bias circuit. A point between the diode 1 and the resistor 3 is defined as a point A. The temperature dependence of the potential at point A is determined by the number of diodes 1 connected in series. Generally, the temperature dependence of the forward voltage of one diode is about -2 mV / ° C. Therefore, the temperature dependency of the forward voltage of the four diodes 1 connected in series is about -8 mV / ° C (-
2mV / ° C x 4). Then, the potential at the point A at RT (room temperature) is set to a desired potential by the resistors 2 and 3. The potential at the point A is converted to an n-channel MOS
The substrate (or well) of the FET 10 is biased.
The number of the diodes 1 may be set so as to have a desired temperature coefficient.

The drain current _ID is expressed by the following equation (1) in the saturation region.
It is represented by _{I D = (1/2) · (} W / L) μC OX (V G -V T) 2 ......... (1) where, W: gate width, L: gate length, mu: carrier mobility, C _OX : capacitance of gate oxide film, V _G : gate voltage,
_VT : threshold voltage. The temperature dependence (approximate expression) of the carrier mobility μ is expressed by the following expression (2). μ (T) = μ (T _r ) (T / T _r ) ^{−k 1} (2) where T: temperature (K), T _r : room temperature, k ₁ : constant (1.5
~ 2.0 value). Temperature dependence of the threshold voltage V _T (approximate expression) is represented by the following formula (3). V _T (T) = V _T (T _r ) −k ₂ (T−T _r ) (3) where k _{2 is a} constant (a value of 0.5 to 4.0 mV / K).

[0009] decreased carrier mobility μ increasing temperature, shifts towards the lower threshold voltage V _T. Lowering of the carrier mobility μ acts in a direction to reduce the drain current I _D, reduction of the threshold voltage V _T acts in a direction to increase the drain current I _D in reverse. The point where these two actions cancel each other is the above-mentioned ZTC point. Therefore, by changing the temperature dependency of or threshold voltage V _T of carrier mobility mu, it is possible to move the ZTC point. Among them, it focused toward the threshold voltage V _T because it is difficult to control the carrier mobility mu. As shown in FIG. 8, when the rate of change of the threshold voltage V _T at high temperature with respect to the threshold voltage V _T at RT increases as b from a ZT
It is clear that the point C shifts from ZTC-a to ZTC-b, whichever is larger. A substrate bias effect in order to control the temperature dependence of the threshold voltage V _T. Figure 9 is an explanatory view showing the temperature dependency of the threshold voltage V _T with respect to the substrate potential V _BS of n-channel MOSFET. Threshold voltage V _T
Varies almost linearly with temperature. Threshold voltage change rate in this case is _{ΔV T / ΔT ≒ -2mV / ℃} . Here, the threshold voltage V _T is if changes as indicated by a dotted line, the threshold voltage variation rate becomes large as ΔV _T /ΔT≒-4.6mV/℃.
That is, by changing the substrate potential V _BS so as to increase with the temperature rise of the substrate, the change rate ΔV of the threshold voltage V _T is apparently changed.
_{What is} necessary is just to increase the absolute value of _T / ΔT. Figure 10 is with respect to the temperature change of the substrate - shows [V _G (I _D) ^1/2] characteristic curve. FIG. 10A shows a case where the substrate potential V _BS = 0 V and is constant. Further, FIG. 10 (b) in the case of varying the temperature of the substrate potential V _BS - a [V _G (I _D) ^1/2] characteristic curve. The substrate potential V _BS takes a value indicated by a dotted line in FIG. Here, since the substrate potential V _BS at the substrate temperature RT and -0.6V [V _G - (I _D) ^1/2] characteristic curve is shifted to the right by the substrate bias effect. Further increasing the temperature dependency of the threshold voltage V _T to increase the substrate potential V _BS with increasing temperature. Due to these two effects, ZT
Point C has shifted from 1.5V in FIG. 10 (a) to 2.5V in FIG. 10 (b). In order to realize the above effects, FIG.
The configuration of (b) may be used.

In FIG. 1, the potential at the point A (ie, the substrate potential V _BS ) increases as the temperature of the substrate increases. As a result, the ZTC point moves to the larger one. The gate voltage V _G (ZTC) at the ZTC point is added to the power supply voltage of the digital circuit.
Is used, it is possible to suppress a decrease in operation speed due to a temperature rise. That is, a potential having a positive temperature coefficient is created, and this is set to the substrate potential V
_BS . Thereby, the n-channel MOSFET 10
Can change the gate voltage V _G (ZTC) at the ZTC point in a direction to increase with the temperature change of the substrate.

FIGS. 2 and 3 show an n-channel MOSFET.
In order to change the gate voltage V _G (ZTC) at the 10 ZTC points, a temperature-dependent element TCR (Tempera
FIG. 3 is a circuit diagram showing an electrical configuration in a case where compensation is performed using resistances having different values of turecoefficient (resistivity). FIG.
As shown in (a), the resistor R ₁ (TC
The potential at point D, which is the connection point between R (small R) and the ground-side resistor R ₂ (large TCR), is defined as the substrate potential V _BS of the n-channel MOSFET 10. At this time, the potential at the point D has a positive temperature coefficient as in the above-described embodiment. A resistor R ₁
48 kΩ, 100 ppm / ° C (Si-Cr), resistance R ₂ is ₂ kΩ, 200
The temperature dependency of the potential at the point D at 0 ppm / ° C (diffusion resistance) is about 0.5 mV / ° C. Thereby, n channel M
The ZTC point in the OSFET 10 can be moved to a larger one. As shown in FIG. 2 (b), the positive power supply (5V)
The potential at point E, which is the connection point between the side resistor R ₃ (TCR small) and the resistor R ₄ (TCR large) on the negative power supply (−5 V) side, is defined as the substrate potential V _BS of the n-channel MOSFET 10. At this time, the potential at the point E has a positive temperature coefficient as in the above-described embodiment. In addition, the potential at point E can be lower than the source potential at RT. Consequently, - in [V _G (I _D) ^1/2] characteristic curve, the threshold voltage V _T at RT is larger than that in case of equal to the substrate potential and the source potential (V _BS = 0). Further, the substrate potential with increasing temperature so rises - large transitions in the negative direction as compared with the case [V _G (I _D) ^1/2] of the threshold voltage V _T in the characteristic curve of constant substrate potential V _BS. By the effect of both,
[V _G - (I _D) ^1/2] characteristic curve ZTC point is the intersection of varying the direction in which the gate voltage V _G is increased as compared with the case where the same substrate potential to the source potential. A resistor R ₃ 50k
When the resistance R ₄ is 2 kΩ and 2000 ppm / ° C., the temperature dependence of the potential at the point E is about 4 mV / ° C. As a result, the gate voltage V _G (ZTC) at the ZTC point of the n-channel MOSFET 10 can be shifted to the larger one. Further, as shown in FIG. 3, the power supply-side resistor R ₅
(TCR large) and a resistor R ₆ (T
The temperature coefficient of the potential at the point F, which is the connection point with the resistor R ₇ (small CR) and the resistor R ₇ (small TCR), is adjusted. The potential of this point F and the substrate potential V _BS of n-channel MOSFET 10. At this time, the potential at the point F has a positive temperature coefficient as in the above-described embodiment. Thus, the ZTC point of the n-channel MOSFET 10 is adjusted to a desired position.
As a result, the gate voltage V _G (ZTC) at the ZTC point of the n-channel MOSFET 10 can be shifted to the larger one. The resistor R ₅ 48kΩ, 2000ppm / ℃, the resistance R ₆ 1kΩ, 2000ppm / ℃, the resistance R ₇ 1kΩ, 100ppm
/ ° C. First, the resistance of the resistor R _6, R ₇ is previously set rather small. Then, to trim the resistor R _6, R _7, a resistor R ₆ and a resistor R ₇ is connected to the combined resistance in parallel 2k
Ω. At this time, the temperature dependence of the potential at the point F can be adjusted in the range of 0 to 0.5 mV / ° C. Further, FIG.
Is the potential at point F set by the circuit of FIG.
2 shows a case where the invention is applied to a CMOS operational amplifier.
As V _bias is ZTC point, resistors R _6, R ₇ are trimmed.

FIG. 5 shows an electric circuit in which the gate voltage V _G (ZTC) at the point ZTC of the p-channel MOSFET 20 which is an insulated gate type field effect transistor is compensated by a circuit using the diode 1 in order to move it to a larger one. FIG. 3 is a circuit diagram showing a configuration. Note that the same components as those in the above-described embodiment are denoted by the same reference numerals, and description thereof will be omitted. In the case of the p-channel MOSFET 20, the potential at the point C accompanying the rise in the temperature of the substrate, that is, the substrate potential V _BS , together with the temperature rise of the substrate based on the temperature dependence of the forward voltage of the four diodes 1 connected in series. What is necessary is just to change so that it may fall. That is, the potential at the point C is n
It will have a negative temperature coefficient opposite to that of the channel MOSFET 10. As a result, the gate voltage V _G (ZTC) at the point ZTC can be moved to the larger one.

FIGS. 6 and 7 show a p-channel MOSFET.
FIG. 13 is a circuit diagram showing an electrical configuration in the case where compensation is performed using different resistors of the TCR in order to change the gate voltage V _G (ZTC) at the 20 ZTC points. In addition, FIG.
(b) corresponds to FIGS. 2 (a) and (b), and FIG. 7 corresponds to FIG. In FIG. 6 (a), the resistor R ₈ (T
The potential at the connection point between the large CR and the ground-side resistor R ₉ (small TCR) is defined as the substrate potential V _BS of the p-channel MOSFET 20. At this time, the potential at the connection point has a negative temperature coefficient. Thereby, the p-channel MOSFET 2
The ZTC point at 0 can be moved to the larger one. In FIG. 6 (b), the resistor R ₁₀ (TC
The potential at the connection point between the large R and the resistor R ₁₁ (small TCR) on the negative power supply (−5 V) side is defined as the substrate potential V _BS of the p-channel MOSFET 20. At this time, the potential at the connection point has a negative temperature coefficient. Thereby, the p-channel MO
The ZTC point in the SFET 20 can be moved to a larger one. In FIG. 7, the potential at the connection point between the resistor R ₁₂ (large TCR) and the resistor R ₁₃ (large TCR) connected in parallel on the positive power supply side and the resistance R ₁₄ (large TCR) on the ground side is set to the potential of the p-channel MOSFET 20. and the substrate potential V _BS. At this time, the potential at the connection point has a negative temperature coefficient. Thereby, the ZTC point in the p-channel MOSFET 20 can be moved to a larger one.

[Brief description of the drawings]

FIG. 1 is an insulated gate field effect transistor, an n-channel MOSFET according to a specific embodiment of the present invention.
FIG. 5 is a circuit diagram showing an electrical configuration in the case where a diode is used to move the gate voltage V _G (ZTC) at the point ZTC to the larger one.

FIG. 2 is an electrical configuration of an n-channel MOSFET, which is an insulated gate field effect transistor according to the present invention, in the case where resistors having different TCRs are used to move a gate voltage V _G (ZTC) at a ZTC point to a larger one; FIG.

FIG. 3 is a circuit diagram showing an electrical configuration in a case where trimming and adjustment are performed using different resistors of a TCR to control the position of a ZTC point of an n-channel MOSFET which is an insulated gate field effect transistor according to the present invention. It is.

4 is a circuit diagram showing an electrical configuration when the embodiment of FIG. 3 is applied to the CMOS operational amplifier of FIG.

FIG. 5 shows an electrical configuration of a p-channel MOSFET which is an insulated gate field effect transistor according to the present invention when a diode is used to move a gate voltage V _G (ZTC) at a ZTC point to a larger one. It is a circuit diagram.

FIG. 6 is an electric configuration of a p-channel MOSFET, which is an insulated gate field effect transistor according to the present invention, in the case where resistors having different TCRs are used to move a gate voltage V _G (ZTC) at a ZTC point to a larger one; FIG.

FIG. 7 is a circuit diagram showing an electric configuration in a case where trimming and adjustment are performed using different resistors of a TCR in order to control a position of a ZTC point of a p-channel MOSFET which is an insulated gate field effect transistor according to the present invention. It is.

[8] - in [V _G (I _D) ^1/2] characteristic curve is an explanatory diagram showing the movement of the ZTC point by the magnitude of the rate of change of the threshold voltage V _T.

9 is an explanatory view showing the temperature dependence of the threshold voltage V _T with respect to the substrate potential V _BS of n-channel MOSFET.

[10] - it is a diagram showing a [V _G (I _D) ^1/2] characteristic curve.

FIG. 11 is a circuit diagram showing a basic form of a digital circuit including a CMOS inverter and a load capacitance.

FIG. 12 is a circuit diagram showing a configuration of a CMOS operational amplifier.

[Explanation of symbols]

1-diode (temperature-dependent element) 2,3-resistance
4-positive power supply 5-ground 6-negative power supply 10-n channel MOS
FET

Continuation of front page (56) References JP-A-52-32278 (JP, A) JP-A-61-160960 (JP, A) JP-A-59-168524 (JP, A) JP-A-61-53804 (JP) JP-A-63-242005 (JP, A) JP-A-60-128701 (JP, A) JP-B-45-19921 (JP, B1) (58) Fields investigated (Int. Cl. ⁷ , DB Name) H01L 29/78 H03F 1/30

Claims (2)

(57) [Claims] 1. A insulated gate field effect transistor, by adding a bias circuit using a plurality of trimmable resistors with different temperature dependence, by changing the substrate potential with temperature variations of the substrate, An insulated gate field effect transistor wherein the position of the ZTC point is shifted to the side where the gate voltage and the gate current are larger . 2. An insulated gate field effect transistor
And using multiple trimmable resistors with different temperature dependencies
Board temperature fluctuation by adding a bias circuit
It is possible to change the substrate potential with
In addition, Z is adjusted by adjusting the trimmable resistance after manufacturing.
Insulation characterized in that the position of the TC point can be controlled.
Gate type field effect transistor.