JP3186247B2 - DMA controller for communication - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication DMA controller in a communication control device.

[0002]

2. Description of the Related Art A conventional technique will be described with reference to FIGS. FIG. 2 shows a configuration of a peripheral circuit connected to the communication DMA controller. In FIG. 2, a CP 201 sets data necessary for the operation of the communication DMA controller 202 such as the number of DMA transfers and an operation mode command in the communication DMA controller 202.
U and 202 are communication DMA controllers for converting serial data into parallel data and transferring the data to a memory 203 without a CPU via direct memory access (hereinafter referred to as DMA). Memory, 111 is a data bus used for mutual data transfer, 112 is a clock signal line synchronized with serial data, and 113 is a serial data signal line to be received.

FIG. 4 shows a serial data receiving unit in the communication controller 202. In FIG. 4, 1
01 is a reception data buffer for storing reception data until transferred to the outside of the communication DMA controller 202;
Reference numeral 102 denotes a reception shift register which converts received serial data into parallel data in accordance with a clock signal of a reception clock line 112, and 401 denotes a CPU which indicates the number of data to be DMA-transferred.
DMA transfer number register set from 201, 111 is a data bus used for various data transfer, 112 is a clock signal line synchronized with serial data, 113 is a serial data signal line to be received, and 114 is a reception shift register 102. When the serial data is converted into parallel data, the reception data buffer 101 becomes active.
This is a received data write control signal line for writing data to.

When the received data is DMA-transferred to the memory 203, it is necessary to set the number of transfers to the communication DMA controller 202 prior to the DMA transfer. Usually, the number of transfers is 2 to 3 from the head data of the received serial data.
Conventionally, when the data indicating the number of transfers is received by the reception shift register 102,
201 once reads through the receive data buffer 101, writes to the DMA transfer number register 401,
A transfer had been started.

[0005]

When serial data is received and the data is DMA-transferred to the memory, the number of DMA transfers must be read by the CPU from the serial data and set by the CPU to the communication DMA controller. C
I was putting a burden on the PU.

An object of the present invention is to provide a communication DMA controller with a light load on the CPU.

[0007]

In order to achieve the above object, a communication DMA controller according to the present invention comprises a shift register for converting serial data into parallel data, and a data for storing parallel data output from the shift register. A buffer for storing a predetermined set value by the CPU; and a command register for storing a command for activating the command by the CPU, the number of times the shift register transfers parallel data to the data buffer. was counted by said count, DMA values of the parallel data when the count value matches with the set value as the DMA transfer count
This is to start the transfer.

[0008]

When the received serial data is DMA-transferred to the memory, the continuously transmitted data including the serial data is stored in a register for controlling the DMA transfer without the intervention of the CPU. This reduces the load on the CPU.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing a serial data receiving section inside a communication controller 202 according to a first embodiment of the present invention.

In FIG. 1, reference numeral 101 denotes a reception data buffer for storing reception data until the data is transferred to the outside of the communication DMA controller 202. 102 converts received serial data into parallel data in accordance with a clock signal of a reception clock line 112. Receive shift register, 103 is D
Not only can the number of data to be transferred by the MA be set from the CPU 201, but also when the write control signal 115 becomes active, the data from the reception shift register 102 is fetched.
This is the MA transfer number register.

Reference numeral 104 denotes a received data write control signal 11
4 becomes active and counts
A counter circuit which compares the value with the value set by 201 and activates the write control signal 115 when they coincide with each other. 105 is a command register for storing command data for determining the operation of the communication DMA controller 202 by setting from the CPU 201; This is a data bus used during data transfer.

Reference numeral 112 denotes a clock signal line synchronized with the serial data, 113 denotes a serial data line to be received, 1
Reference numeral 14 denotes a reception shift register 102 which is activated when the conversion from serial data to parallel data is completed, writes data into the reception data buffer 101, and performs DMA transfer.
This is a received data write control signal line that is output to the transfer control circuit and serves as a DMA transfer start signal.

Reference numeral 115 denotes a write control signal line for setting the data of the reception shift register 102 to the DMA transfer number register 103. Reference numeral 116 denotes a counter control signal which is activated by the data set in the command register 105 and starts the operation of the counter circuit 104. It is.

Assuming that the third data from the head of the serial data is the number of serial data transmitted continuously, the CPU 201 sets "3" in the counter circuit 104, and the counter control signal 116 is activated. Is written to the command register 103 so that

When the third serial data is received by the reception shift register 102 by the activation of the counter control signal 116, the reception data write control signal line 114 becomes active.

In the third active signal, the count result of the active signal is set to "3" in the counter circuit 104.
And the write control signal line 115 becomes active. By the activation of the write control signal line 115, the third serial data from the reception shift register 102 is stored in the DMA transfer number register 103, and the DMA transfer control circuit is activated.

(Embodiment 2) FIG. 3 is a block diagram showing Embodiment 2 of the present invention. In FIG. 3, the same symbols and the same names indicate that they have the same functions, and are different from the first embodiment in the following points. That is, in this embodiment, the data stored in the DMA transfer number register 103 is configured to be fetched from the reception data buffer 101.

[0019]

As described above, in the present invention,
A conventional communication DMA controller is provided with a counter circuit for outputting a signal for transferring and storing data in a shift register or a data buffer to a register for setting the number of times of DMA transfer, so that the CPU can convert serial data from the serial data. Since there is no need to read the number of data to be received and set the DMA transfer control register, DMA transfer can be started, so that the CPU load can be reduced by 5 to 10 instructions. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a peripheral circuit configuration of a communication DMA controller.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional example.

[Explanation of symbols]

 Reference Signs List 101 reception data buffer 102 reception shift register 103 DMA transfer number register 104 counter circuit 105 command register 111 data bus 112 reception clock signal line 113 reception serial data line 114 reception data write control signal line 115 write control signal line 116 counter control signal line 201 CPU 202 DMA controller for communication 203 Memory 401 DMA transfer number register

Claims (1)

(57) [Claims] A shift register for converting serial data into parallel data; a data buffer for storing parallel data output from the shift register; a counter for storing a predetermined set value by a CPU; A command register in which a command for activating the shift register is stored.The counter counts the number of times the shift register transfers parallel data to the data buffer, and the parallel when the count value matches the set value. DMA controller for communication, characterized by subjecting the activation of the DMA transfer values of data as DMA transfer count.