JP3190862B2 - Memory control system and printer device provided with this memory control system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control system and a printer having the memory control system.
In particular, the present invention relates to a multi-processor type memory control method including a master processor and a plurality of slave processors, and a printer device having the memory control method.

[0002]

2. Description of the Related Art In a printer device, editing of print data,
There are a printer control unit for drawing and a printer device unit for printing on paper. The printer control unit interfaces with the higher-level device, analyzes commands and print information sent from the higher-level device, and edits and edits according to the print information.
Perform drawing. After the drawing is completed, the printer device section performs printing.

Conventionally, in order to perform the above processing at high speed, a plurality of processors have been provided, and parallel processing has been performed to achieve high speed. In this case, when a plurality of processors execute the same process and a write operation to the memory of the master processor occurs, all the processors execute the write operation even though the contents to be written are the same.
Processing time is wasted due to bus contention and the like.

In a multiprocessor device using a plurality of processors, a control method of a common memory shared by a master processor and a slave processor is as follows.
It is disclosed in JP-A-2-143363. This publication describes a technique for avoiding bus contention by giving a priority rate for access to the slave processor when accessing a common memory between the slave processor and the master processor. The priority rates of the master processor and the slave processors are changed according to the operation state.

FIG. 4 is a block diagram shown in this publication. The multiprocessor device includes a master processor 7
2, a master memory 73 connected to the master processor 72 by a bus 75, a master memory control circuit 74 for controlling the master memory 73, a slave processor 76, a master processor 72, a slave processor 76, and a bus 75;
Common memory 77, common memory 77 connected by 79
, And an input / output device 80 under the control of the slave processor 76.

Next, the operation will be described. When there is an access request from the master processor 72, the master processor 72
Cannot access the common memory 77 unless the slave processor 76 is accessing and has no access right. As described above, the arbitration circuit 82 for giving the access right and arbitrating the access right determines the priority rate of the common memory access, thereby preventing the bus contention at the time of the memory access. In this way, bus contention between the master processor and the slave processors is prevented, and the processing time is reduced.

[0007]

In the above-mentioned conventional memory control method, the contention of buses can be prevented by setting a memory access priority rate in the processor. However, since memory access cannot be prevented, unnecessary memory access is not performed. Occurs, and the efficiency of the slave processor is not sufficiently improved.

An object of the present invention is to provide a memory control system which prevents a slave processor which has received a command from a master processor from making unnecessary access to a master memory, thereby improving the processing speed, and a memory control system which improves the processing speed. Printer device provided with the same.

[0009]

According to the present invention, there is provided a memory control method for a multiprocessor having a master processor and a plurality of slave processors, wherein the master processor is identical to the plurality of slave processors. When a command is issued, one of the plurality of slave processor units performs processing access to the master processor unit.

In the memory control method according to the present invention, the plurality of slave processors may include a master memory access information area for recording information on whether access to the master processor is possible.

[0011] In the memory control method according to the present invention, the master processor section may include, among the plurality of slave processor sections,
The access permission information to the master processor unit may be recorded in the master memory access permission information area of one slave processor unit.

In the memory control method according to the present invention, the master processor may record the access priority of the plurality of slave processors to the master processor in the master memory access availability information area.

In the memory control method according to the present invention, the master processor may perform recording in the master memory access information area when the master processor is initialized.

In the printer of the present invention, when the master processor issues the same command to the plurality of slave processors, one of the plurality of slave processors accesses the master processor for processing. It is characterized by performing.

[0015]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration. The printer device 1 includes a printer control unit 2
And a printer device unit 3. When the printer 1 receives a print request from the host device 10, the printer control unit 2 analyzes the command and print information from the host device 10, and performs editing and drawing according to the print information. After the drawing is completed, the printer control unit 2 sends data to the printer device unit 3 to perform printing.

The printer controller 2 includes a master processor 4, a slave processor 5a, a slave processor 5b, a slave processor 5c, and a slave processor 5d. The master processor unit 4 and the slave processor units 5a, 5b, 5c, 5d are connected by a common bus 6. The reason for including a plurality of slave processor units is to speed up the processing.

The master processor 4 has a master memory 41.
including.

The slave processor units 5a, 5b, 5c,
Reference numerals 5d denote a master memory access information area 51a, a master memory access information area 51b, a master memory access information area 51c, and a master memory information area for recording information as to whether access to the master memory 41 is permitted or not. Memory access availability information area 51d
Exists.

Next, the operation will be described. FIG. 2 is a flowchart showing the operation of the master processor unit 4.

When the printer device 1 is turned on (step S1), the master processor unit 4 initializes itself (step S2) and simultaneously operates the slave processor units 5a, 5b, 5c, and 5d mounted. The mounting is confirmed, and if the slave processor unit 5a is mounted, access is set to the master memory access availability information area 51a of the slave processor unit 5a.

If the slave processor 5a is not mounted, the mounting of the slave processor 5b is confirmed. If the slave processor 5b is mounted, the master memory access availability information area 51b of the slave processor 5b can be accessed. And set.

As described above, the implementation of the slave processor unit is checked (step S3), and only the master memory access availability information area of one of the slave processor units installed at the time of initialization processing is set to be accessible (step S4). .

Next, a process with reference to the set memory access availability information area will be described. FIG. 3 is a flowchart showing the operation of the slave processor units 5a, 5b, 5c and 5d.

When a common processing command is issued from the master processor unit 4 to the slave processor units 5a, 5b, 5c and 5d, the slave processor units 5a, 5b,
5c and 5d receive the command from the master processor unit 4 and execute the processing of the command (Step S11).
When an access to the master memory 41 occurs during the command processing (step S12), referring to the master memory access availability information area set in the initialization processing,
It is determined whether access to the master memory 41 is permitted or not (step S13).
Processor unit 1 that can access to
Only the sheet accesses and executes the processing (step S1).
4). In the present embodiment, since the slave processor unit 5a is accessible, the slave processor unit 5a is accessible.
a accesses the master memory 41.

Examples of the common processing command to be executed in step S11 include initialization processing of the slave processor sections, and loading of data that all slave processor sections should have at the time of editing. Data to be held by all slave processors during editing is, for example, font data.

As described above, the master processor unit 4
After receiving the command from the host device 10, the primary processing is performed in the master processor unit 4, and the secondary processing command is issued to the slave processor units 5a, 5b, 5c, and 5d.

When the master processor 4 issues a common processing command, that is, the same command to a plurality of slave processors, the processing steps and processing results in the slave processors are the same. Therefore, it is not necessary to report the processing result to the master processor unit 4 from a plurality of slave processor units.

The slave processor units 5a, 5b, 5c,
5d executes the command of the secondary processing,
Only one slave processor unit that has access to 1 reports the result of the secondary processing to the master processor unit 4. Since the command is a common processing command, the other slave processors do not access the master processor 4 to report the result of the secondary processing. Thereby, access to the master processor unit 4 can be reduced.

It should be noted that, in this embodiment,
Although an example in which all the slave processor units are used has been described, the number of slave processor units is not limited to four, and it is not necessary to cover all the slave processor units. For example, this memory control method may be applied to three slave processors out of four slave processors.

Also, an example has been described in which information on whether the master processor can be accessed is recorded in the master memory access availability information area of one slave processor. However, the priority is not limited to one, and priority is recorded. You may make it.

The apparatus to which the present invention is applied is not limited to a printer apparatus, but can be applied to a multiprocessor type information processing apparatus.

[0032]

As described above, according to the present invention, since only the slave processor unit which can access the master memory accesses the master processor unit, the memory access is reduced and the response time of the command processing is reduced. Has the effect of shortening

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a flowchart illustrating an operation of a master processor unit.

FIG. 3 is a flowchart illustrating an operation of a slave processor unit.

FIG. 4 is a block diagram showing a conventional technique.

[Explanation of symbols]

Reference Signs List 1 printer device 2 printer control unit 3 printer device unit 4 master processor unit 5a, 5b, 5c, 5d slave processor unit 6 common bus 10 host device 41 master memory 51a, 51b, 51c, 51d master memory access availability information area

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 3/12 G06F 15/177 672

Claims (6)

(57) [Claims] In a multiprocessor memory control system having a master processor and a plurality of slave processors, when the master processor issues the same command to the plurality of slave processors, the plurality of slave processors are controlled by the slave processor. Wherein one of the slave processor units accesses the master processor unit for processing. 2. The memory control method according to claim 1, wherein said plurality of slave processors have a master memory access information area for recording information on whether access to said master processor is possible. 3. The method according to claim 2, wherein the master processor records information indicating that the master processor can be accessed in the master memory access availability information area of one of the plurality of slave processors. 3. The memory control method according to claim 2, wherein: 4. The memory control according to claim 2, wherein the master processor records the access priority of the plurality of slave processors to the master processor in the master memory access availability information area. method. 5. The master processor unit according to claim 3, wherein recording in the master memory access information area is performed when the master processor unit is initialized.
Or the memory control method according to 4. 6. A printer device comprising the memory control system according to at least one of claims 1 to 5.