JP3191366B2 - Semiconductor device manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a BiCMOS device having a MOS transistor and a bipolar transistor formed on the same substrate.

[0002]

2. Description of the Related Art In recent years, with respect to semiconductor devices, a so-called BiCMOS device in which a memory cell is formed of a MOS transistor capable of high integration and a peripheral circuit is formed of a circuit including a bipolar transistor to achieve high speed has been receiving attention. ing.

What is important here is rationalization of the manufacturing process by integrating the bipolar process and the CMOS process, and simplification of the structure itself such as reduction of steps.

Here, a conventional method for manufacturing a BiCMOS device will be described with reference to FIGS. First, FIG.
As shown in FIG. 6, an N-type epitaxial layer 62 is formed on a P-type silicon substrate 61, for example. At this time, an N-type buried layer 64 is formed in a region 63 (hereinafter, referred to as a bipolar transistor formation region) where a bipolar transistor is to be formed. After that, selective oxidation is performed to selectively form a field insulating layer 65 on the surface of the epitaxial layer 62.

Next, as shown in FIG. 15B, after forming a polycrystalline silicon layer on the entire surface, patterning is performed
A gate electrode 67 of a polycrystalline silicon layer is formed in a region (hereinafter, simply referred to as a MOS transistor formation region) 66 where a transistor is formed.

Next, as shown in FIG. 16A, after a photoresist film 68 is formed on the bipolar transistor formation region 63, impurities for forming an LDD region, eg, BF, are formed in the MOS transistor formation region 66 using the gate electrode 67 as a mask. P ⁺ (low concentration) LDD by ion implantation of ₂ ⁺
An area 69 is formed.

Next, as shown in FIG. 16B, after removing the photoresist film 68 on the bipolar transistor formation region 63, the photoresist film 7 is formed on the portion where the MOS transistor formation region 66 and the collector extraction region are formed.
0 is formed. Then, impurities for forming a base region, for example, BF
₂ ⁺ a is ion-implanted to form a P-type base region 71.

Next, as shown in FIG. 17A, after removing the photoresist film 70, the MOS transistor forming region 66 and the bipolar transistor forming region 63 are again formed.
A photoresist film 72 is formed in a portion to be an intrinsic base region. Thereafter, using the photoresist film 72 as a mask, an impurity for forming a base extraction region, for example, BF ₂ ⁺ is ion-implanted into the bipolar transistor formation region 63 and a P-type (high concentration) is implanted into the bipolar transistor formation region 63.
Is formed.

Next, as shown in FIG. 17B, after removing the photoresist film 72, an insulating film made of, for example, SiO ₂ is formed on the entire surface by a CVD method or the like. After that, RIE
The entire surface is etched back by (reactive ion etching) to leave an insulating film on the side wall of the gate electrode 67. That is, the side wall 73 of the insulating film is formed on the gate electrode 67.

Next, as shown in FIG. 18A, after a photoresist film 74 is formed on the bipolar transistor formation region 63, source and drain regions are formed in the MOS transistor formation region 66 using the gate electrode 67 and the sidewall 73 as a mask. For example, BF ₂ ⁺ is ion-implanted to form a P-type (high concentration) source region 75 and a drain region 76 in the MOS transistor formation region 66.

Next, as shown in FIG. 18B, after removing the photoresist film 74, a photoresist film 77 is formed on the bipolar transistor formation region 63 and the MOS transistor formation region 66 except for a portion to be a collector extraction region. After the formation, an N-type impurity is ion-implanted into a portion (not shown) serving as a source region and a drain region of the N-channel MOS transistor and a portion serving as a collector take-out region. An N-type source region and a drain region (not shown) are formed, and an N-type collector extraction region 78 is formed in the bipolar transistor formation region 63.

Next, as shown in FIG. 19A, after removing the photoresist film 77, an insulating film 79 made of, for example, SiO ₂ is formed on the entire surface by a CVD method or the like. Thereafter, an opening 79 is formed at a position corresponding to the portion where the emitter region is formed.
After forming a, a polycrystalline silicon layer 80 is formed on the entire surface. Thereafter, impurities for forming an emitter region, for example, arsenic (As ⁺ ) are ion-implanted into the polycrystalline silicon layer 80.

Next, as shown in FIG. 19B, the polycrystalline silicon layer 80 is patterned to leave the polycrystalline silicon layer 80 only at the opening 79a. Then, for example, SiO ₂
After forming the interlayer insulating film 81 made of, heat treatment is performed.
At this time, the impurities in polycrystalline silicon layer 80 diffuse into intrinsic base region 71b to form N-type emitter region 82.

Then, as shown in FIG. 20, openings 83 are formed at locations corresponding to the source region 75, the drain region 76, the base extraction region 71a, the polycrystalline silicon layer 80, and the collector extraction region 78, respectively. An Al layer is formed, and then the Al layer is patterned to form a source electrode 84, a drain electrode 85, and a base electrode 8 of the Al layer.
6. An emitter electrode 87 and a collector electrode 88 are respectively formed to obtain a BiCMOS device.

[0015]

However, in the conventional BiCMOS device, when the sidewall 73 is formed on the gate electrode 67 in the process shown in FIG. 17B, the entire surface is etched back by RIE. There is a problem that the bipolar transistor formation region 63, particularly its operation region, is damaged by etching. To eliminate this damage, a high temperature (for example, 1
000 ° C. or higher), but usually MOS
In the transistor formation process, heat treatment at a high temperature cannot be performed due to abnormal diffusion of impurities.

Therefore, the damage caused by the etching that has entered the bipolar transistor formation region 63 cannot be effectively removed in a subsequent process, and the fabricated Bi
Among the CMOS devices, there is a problem that the characteristics of the bipolar transistor are inevitably deteriorated.

The present invention has been made in view of such a problem, and an object of the present invention is to provide an etching method for forming a bipolar transistor in a region where a bipolar transistor is to be formed at the time of an etching process for forming a sidewall on a gate electrode of a MOS transistor. It is an object of the present invention to provide a method for manufacturing a semiconductor device which does not cause damage due to the semiconductor device and does not cause deterioration of characteristics.

[0018]

According to the present invention, a MOS transistor forming region 3 and a bipolar transistor forming region 4 separated by an element separating region 2 formed on the same substrate 1 have a MOS transistor Tr and a bipolar transistor Q, respectively. In the method of manufacturing a semiconductor device in which
After the gate electrode 8 is formed on the S-transistor formation region 3, an impurity for forming an LDD region is selectively introduced into the MOS transistor formation region 3 using the gate electrode 8 as a mask.

Thereafter, a base region forming impurity is selectively introduced into the bipolar transistor forming region 4, and then a first insulating film 23 is formed on the entire surface. Thereafter, an etch back is performed to form a sidewall of the gate electrode 8 on the MOS transistor formation region 3 and the bipolar transistor formation region 4.
In the middle, the insulating film 23 is left on a portion to be the operation region 4a of the bipolar transistor. That is, the side wall 10 and the insulating film 22 are formed by the insulating film 23. Next, a second insulating film 37 is formed on the entire surface.

Thereafter, the gate electrode 8 and the insulating film (sidewall 10) remaining on the side wall of the gate electrode 8 in the MOS transistor forming region 3 and the insulating film 22 on the bipolar transistor forming region 4 are selectively used as masks in the source region. 5 and the drain region 6 and an impurity for forming the base extraction region 17a are introduced. After that, the first transistor remaining on the bipolar transistor formation region 4 is removed.
After the opening 24 is formed in a part of the second insulating films 22 and 37, the first semiconductor layer 21 is formed on the entire surface. Next, after introducing impurities for forming an emitter region into the bipolar transistor forming region 4 through the opening 24, the first semiconductor layer 21 is processed into a predetermined pattern.

Further, according to the present invention, the MOS transistor forming region 3 and the bipolar transistor forming region 4 which are separated by the device separating region 2 formed on the same substrate 1 have M
In a method of manufacturing a semiconductor device in which an OS transistor Tr and a bipolar transistor Q are formed, after a gate electrode 8 is formed on a MOS transistor formation region 3, a MOS transistor is formed.
Using the gate electrode 8 as a mask, an impurity for forming an LDD region is selectively introduced into the transistor formation region 3.

Then, after selectively introducing a base region forming impurity into the bipolar transistor forming region 4, an insulating film 23 is formed on the entire surface. After that, an opening 24 is formed in a part of the insulating film 23 on the bipolar transistor formation region 4, and a semiconductor film 21 serving as an emitter diffusion source is formed in a part including the opening 24. Next, the opening 24
A film 52 having a wider pattern covers the opening 24
After the formation, the etch back is performed to leave the insulating film 23 on the side wall of the gate electrode 8 on the MOS transistor forming region 3 and the portion where the semiconductor film 21 is formed in the bipolar transistor forming region 4. That is, the side wall 10 and the insulating film 22 are formed by the insulating film 23.

Thereafter, the gate electrode 8 and the insulating film (sidewall 10) remaining on the side wall of the gate electrode 8 in the MOS transistor forming region 3 and the insulating film 22 on the bipolar transistor forming region 4 are selectively used as masks in the source region. 5 and the drain region 6 and an impurity for forming the base extraction region 17a are introduced. Then half
Region formed by impurities diffused from conductive film 21
Impurities for forming base extraction region except 18
Are connected to the region 17a in which
2 electrode 25 to the impurity diffused from the semiconductor film 21.
Is formed so that the formed region 18 is located therebetween.
You.

[0024]

According to the first manufacturing method of the present invention, after the first insulating film 23 is formed on the entire surface, the insulating film 23 is left on the side wall of the gate electrode 8 and the side wall of the insulating film 23 is formed on the gate electrode 8. In the case where 10 is formed, for example, even if etching by RIE is performed on the entire surface, the insulating film 23 (insulating film 22) may be left at least on the bipolar transistor operating region 4a in the bipolar transistor forming region 4. it can. Therefore, the operation area 4
The damage of the bipolar transistor Q due to etching damage can be prevented by the insulating film 22 on the operation region 4a, and the deterioration of the characteristics of the bipolar transistor Q due to the etching damage can be prevented.

In this case, for example, after the insulating film 23 is formed on the entire surface, a photoresist film 36 is formed on the insulating film 23 in the operation region 4a in the bipolar transistor formation region 4 before performing the etch back. , It is possible to minimize the number of manufacturing steps.

The source region 5 and the drain region 6 and the base extraction are selectively performed using the gate electrode 8, the insulating film (sidewall 10) remaining on the side wall of the gate electrode 8 and the insulating film 22 on the operation region 4a as a mask. Area 1
Since the impurity for forming 7a is introduced, the manufacturing process can be simplified, and the increase in the number of manufacturing processes accompanying the formation of the photoresist film 36 can be offset.

When the first semiconductor layer 21 is etched into a predetermined pattern, the underlying second insulating film 37 serves as an etching stopper, and the source region 5 and the drain region 6 in the MOS transistor formation region 3 and the bipolar transistor formation region 4 prevents overetching of the base extraction region 17a and the collector extraction region.

Incidentally, the base region 17 of the bipolar transistor Q is composed of the base extraction region 17a and the intrinsic base region 17a.
b, the intrinsic base region 17b and M
By simultaneously forming the LDD region 9 of the OS transistor Tr, the manufacturing process can be further simplified.

According to the second manufacturing method of the present invention, similarly to the first manufacturing method, damage to the operation region 4a due to etching is avoided by the insulating film 22 on the operation region 4a. In addition, deterioration of the characteristics of the bipolar transistor Q due to etching damage can be prevented.

In the first manufacturing method, the operating region 4a
Since the semiconductor film 21 serving as an emitter diffusion source is patterned after the insulating film 22 is left thereon, the insulating film 22 must be formed to be relatively wide due to mask alignment accuracy. In the case of the second manufacturing method, the upper semiconductor layer 21 and the lower insulating film 22 can be patterned with the same width, so that the width of the insulating film 22 left on the operation region 4a can be reduced. The base extraction region 17a can be closer to the intrinsic base region 17b. As a result, the base resistance can be reduced, and the characteristics of the bipolar transistor can be further improved. Also, each of the base take-out areas 17a
The first and second electrodes 25 connected thereto are connected to the semiconductor film 21.
Region formed by impurities diffused from the
Region 18 between them, ie, the emitter region 1
8 so as to sandwich the opening 24.
Relative displacement with the wider film 52 (so-called mask
Even if misalignment occurs, the emitter is
The distance to the intrinsic base area immediately below the area 18 is smaller.
The base electrode functions as the actual base electrode,
Can lower the base resistance affecting
You.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows a BiCM according to the first embodiment.
FIG. 2 is a cross-sectional view illustrating a configuration of an OS device (hereinafter, simply referred to as a device).

This device has a P-channel MOS transistor T on the same silicon substrate 1 as shown in FIG.
r and an NPN transistor Q. These transistors Tr and Q are respectively formed in a MOS transistor formation region 3 and a bipolar transistor formation region 4 separated from each other by an element isolation region (field insulating layer) 2 formed by a selective oxidation (LOCOS) method or the like. .

The P-channel MOS transistor Tr is formed, for example, with a P-type (high-concentration) source region 5 and a drain region 6 formed in the formation region 3 and a gate insulating film 7 on the channel region. Gate electrode 8
It is composed of In particular, in this example, a P-type (low-concentration) LDD is used to prevent electric field concentration (short channel effect) at the drain end due to high integration of MOS transistors.
A region 9 is formed.

The LDD region 9 is formed under the insulating film remaining on the side wall of the gate electrode 8, that is, under the side wall 10. Incidentally, 11 is an interlayer insulating film, and 12 and 13 are Al
A source electrode and a drain electrode by a layer. Gate electrode 8 is formed of a tungsten polycide layer including upper tungsten silicide layer 14 and lower polycrystalline silicon layer 15.

On the other hand, the NPN transistor Q includes, for example, an N-type collector region (epitaxial layer 16) formed in the formation region 4, a P-type base region 17, and an N-type emitter region 18. . In particular, in this example, the base region 17 has a relatively large depth, and a base extraction region 17a formed in a substantially U-shape in a plane so as to surround the central emitter region, and a base extension region extending below the emitter region 18. It is composed of a shallow intrinsic base region 17b.

Below the collector region 16, an N-type buried layer 19 for reducing collector resistance and a collector extraction region 20 reaching the buried layer 19 from the surface are provided.
And Emitter region 18 is formed by impurity diffusion from impurity-doped polycrystalline silicon layer 21 formed thereon.

In the present embodiment, the insulating film 22 formed between the operation region 4a and the polysilicon layer 21 in the bipolar transistor formation region 4 and the gate electrode 8 on the MOS transistor formation region 3 are formed. The formed sidewalls 10 are formed of the same insulating film 23.

That is, after the insulating film 23 is formed on the entire surface, the side wall 10 of the gate electrode 8 and the insulating film 2 under the polycrystalline silicon layer 21 are etched by, for example, RIE.
2 are formed simultaneously. After an opening 24 is formed in the insulating film 22, an impurity-doped polycrystalline silicon layer 21 is formed.
To form an emitter region 18 by diffusing impurities.

In the figure, 25, 26 and 27 are:
2 shows a base electrode, an emitter electrode, and a collector electrode made of an Al layer. FIG. 2 shows a plan shape of the NPN transistor. From this figure, a polysilicon layer 21 is formed on the emitter region 18, and the polysilicon layer 21 is formed on the polysilicon layer 21.
The emitter electrode 26 is formed by an l-layer, and the base electrode 2 is formed so as to surround the emitter electrode 26.
5 has a substantially U-shape.

As described above, when the insulating film 23 is left on the side wall of the gate electrode 8 and the side wall 10 of the insulating film 23 is formed on the gate electrode 8, for example, etching by RIE is performed on the entire surface. Although the insulating film 23 on the bipolar transistor formation region 4 is entirely removed by etching, in the configuration of this example, the side wall 10 of the gate electrode 8 and the substrate 1 and the polysilicon layer on the bipolar transistor formation region 4 are formed. Since the same insulating film 23 is formed between the insulating film 22 and the insulating film 22 on the bipolar transistor forming region 4,
No. 2 is not etched by the RIE and remains until the final step. This means that damage to the bipolar transistor formation region 4 due to etching is avoided by the upper insulating film 22,
Deterioration of characteristics of the bipolar transistor due to etching damage can be prevented.

Next, two manufacturing methods for realizing the device according to the present embodiment (first embodiment and second embodiment).
Will be described with reference to the process charts of FIGS. The components corresponding to those in FIG. 1 are denoted by the same reference numerals.

FIGS. 3 to 9 are process diagrams showing a method for manufacturing a device according to the first embodiment. Hereinafter, the steps will be described in order.

First, as shown in FIG. 3A, after a thermal oxide film 31 is formed on a P-type silicon substrate 1, for example, an NPN
A window 31a is formed in a portion where the transistor is formed.
Thereafter, after forming an antimony film 32 on the entire surface, heat treatment is performed to remove N-type impurities (antimony) from the antimin film 32 through the window 31 a of the thermal oxide film 31.
To form an N-type impurity diffusion region 33.

Next, as shown in FIG. 3B, after exfoliating the antimony film 32 and the thermal oxide film 31 on the surface, the N-type epitaxial layer 16 is deposited on the silicon substrate 1. At this time, the N-type impurity diffusion region 33 below the region (hereinafter simply referred to as a bipolar transistor formation region) 4 in the epitaxial layer 16 where the NPN transistor is formed grows upward to become the N-type buried layer 19. . Epitaxial layer 16 has a thickness of about 1.5 μm. After that, the field insulating layer 2 is formed by selectively oxidizing the epitaxial layer 16.

Next, as shown in FIG. 3C, a polycrystalline silicon layer 15 having a thickness of about 100 nm and a
m tungsten silicide layers 14 are sequentially formed to form a tungsten polycide layer. At this time, impurities are introduced into the polycrystalline silicon layer 15 to have conductivity. Thereafter, the tungsten polycide layer is patterned to form a P-channel type MO in the epitaxial layer 16.
A gate electrode 8 of a tungsten polycide layer is formed on a region (hereinafter, simply referred to as a MOS transistor forming region) 3 where an S transistor is to be formed.

Next, as shown in FIG. 4A, after a photoresist film 34 is formed on the bipolar transistor formation region 4, impurities for forming an LDD region, for example, BF are formed in the MOS transistor formation region 3 using the gate electrode 8 as a mask.
₂ ⁺ ion implantation to P-type LDD regions 9 (low concentration) in a self-aligned manner. Although not shown in the drawing, an N-type LDD region is formed before and after that in a region where an N-channel MOS transistor is formed.

Next, as shown in FIG. 4B, after removing the photoresist film 34 on the bipolar transistor formation region 4, a photoresist film 35 is formed on the MOS transistor formation region 3 and on a portion to be a collector extraction region. I do. Thereafter, an impurity for forming a base region, for example, BF ₂ ⁺ is ion-implanted into a portion to be a base region to form a P region.
A mold base region 17 is formed.

In this example, the LDD region 9 and the base region 1
7 is formed in a separate process, but as shown in FIG. 10, the above impurities are simultaneously ion-implanted into the bipolar transistor formation region 4 and the MOS transistor formation region 3 except for a portion serving as a collector extraction region. A P-type base region (relatively shallow region) 17 may be formed in the bipolar transistor formation region 4 simultaneously with the LDD region 9.

Next, as shown in FIG. 5A, after removing the photoresist film 35, an insulating film 23 made of, for example, SiO ₂ and having a thickness of about 250 nm is formed on the entire surface by a CVD method or the like. Then, in the bipolar transistor formation region 4,
In particular, a photoresist film 36 is formed on the insulating film 23 in a portion to be the operation region 4a (except for a portion where a base extraction region is formed, the same applies hereinafter).

Next, as shown in FIG. 5B, the entire surface is etched back by RIE to leave the insulating film 23 on the side wall of the gate electrode 8. That is, the side wall 10 of the insulating film 23 is formed on the gate electrode 8. On the other hand, in the bipolar transistor formation region 4, the portion to be the operation region 4 a is prevented from being etched by RIE due to the presence of the photoresist film 36. Does not enter. At this time, the insulating film 23 remains on the operation region 4a, and the insulating film 22 shown in FIG. 1 is formed.

Subsequently, as shown in FIG.
After removing the photoresist film 36 on a, an SiO ₂ film 37 having a thickness of about 20 nm is formed on the entire surface by a CVD method.
This SiO ₂ film 37 will be used for the polycrystalline silicon layer 2 in a later step.
1 (see FIG. 1) is important in preventing over-etching of the substrate 1 when patterning.

Thereafter, a photoresist film 38 is formed on a portion serving as a collector extraction region and a portion (not shown) where an N-channel MOS transistor is formed, and then an insulating film on the gate electrode 8 and the sidewalls 10 and the operation region 4a is formed. Using the mask 22 as a mask, impurities for forming source / drain regions and a base extraction region, for example, BF ₂ ^+, are ion-implanted into the MOS transistor formation region 3 and the bipolar transistor formation region 4 to form a P-type (high concentration) in the MOS transistor formation region 3. The source region 5 and the drain region 6 are formed, and a P-type base extraction region 17a is formed in the bipolar transistor formation region 4.

Subsequently, as shown in FIG. 6B, after removing the photoresist film 38, the bipolar transistor forming region 4 and the M
A photoresist film 39 is formed on the OS transistor formation region 3.
Are formed, portions (not shown) serving as a source region and a drain region of the N-channel MOS transistor and P
N-type impurities are ion-implanted into a portion (not shown) serving as a base take-out region and a collector take-out region of an NP transistor, and N-type source and drain regions are formed in a portion serving as an N-channel MOS transistor, respectively. (Not shown), a base extraction region (not shown) is formed in a portion to be a PNP transistor, and an N-type collector extraction region 20 is formed in the bipolar transistor formation region 4.

Next, as shown in FIG. 7A, after removing the photoresist film 39, a photoresist film 40 having an opening 40a at a portion corresponding to the emitter region is formed. After that, the lower insulating films 37 and 22 are removed by etching through the openings 40 a of the photoresist film 40 to form the openings 24 reaching the bipolar transistor formation region 4.

Next, as shown in FIG. 7B, after removing the photoresist film 40, a polycrystalline silicon layer 21 having a thickness of about 150 nm is formed on the entire surface. Thereafter, an impurity for forming an emitter region, for example, arsenic (As ⁺ ) is ion-implanted into the polycrystalline silicon layer 21.

Next, as shown in FIG. 8A, after a photoresist film 41 is formed in the portion of the opening 24, the exposed polysilicon layer 21 is removed by etching so that the polysilicon layer 21 is formed in the portion of the opening 24. leave. When the polycrystalline silicon layer 21 is etched, the underlying SiO ₂ film 37 serves as an etching stopper, so that the source region 5 and the drain region 6 in the MOS transistor formation region 3 and the base extraction region 17 a and the collector extraction in the bipolar transistor formation region 4. Over-etching of a portion to be a region can be prevented.

Next, as shown in FIG. 8B, after removing the photoresist film 41 on the polycrystalline silicon layer 21, an interlayer insulating film 11 made of, for example, SiO ₂ is formed on the entire surface, and then heat treatment is performed. At this time, impurities in the polycrystalline silicon layer 21 diffuse into the intrinsic base region 17b to form an N-type emitter region 18.

Then, as shown in FIG. 9, openings 42 are formed at locations corresponding to the source region 5, the drain region 6, the base extraction region 17a, the polycrystalline silicon layer 21 and the collector extraction region 20, respectively. After forming an Al layer, the Al layer is patterned and the source electrode 12, the drain electrode 13, the base electrode 25,
The emitter electrode 26 and the collector electrode 27 are respectively formed to obtain the device according to the present example.

According to the manufacturing method of the first embodiment, after the insulating film 23 is formed on the entire surface, the side wall 10 of the insulating film 23 is formed on the gate electrode 8 while leaving the insulating film 23 on the side wall of the gate electrode 8. In this case, for example, even if etching by RIE is performed on the entire surface, the insulating film 23 (the insulating film 22) can be left in at least the bipolar transistor operation region 4a in the bipolar transistor formation region 4.

Therefore, the damage to the operation region 4a due to etching is avoided by the insulating film 22 on the operation region 4a, and the deterioration of the characteristics of the bipolar transistor Q due to the etching damage can be prevented.

In this case, for example, after the insulating film 23 is formed on the entire surface, a photoresist film 36 (see the step shown in FIG. 5A) is formed on the insulating film 23 in the bipolar transistor formation region 4 before performing the etch back. Since it is only necessary to form them, an increase in the number of manufacturing steps can be minimized.

Further, impurities for selectively forming the source region 5, the drain region 6 and the base extraction region 17a are selectively formed using the gate electrode 8, the side wall 10 of the gate electrode 8 and the insulating film 22 on the operation region as a mask. Since the introduction is performed, the manufacturing process can be simplified, and the increase in the number of manufacturing processes associated with the formation of the photoresist film 36 can be offset. Also, the central Emi
A base U-shaped base take-out area surrounding the
A region 17a is formed, and the emitter electrode 26 is
Since it is formed to be surrounded by the base electrode 25,
Even if the position of the emitter region 18 is shifted (that is,
8. Mask alignment for forming base extraction region 17a
Even if there is a deviation), make sure that the base electrode 25 and the intrinsic base
There is a short distance between the regions 17b, and the base resistance
Can be lowered, causing deterioration of high frequency characteristics
Nothing.

Incidentally, the base region 17 of the bipolar transistor Q is composed of the base extraction region 17 a and the intrinsic base region 17.
b, the intrinsic base region 17b and M
By simultaneously forming the LDD region 9 of the OS transistor Tr, the manufacturing process can be further simplified.

Next, a method of manufacturing the device according to the second embodiment will be described with reference to FIGS. In the second embodiment, the same steps are performed up to the step of forming the P-type base region 17 shown in the first embodiment (see FIG. 4B).
The description of these steps is omitted. Therefore,
In the manufacturing method of the second embodiment, the steps after the formation of the base region 17 will be sequentially described.

First, as shown in FIG. 11A, after removing the photoresist film 35 (see FIG. 4B), an insulating film 23 made of, for example, SiO ₂ and having a thickness of about 250 nm is formed on the entire surface by a CVD method or the like. Thereafter, a photoresist film 51 having an opening 51a at a portion corresponding to the emitter region is formed. After that, the lower insulating film 23 is removed by etching through the opening 51 a of the photoresist film 51 to form an opening 24 reaching the bipolar transistor formation region 4.

Next, as shown in FIG. 11B, after the photoresist film 51 is removed, a thickness of about 150 nm
Is formed. Thereafter, an impurity for forming an emitter region, for example, arsenic (As ⁺ ) is ion-implanted into the polycrystalline silicon layer 21.

Next, as shown in FIG. 12A, after a photoresist film 52 (for example, a resist film made of an ultraviolet curable resin) is formed in the opening 24, the exposed polycrystalline silicon layer 21 is formed by, for example, RIE. Remove by etching.
Subsequently, the lower exposed insulating film 23 is removed by etching by RIE. This continuous etching by RIE can be performed by changing the etching conditions (for example, gas components and the like) by sequence control. In this continuous etching,
The polycrystalline silicon layer 21 and the insulating film 23 having substantially the same width (FIG. 1)
Corresponds to the insulating film 22. Hereinafter, this insulating film 23 will be referred to as an insulating film 22) will remain on the portion to be the operation region 4a.

Thereafter, although not shown, the photoresist film 52 is altered and cured by a curing process using ultraviolet rays.

Next, as shown in FIG. 12B, a portion serving as a collector extraction region and an N channel type MO (not shown)
A photoresist film 5 is formed on the portion where the S transistor is formed.
3 is formed, and then the gate electrode 8 and the side wall 10 are formed.
And using the insulating film 22 on the operation region 4a as a mask,
Impurities for forming source / drain regions and a base extraction region, for example, BF ₂ ^+, are ion-implanted into the S transistor formation region 3 and the bipolar transistor formation region 4, and a P-type (high concentration) source region 5 is implanted into the MOS transistor formation region 3. And a drain region 6, and a P-type base extraction region 17a is formed in the bipolar transistor formation region 4. Since the photoresist film 52 on the polycrystalline silicon layer 21 has been cured by a curing process using ultraviolet light, it is not removed by the development of a photoresist film 53 formed later, or the like. This will remain (this method is generally called a double resist method).

Subsequently, as shown in FIG. 13A, after the photoresist films 52 and 53 are removed, a photoresist film is formed on the bipolar transistor formation region 4 and the MOS transistor formation region 3 except for a portion which becomes a collector extraction region. After the formation of the N-type MOS transistor, a portion serving as a source region and a drain region (not shown) of the N-channel MOS transistor, a portion serving as a base take-out region (not shown) of the PNP transistor, and a portion serving as a collector take-out region are N-type. Ion implantation of N-type MOS
An N-type source region and a drain region (not shown) are respectively formed in a portion to be a transistor, a base extraction region (not shown) is formed in a portion to be a PNP transistor, and an N-type region is formed in a bipolar transistor formation region 4. A mold collector removal area 20 is formed.

Next, as shown in FIG. 13B, after removing the photoresist film 54, an interlayer insulating film 11 made of, for example, SiO ₂ is formed on the entire surface, and then heat treatment is performed.
At this time, impurities in the polycrystalline silicon layer 21 diffuse into the intrinsic base region 17b to form an N-type emitter region 18.

Then, as shown in FIG. 14, openings 42 are formed at locations corresponding to the source region 5, the drain region 6, the base extraction region 17a, the polycrystalline silicon layer 21 and the collector extraction region 20, respectively. After forming an Al layer, the Al layer is patterned and the source electrode 12, the drain electrode 13, the base electrode 25,
The emitter electrode 26 and the collector electrode 27 are respectively formed to obtain the device according to the present example.

According to the manufacturing method of the second embodiment, similarly to the first embodiment, damage to the operation region 4a due to etching is avoided by the insulating film 22 on the operation region 4a. It is possible to prevent the characteristics of the bipolar transistor Q from deteriorating due to etching damage.

In the first embodiment, the operation area 4a
Since the polycrystalline silicon layer 21 serving as an emitter diffusion source is patterned after the insulating film 22 is left on the insulating film 22, it is necessary to form the insulating film 22 relatively wide due to mask alignment accuracy. In the case of the second manufacturing method, the upper polycrystalline silicon layer 21 and the lower insulating film 22 can be patterned with the same width. Therefore,
The width of the insulating film 22 remaining on the operation region 4a can be reduced, and the base extraction region 17a can be made closer to the intrinsic base region 17b. As a result, the base resistance can be reduced, and the bipolar transistor Q
Characteristics can be further improved. In addition, the first
As in the embodiment, the central emitter region 18 is
A flat U-shaped base extraction region 17a is formed.
The electrode 26 is surrounded by a base electrode 25 having a U-shape in plan view.
The emitter region 18 is misaligned.
However, the base resistance can be lowered,
Does not cause deterioration.

[0075]

According to the method of manufacturing a semiconductor device according to the present invention, in a BiCMOS, during etching processing for forming a sidewall on a gate electrode of a MOS transistor, damage to the bipolar transistor formation region due to etching may be caused. In addition, it is possible to prevent the characteristics from deteriorating due to the etching damage. In addition, it is possible to prevent the deterioration of the characteristics while minimizing the increase in the number of manufacturing steps. When patterning the semiconductor layer for forming the emitter region, over-etching of the source, drain, base extraction region, and collector extraction region can be prevented. Further, the base resistance affecting the high frequency characteristics can be suppressed low.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration of a BiCMOS device according to an embodiment.

FIG. 2 is a plan view showing the configuration of the NPN transistor according to the embodiment.

FIG. 3 is a process chart (1) showing a method for manufacturing a BiCMOS device according to the first embodiment.

FIG. 4 is a process diagram (part 2) illustrating the method for manufacturing the BiCMOS device according to the first embodiment.

FIG. 5 is a process diagram (part 3) illustrating the method for manufacturing the BiCMOS device according to the first embodiment.

FIG. 6 is a process diagram (part 4) illustrating the method for manufacturing the BiCMOS device according to the first embodiment.

FIG. 7 is a process view (5) showing the method for manufacturing the BiCMOS device according to the first embodiment.

FIG. 8 is a process view (part 6) illustrating the method for manufacturing the BiCMOS device according to the first embodiment.

FIG. 9 is a process chart (part 7) illustrating the method for manufacturing the BiCMOS device according to the first embodiment.

FIG. 10 is a process flow chart showing another example of forming a base region.

FIG. 11 is a process chart (1) showing a method for manufacturing a BiCMOS device according to the second embodiment.

FIG. 12 is a process chart (2) showing the method for manufacturing the BiCMOS device according to the second embodiment.

FIG. 13 is a process chart (3) showing a method for manufacturing a BiCMOS device according to the second embodiment.

FIG. 14 is a process view (part 4) showing the method for manufacturing the BiCMOS device according to the second embodiment.

FIG. 15 is a process chart (1) showing a method for manufacturing a BiCMOS device according to a conventional example.

FIG. 16 is a process diagram (part 2) illustrating a method for manufacturing a BiCMOS device according to a conventional example.

FIG. 17 is a process chart (3) showing a method for manufacturing a BiCMOS device according to a conventional example.

FIG. 18 is a process diagram (part 4) illustrating a method for manufacturing a BiCMOS device according to a conventional example.

FIG. 19 is a process view (5) showing a method for manufacturing a BiCMOS device according to a conventional example.

FIG. 20 is a process chart (part 6) illustrating the method for manufacturing the BiCMOS device according to the conventional example.

[Explanation of symbols]

 Tr P-channel type MOS transistor Q NPN transistor 1 Silicon substrate 2 Field insulating layer 3 MOS transistor forming region 4 Bipolar transistor forming region 5 Source region 6 Drain region 7 Gate insulating film 8 Gate electrode 9 LDD region 10 Side wall (insulating film 23) DESCRIPTION OF SYMBOLS 11 Interlayer insulating film 12 Source electrode 13 Drain electrode 14 Tungsten silicide layer 15 Polycrystalline silicon layer 16 Epitaxial layer 17 Base region 17a Base extraction region 17b Intrinsic base region 18 Emitter region 19 Buried layer 20 Collector extraction region 21 Polycrystalline silicon layer 22 Insulation Film (insulating film 23) 25 Base electrode 26 Emitter electrode 27 Collector electrode 36, 52 Photoresist film

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/06 H01L 21/2849

Claims (8)

(57) [Claims] 1. A method of manufacturing a semiconductor device in which a MOS transistor and a bipolar transistor are formed in a MOS transistor formation region and a bipolar transistor formation region separated by an element isolation region formed on the same substrate, respectively. Forming a gate electrode on the region; selectively introducing an impurity for forming an LDD region into the MOS transistor forming region using the gate electrode as a mask; and selectively forming a base region in the bipolar transistor forming region. A step of introducing impurities, and after forming a first insulating film on the entire surface, etch back,
Leaving the insulating film on the side wall of the gate electrode on the MOS transistor forming region and on the portion of the bipolar transistor forming region which will be the operation region of the bipolar transistor; and forming a second insulating film on the entire surface Source and drain regions selectively using the gate electrode in the MOS transistor formation region, the first insulating film remaining on sidewalls of the gate electrode, and the first insulating film on the bipolar transistor formation region as a mask; A step of introducing an impurity for forming a base extraction region; and forming an opening in a part of the first and second insulating films remaining on the bipolar transistor formation region, and then forming a first semiconductor on the entire surface. Forming a layer, and forming an emitter region in the bipolar transistor formation region through the opening. A method for manufacturing a semiconductor device, comprising: a step of introducing an impurity; and a step of processing the first semiconductor layer into a predetermined pattern. 2. After the first insulating film is formed on the entire surface, the first insulating film is etched back so that the first insulating film is formed on a side wall of the gate electrode on the MOS transistor formation region and a portion to be an operation region of the bipolar transistor. In the step of leaving the first insulating film , after forming the first insulating film on the entire surface, a photoresist film is formed on the first insulating film in a portion to be the operation region in the bipolar transistor formation region. 2. The method for manufacturing a semiconductor device according to claim 1, wherein said etch back is performed thereafter. 3. In the step of introducing an impurity for forming an emitter region through the opening, a step of introducing an impurity into the entire surface including the opening is performed .
After forming a polycrystalline silicon layer as one semiconductor layer, an impurity for forming an emitter region is introduced into the polycrystalline silicon layer, and thereafter, the polycrystalline silicon layer is patterned and left only in the opening portion. , Heat treatment,
3. The method of manufacturing a semiconductor device according to claim 1, wherein impurities for forming an emitter region are diffused from the remaining polycrystalline silicon layer to the bipolar transistor formation region through the opening. 4. A method of manufacturing a semiconductor device in which a MOS transistor and a bipolar transistor are formed in a MOS transistor formation region and a bipolar transistor formation region separated by an element isolation region formed on the same substrate, respectively. Forming a gate electrode on the region; selectively introducing an impurity for forming an LDD region into the MOS transistor forming region using the gate electrode as a mask; and selectively forming a base region in the bipolar transistor forming region. Introducing an impurity, forming an insulating film on the entire surface, forming an opening in a part of the insulating film on the bipolar transistor forming region, and forming a semiconductor film serving as an emitter diffusion source in a portion including the opening. Forming a pattern and a pattern wider than the opening Is formed so as to cover the opening, and then etched back to form a film having the M
Leaving the insulating film in the portion where the semiconductor film is formed in the side wall of the gate electrode on the OS transistor formation region and the bipolar transistor formation region; and forming the gate electrode and the side wall of the gate electrode on the MOS transistor formation region Selectively introducing impurities for forming source, drain and base extraction regions using the insulating film remaining on the substrate and the insulating film on the bipolar transistor formation region as a mask, and diffusing from the semiconductor film. Except for the region formed by the impurity, the first and second electrodes connected to the region into which the impurity for forming the base extraction region is introduced are connected to the region formed by the impurity diffused from the semiconductor film. Forming a semiconductor device between them. . 5. An etching process is performed on the entire surface from the step of forming a semiconductor film serving as an emitter diffusion source in a portion including the opening, and then an impurity for selectively forming a source / drain region and a base extraction region is removed. In a series of steps up to the introduction step, after forming the semiconductor film on the entire surface, a photoresist film as a film having a pattern wider than the opening is formed on a portion to be an operation region of the bipolar transistor. After that, after removing the exposed semiconductor film and leaving the semiconductor film at the opening, the entire surface is etched back, and the insulating film is formed on the side wall of the gate electrode and under the photoresist film. The source and the drain are selectively left using the gate electrode, the insulating film remaining on the side wall of the gate electrode, and the photoresist film as a mask. Preparation of a semiconductor device according to claim 4, wherein introducing the impurity for forming the region as well as the base take-out region. 6. The bipolar transistor according to claim 1, wherein the base region of the bipolar transistor comprises a base extraction region and an intrinsic base region, and the intrinsic base region and the LDD region of the MOS transistor are formed simultaneously. Any one of the semiconductor device manufacturing methods. 7. The method according to claim 1, wherein said MOS transistor is a P-channel type MOS transistor, and said bipolar transistor is an NPN transistor. 8. The MOS transistor according to claim 1, wherein said gate electrode is formed of a tungsten polycide layer comprising an upper tungsten silicide layer and a lower polycrystalline silicon layer. Manufacturing method of semiconductor device.