JP3192266B2 - Amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog processing section of an image reading apparatus such as a scanner, a copying machine, a facsimile, etc., which amplifies an input voltage obtained based on an image and outputs the voltage in a range smaller than a predetermined voltage. The present invention relates to an amplifier circuit for obtaining a voltage.

[0002]

2. Description of the Related Art An image reading apparatus such as a scanner, a copying machine and a facsimile will be described below with reference to the drawings.
FIG. 4 shows a schematic diagram thereof, and FIG. 5 shows waveforms of the analog voltages VA, VB, VC and the output voltages WA, WB, WC when the gain of the amplifying unit 6 is set to 3. FIG. 4 (a)
In the sensor fixing jig 1, the longitudinal direction 1
A number of sensors 2 are fixed in a row. On the upper surface of the sheet 3, the area between the lines P0 and P1 is uniformly painted "white" at all places.

[0003] In an area between the lines P1 and P2, "gray" becomes darker as the line P1 approaches the line P2.
Painted on. The line P2 is painted “almost black”. In the region between the lines P2 and P3, the line P2
It is painted in “gray”, which becomes whitish as it approaches P3 from 2. The line P3 is painted "white". In the region between the lines P3 and P4, the lines P3 to P4
It is painted in "gray", which becomes darker as it approaches.
The line P4 is painted "black".

The sheet 3 is placed so that the lines P0 to P4 are parallel to the longitudinal direction of the sensor fixing jig 1, and is moved at a constant speed below the sensor 2 from the line P0 in the direction of arrow 5. As shown in FIG. 5, the times at which the lines P0, P1, P2, P3, and P4 are detected by the sensor 2 are defined as T0, T1, T2, T3, and T4, respectively. The sensor 2 senses light emitted from the light source 4 and reflected by the sheet 3, and at this time, the sensor 2 outputs an analog voltage according to the amount of light received.

FIG. 4B shows the arrangement of the sensors 2 viewed from the front of the arrow 5. In FIG. 4B, the sensor 2A is located at a position where the optical path of light emitted from the light source 4 and reflected by the sheet 3 until it is received is the shortest distance, and the sensor 2B is located at a position where the optical path is further increased. The sensor 2C is located at a position where the optical path is the longest distance.

At this time, since the analog voltages VA, VB, and VC output from the sensors 2A, 2B, and 2C are weak, respectively, the amplifier circuits AMPA, AMPB, and A of the normal amplifier 6 are used.
The output voltages WA, WB, W amplified by the MPC, respectively.
C respectively. As shown in FIG.
Since the area of the line P0 to P1 sensed by each of the sensors 2A, 2B, and 2C is “white” in the period from T1 to T1, the analog voltages VA, VB, and VC output from the respective areas are represented by graphs g1, g2, and g3, respectively. The voltage values at the “High” level are 0.5 V, 0.4 V, and 0.3 V. The different values are due to the amount of light received and the sensitivity of each sensor 2.

As shown in graphs g1, g2 and g3, the time T
At 1 to T2, T2 to T3, and T3 to T4, the values of the analog voltages VA, VB, and VC change according to the change in the amount of received light. :
0.4V: 0.3V = 5: 4: 3. Graphs g4, g5, and g6 show output voltages WA, WB, and W, respectively.
C, which is obtained by simply multiplying the graphs g1, g2, and g3 by the value 3 of the gain G. In this case, the reference value for recognizing "white" or "black" is not determined, and the subsequent image reading is performed. Processing becomes impossible.

[0008]

As described above, since the analog voltage values VA, VB, and VC output from the sensors are different from each other, if all the signals are amplified equally by the amplifying unit 6, it is determined as "white" or "black". Can not. Even with a voice listening device, the distance between the sound source and the microphone, the sound level of the sound source,
The sound transmitted to the microphone varies depending on various conditions such as the concentration of air that mediates the transmission of sound, and even if all the audio signals output from the microphone are simply amplified with equal gain, it is large for each sound source. It is not possible to distinguish whether it is emitting a sound or a small sound.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide an amplifier circuit capable of selecting a maximum amplification factor that does not exceed a fixed voltage of an analog voltage.

[0010]

In order to achieve the above object, an amplifier circuit according to the present invention is used in an image reading apparatus that reads an image using a plurality of sensors that output a detection signal having an analog value corresponding to a detection amount. in the amplifier circuit, an amplifier means for obtaining an output signal by amplifying the detection signal, a pulse generating means for said output signal to generate a pulse greater period than the predetermined voltage, the clock pulse enable signal Ka
A signal generating means for generating a count end signal;
Signal and enable signal and count end signal.
And a pulse output from the logic circuit.
Clock pulses during the specified period, and the count value
Counting means for outputting a switching signal according to
A plurality of switches are appropriately turned off in response to a signal, and the amplification is performed.
While Ru is provided a gain switching means for switching the gain of the means to a small value, to each of said sensor, said signal generating means,
A switching signal for turning on the switch from the counting means;
During the period when no signal is output, the voltage value of "0"
Signal to generate a count
For a period set based on the number of switches
Configured to generate an enable signal with a value
It is.

[0011]

Therefore, according to the present invention, a pulse is output from a logic circuit.
Means for counting clock pulses during the period when
Counts and outputs a switching signal according to the count value
On the other hand, in response to the switching signal,
Switch off as necessary to reduce the gain of the amplification means to a small value.
Switching can reduce the value of the output signal. Soshi
When the output signal falls below a predetermined voltage,
A switching signal to turn on the switch is output from the
Set when missing or based on number of switches
After the period, no pulse is output from the logic circuit
That is, the gain of the amplifying means is determined.

[0012]

FIG. 1 is a circuit diagram of an amplifier circuit AMP embodying the present invention, and its configuration will be described. This amplifier circuit AMP is used for the amplifier 6, and the output of each sensor 2 shown in FIG. 5 is applied to the terminal 7 as an analog voltage VI and amplified to obtain an output voltage VO from the terminal 12. The amplifier circuit shown in FIG. AMPA,
It is assumed that AMPB and AMPC all have the same circuit configuration as the amplifier circuit AMP in FIG. In FIG. 1, the terminal 7 is connected to the non-inverting terminal + of the operational amplifier 14. The output terminal of the operational amplifier 14 is connected to the non-inverting terminal + of the comparator 13, the terminal 12, and one end of the resistor 26. The terminal 8 is connected to the inverting terminal-of the comparator 13. The output terminal of the comparator 13 is connected to the input terminal A of the AND circuit 15. The terminal 9 is connected to the input terminal A of the AND circuit 15. The output terminal -CR of the counter 16 is connected to the input terminal c of the AND circuit 15. Connect the terminal 10 to the input terminal CL of the counter 16
Connect to R. Connect terminal 11 to input terminal CK of counter 16
Connect to The output terminal of the AND circuit 15 is connected to the counter 16
To the input terminal EN.

In the counter 16, output terminals -Q0,
-Q1, -Q2, and -Q3 are connected to switches 22, 2
3, 24 and 25, respectively. One end of each of the resistors 17, 18, 19, 20, 21 is grounded. The other end of each of the resistors 18, 19, 20, 21 is connected to a terminal of each of the switches 22, 23, 24, 25. The inverting terminal-of the operational amplifier 14 is connected to the other end of the resistor 17, the terminals of the switches 22, 23, 24, 25 and the other end of the resistor 26. Note that the resistors 17, 18, 1
9, 20, 21 and 26 are represented by RS and R, respectively.
1, R2, R3, R4, RM, and resistors 17, 18, 1
Let R be the combined resistance value of 9, 20, and 21. The switches 22, 23, 24, and 25 have switching terminals S1, S2, S3, and S4 that have switching signals S1, S2, S3, and S4 provided from output terminals -Q0, -Q1, -Q2, and -Q3 of the counter 16 at "1". ”And turned off when it is“ 0 ”.

The terminal 7 is supplied with an analog voltage VI from the sensor 2 (FIG. 5). As is well known, operational amplifier 1
4 forms a positive-phase amplifier, and its gain G is G =
(1 + RM / R).
Amplify analog voltage VI applied to output voltage VO
Is supplied to the terminal 12. Therefore, the following equation (1) holds. VO = (1 + RM / R) VI (1)

The inverting terminal of the comparator 13 has a terminal 8
Is supplied with a constant voltage VMAX from the comparator 1
3, when the output voltage VO is larger than the constant voltage VMAX, the value of the signal CMP is set to "1", and the output voltage VO is set to the constant voltage VMA.
If it is smaller than X, the value of the signal CMP is set to “0”, and this voltage CMP is given to the AND circuit 15. Here, the value of the constant voltage VMAX is set to 0.80V.

Next, FIG. 2 shows a time chart when the analog voltage VC output from the sensor 2C is amplified by the amplifier circuit AMP embodying the present invention. The counter value of the counter 16 and the switching signals S1, S2, S3, The operation of the amplifier circuit will be described with reference to FIG. 3 showing a table of the relationship of S4 and the combined resistance value R and gain G at that time.

In order to change the amplification factor by a constant value, each resistance value RS, R is adjusted so that the relationship of the following equation (2) is satisfied.
1, R2, R3, and R4 are set. For simplicity, RS = 16 KΩ, R1 = 8 KΩ, and R2 = 4K
Ω, R3 = 2 KΩ, R4 = 1 KΩ, and RM = 1 KΩ. RS = R1 × 2 = R2 × 4 = R3 × 8 = R4 × 16 (2)

For example, as shown in FIG.
Is 0 (= 0000 (2)), the switching signal S
Since the values of 1, S2, S3, and S4 are all “1”,
The switches 22, 23, 24, and 25 are all turned on, and at this time, the value of the combined resistance R becomes the lowest 516Ω, and the value of the gain G becomes 2.94.

Even if the count of the counter 16 increases from 1 to 15, the same applies to FIGS.
(E), (f), (g), (h), (i), (j),
As shown in (k), (l), (m), (n), (o), and (p), the output terminals -Q0, -Q
Switching signals S1, S2, S3, S from -Q2, -Q3
4 in 16 combinations, switches 22, 23, 24, 2
Give 5 Switches 22, 23, 24, and 25 respectively include switching signals S1, S2, S
3, ON when the value of S4 is "1" and OFF when it is "0". As a result, the combined resistance value R also increases stepwise as shown in FIG. 3 for each count and changes among 16 values. As a result, the gain G gradually decreases in 16 values based on the equation (1).

As shown in FIG. 2 (f), the terminal 9 is connected to the terminal 9 for a fixed period of time 16 times or more the period τ of the clock CK (at time TE
1 to TE2), an enable signal E having a voltage value of “1”
Is supplied to the AND circuit 15. The output terminal -CR of the counter 16 has a value of "1" if any one of the switching signals S1 to S4 is "1" (FIGS. 3A to 3O) as shown in FIG. When the switching signals S1 to S4 all become "0" (FIG. 3 (p)), the count end signal S5 which switches to the value "0" is supplied to the AND circuit 15. The terminal 11 supplies the clock CK shown in FIG. 2E to the input terminal CK of the counter 16.

The AND circuit 15 calculates the logical product of the signal CMP, the enable signal E, and the count end signal S5.
The signal S6 shown in (g) is generated and given to the input terminal EN of the counter 16.

The counter 16 is connected from the terminal 10 to the input terminal C.
The signal is first cleared when the clear signal C shown in FIG. 2 (h) applied to the LR rises (time t1 in FIG. 2). The counter 16 counts the number of rises of the clock CK during the pulse period of the signal S6 from 0 to 15 (0000 (2) to 1111 (2).
), But the output terminals -Q0, -Q1,-
The switching signals S1, S2, S3, and S4 that are values obtained by inverting the 1's place, the 2's place, the 4's place, and the 8's place in the case where the count number is written in binary from Q2 and -Q3, respectively. 2 (i), (j), (k), and (l).

When the sensor 2 (FIG. 4) senses a constant amount of light reflected over the "white" area (lines P0 to P1), the value of the analog signal VI does not change over time. It has a constant value. In addition, this value is the highest value among possible values because there is no brightness brighter than “white”. The analog signal VC (= 0.3) of FIG.
V) in the initial state (FIG. 3).
Since the value of the gain G in (a)) is 2.94, the value of the output voltage VO is 0.882 V as shown in FIG. 2 (a), which is given to the non-inverting terminal + of the comparator 13. At this time (time t1 to t2), the output voltage VO (= 0.882)
Since the value of V) is larger than the constant voltage VMAX (= 0.80 V), the signal CMP keeps the value of "1" as shown in FIG.

At time TE1, the enable signal E of FIG. 2 (f) rises. At this time, the signal S6 which is the logical product of the enable signal E and the signal CMP also rises as shown in FIG. 2 (g). Thereafter, the time t2 at which the clock CK rises is within the pulse period of the signal S6, so that the counter 16 counts and counts from 0 to 1 (= 0001
(2)), the switching signals S4, S3, S2, S1
(S4, S3, S2, S1) becomes (1, 1, 1, 0) as shown in FIG. Therefore, switch 2
The switches 2, 23 and 24 are turned on, the switch 25 is turned off, and the value of the combined resistance R becomes 552Ω. Accordingly, from equation (1), the gain G is 2.81, and the value of the output voltage VO is
It converges to 0.843V as shown in (a).

From time t2 to time t3, the value of the output voltage VO (= 0.843 V) is changed to the constant voltage VMAX (= 0.
80V), the signal CMP is applied as shown in FIG.
Is “1”. Accordingly, since the time t3 at which the clock CK rises in FIG. 2E is within the pulse period of the signal S6, the counter 16 counts and the count number increases from 1 to 2 (= 0010 (2)), and thus the switching signal S
4, the values of S3, S2, and S1 (S4, S3, S2, S1)
Becomes (1, 1, 0, 1) as shown in FIG.
Therefore, the switches 22, 23, and 25 are turned on and the switch 24 is turned off, and the value of the combined resistance R becomes 593Ω. Therefore, from equation (1), the gain G is 2.69, and the value of the output voltage VO converges to 0.807 V as shown in FIG.

From the time t3 to the time t4, the value of the output voltage VO (= 0.807 V) is changed to the constant voltage VMAX (= 0.
80V), the signal CMP is applied as shown in FIG.
Is “1”. Accordingly, since the time t4 at which the clock CK rises in FIG. 2E is within the pulse period of the signal S6, the counter 16 counts and the count number increases from 2 to 3 (= 0011 (2)).
4, the values of S3, S2, and S1 (S4, S3, S2, S1)
Becomes (1, 1, 0, 0) as shown in FIG.
Therefore, the switches 22 and 23 are turned on and the switches 24 and 23 are turned on.
25 turns off and the value of the combined resistance R becomes 640Ω. Therefore, from equation (1), the gain G is 2.56, and the value of the output voltage VO converges to 0.768 V as shown in FIG.

At this time, the value of the output voltage VO is
Since it becomes smaller than MAX (= 0.80 V), the value of the signal CMP becomes "0" and the signal S6 falls, and thereafter the counter 16 stops counting. Therefore, since the count number is kept at 3 and does not change, the value of the gain G is determined to be 2.56. At time TE2, FIG.
Signal E6 falls, and the signal S6 is subsequently stopped regardless of the value of the signal CMP, so that the count operation of the counter 16 ends.

FIGS. 7 and 8 are time charts when the amplifiers AMPA and AMPB amplify the analog voltages VA and VB output from the sensors 2A and 2B. Also in this case, in order to operate in the same manner as in the case of the amplifier AMPC described above, the value of the constant voltage VMAX is set to 0.80 V as shown in FIGS. 7B and 8B. FIGS. 7C and 8C are graphs of analog voltages VA and VB, respectively. FIGS. 7A and 8A are output voltages WA and WB, respectively.
It is a graph of. Thus, in FIG.
The MPA counter 16 counts until the count number reaches 11, and the values of the switching signals S4, S3, S2, S1 (S4,
S3, S2, S1) are determined to be (0, 1, 0, 0), and the value of the gain G is fixed at 1.56 as shown in FIG. In FIG. 8, the counter 16 of the amplifier circuit AMPB is used.
Counts until the count number reaches 9, and the switching signal S
4, the values of S3, S2, S1 (S4, S3, S2, S1)
Is fixed at (0, 1, 1, 0), and the value of the gain G is fixed at 1.81 as shown in (j) of FIG.

As shown in FIGS.
AMPB, the analog voltage VA by the amplifier AMPC,
When amplifying VB and VC, the maximum number of counts is 15
The gain G has been determined before. However, the input voltage V
When I originally exceeds the constant voltage VMAX (= 0.80 V), the output is obtained because the gain G is 1.06 (FIG. 3 (p)) even when the count number becomes 15 (time TE2). Since the voltage VO does not become lower than the fixed voltage VMAX (= 0.80 V), the signal CMP shown in FIG. 2D does not fall and the counter 16 continues the counting operation as it is.

However, when the count number becomes 15 as described above, the value of the count end signal S5 provided to the AND circuit 15 from the output terminal -CR switches from "1" to "0". Therefore, the value of the signal S6 is also forcibly set to “0”.
And the switching of the switches 22 to 25 by the counting operation of the counter 16 ends. Further time T
At E2, the enable signal E falls, and the gain G is completely determined since the count number is not changed thereafter.

Next, based on FIGS. 2, 7 and 8, FIG.
FIG. 6 is a graph showing input / output voltages when the amplifier circuits AMPA, AMPB, and AMPC having the circuit configuration of FIG.
And will be described. Analog voltages VA, VB, and VC shown in graphs g1, g2, and g3 are amplified by dedicated amplifier circuits AMPA, AMPB, and AMPC as input voltage VI, and output voltages WA and W output as output voltage VO.
B and WC are obtained by simply multiplying the gain G = 2.97 by a graph g.
7, g8, and g9, and the initial values are 1.470 V, 1.176 V, and 0.882 V, respectively. Since these values all exceed the voltage VMAX (= 0.8 V), as described above, during the period in which the value of the enable signal E is "1" (time TE1 to TE2).
Each converges near MAX (= 0.8 V).

At this time, the amplifier circuit AMPA corresponding to the sensor 2A is in the state shown in FIG. 3 (l), and the value of the gain G is 1.
56 (the maximum value below 0.8 V / 0.5 V)
The output voltage WA becomes 0.780V. The amplifier circuit AMPB corresponding to the sensor 2B enters the state shown in FIG. 3 (i), the value of the gain G is determined to be 1.94 (the maximum value below 0.8V / 0.4V), and the output voltage WB is 0.776V. become. The amplifier circuit AMPC corresponding to the sensor 2C is in the state shown in FIG. 3D, and the value of the gain G is 2.56 (0.8 V / 0.3 V
Is less than the maximum value), and the output voltage WC is 0.768.
V.

Thereafter (at times T1 to T2, T2 to T3, T3
-T4), the analog voltages VA, VB, and VC fluctuate, but the ratio (5: 4: 3) of the respective values is always stored, so the following equations (2), (3), and (4) are used. Holds, and the output voltages WA, WB, and WC become almost equal, and the graph g
7, g8 and g9 almost overlap. WA = VA × GA = VA × 0.8 / 0.5 (2) WB = VB × GB = VB × 0.8 / 0.4 = VA × 0.8 / 0.5 (3) WC = VC × GC = VC × 0.8 / 0.3 = VA × 0.8 / 0.5 (4)

Therefore, in FIG.
B, 2C, output voltages WA, WB, W corresponding to certain positions
If C is around 0.8V, it can be determined as "white", and if it is near 0V, it can be determined as "black". That is,
Regardless of the light emission amount of the light source 4 depending on the image reading device or the sensor sensitivity, the "white" and "black" on the image can be easily and accurately determined by the same determination criterion. It becomes possible.

[0035]

As described above, according to the present invention, the logic
While the pulse is being output from the circuit,
The conversion means appropriately turns off a plurality of switches to amplify the gain of the amplification means.
To a smaller value to lower the output signal value,
When the force signal falls below the specified voltage,
When the switching signal to turn on is no longer output, or when the switch
After a period set based on the number of switches, a logical
The pulse is no longer output from the circuit and the gain of the amplification means
Determine. Therefore, in the image reading apparatus, since the optical path distance of the light emitted from the light source and the detection ability of each sensor are different, even if there is a variation in the value of each input signal obtained by detecting the same object to be detected, the output is not affected. Can be made uniform, and it can be accurately determined whether the image information of the pixel detected by each sensor is “white” or “black”.

[0036]

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an amplifier circuit embodying the present invention.

FIG. 2 is a graph of input / output voltages and a time chart thereof in an amplifier circuit embodying the present invention.

FIG. 3 is a diagram showing a table of various values related to a counter value in the amplifier circuit embodying the present invention.

FIG. 4 is a schematic diagram of a general image reading apparatus.

FIG. 5 is a diagram showing a graph of input / output voltage of a conventional amplifying unit.

FIG. 6 is a graph showing input / output voltages of an amplifying unit including an amplifying circuit embodying the present invention;

FIG. 7 is a graph of input / output voltages in an amplifier circuit embodying the present invention and a time chart thereof.

FIG. 8 is a graph of input / output voltages and a time chart thereof in the amplifier circuit embodying the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Sensor fixing jig 2 Sensor 3 Sheet 4 Light source 5 Arrow 6 Amplifying part 7 Terminal 8 Terminal 9 Terminal 10 Terminal 11 Terminal 12 Terminal 13 Comparator 14 Operational amplifier 15 AND circuit (A, I, C input terminal) 16 Counter 17 Resistance RS Resistance 18 Resistance R1 Resistance 19 Resistance R2 Resistance 20 Resistance R3 Resistance 21 Resistance R4 Resistance 22 Switch 23 Switch 24 Switch 25 Switch 26 Resistance RM Resistance 27 P0-P4 Line t0-t4 Time g1-g9 Graphs VI, VA, VB, VC input voltage VO, WA, WB, WC output voltage AMP amplifier circuit AMP amplifier circuit AMPB amplifier circuit AMPC amplifier circuit S1 to S4 switching signal S5, S6 signal G gain VMAX constant voltage

Continuation of front page (56) References JP-A-1-252013 (JP, A) JP-A-4-68663 (JP, A) JP-A-4-180340 (JP, A) JP-A-4-290068 (JP) JP-A-4-311171 (JP, A) JP-A-56-107613 (JP, A) JP-A-4-91474 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB Name) H03G 1/00-3/34 H04N 1/40-1/409

Claims (1)

(57) [Claims] 1. An amplification circuit used in an image reading apparatus that reads an image using a plurality of sensors that output a detection signal having an analog value according to a detection amount, wherein the amplification circuit obtains an output signal by amplifying the detection signal. Pulse generating means for generating a pulse during a period when the output signal is larger than a predetermined voltage; and a clock pulse enable signal / count end signal.
A signal generating means for generating the signal, the output signal, the enable signal, and the count end signal.
A logic circuit for obtaining a logical product, and a clock during a period in which a pulse is output from the logic circuit.
Clock pulses and switch signals according to the count value.
Signal means, and a plurality of switches are appropriately turned off in response to the switching signal,
While Ru provided, and gain switching means for switching to a smaller value gain of the amplifying means to each of said sensor, said signal generating means, said from said counting means switches
During the period when the switching signal to turn on the switch is not output.
To generate a count end signal having a voltage value of "0".
And a period set based on the number of switches
Generates an enable signal having a voltage value of “1”.
Amplifier circuit for causing.