JP3192849B2 - Driving method of solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method for intermittently driving a solid-state imaging device.

[0002]

2. Description of the Related Art In an image pickup apparatus such as a television camera using a CCD image sensor, a CCD driver for driving a CCD and a timing circuit thereof are provided.
Is provided with a signal processing circuit for performing various processings on the output of the above to obtain a predetermined video signal. Such a signal processing circuit mainly includes a sample-and-hold circuit for sampling the output of the CCD, an automatic gain control circuit for keeping the average level of the signal constant, and compensating for the non-linearity of the emission luminance with respect to the signal level on the video reproduction side. And a gamma correction circuit.

FIG. 7 is a block diagram showing the configuration of a conventional image pickup apparatus, and FIG. 8 is a timing chart for explaining its operation. The frame transfer type CCD image sensor 1
It comprises an imaging unit 2, a storage unit 3, a horizontal transfer unit 4, and an output unit 5. The imaging unit 2 is composed of a plurality of shift registers that are continuous in the vertical direction and are arranged in parallel with each other, and each bit of these shift registers is potential-divided by the action of an electrode to define a plurality of light receiving pixels. . Storage unit 3
Is composed of a plurality of shift registers continuous with each shift register of the imaging unit 2, and receives and accumulates information charges from the shift registers of the imaging unit 2. The horizontal transfer unit 4 includes a single shift register in which each bit is associated with the output terminal of the shift register of the storage unit 3, and sequentially transfers and outputs information charges received from the storage unit 3. The output unit 5 is provided on the output side of the horizontal transfer unit 4 and converts the information charge output from the horizontal transfer unit 4 into a voltage value and outputs the voltage value. The imaging unit 2, the storage unit 3, and the horizontal transfer unit 4 of the CCD image sensor 1.
Are connected to a V driver 6, an S driver 7, and an H driver 8, respectively. The V driver 6, the S driver 7, and the H driver 8 operate according to a common reference clock, and supply, for example, four-phase transfer clocks φ _V and φ _S to the imaging unit 2 and the storage unit 3, respectively. Transfer part 4
Supplies the two-phase transfer clock φ _H to As a result, the information charges generated in the imaging unit 2 of the CCD image sensor 1 are transferred from the imaging unit 2 to the storage unit 3 for each screen, and then transferred from the storage unit 3 via the horizontal transfer unit 4 in units of one horizontal line. Is transferred to the output unit 5.

The CCD output from the output section 5 of the CCD image sensor 1 is subjected to processing such as sampling, amplification and gamma correction in a signal processing circuit 9 and then output to an external device as a video signal. . On the other hand, the timing control circuit 10 including a counter and a decoder controls the horizontal synchronizing signal H-SYC and the vertical synchronizing signal V-
Upon receiving the SYC, the V driver 6, the S driver 7, and the H driver 8 are activated at a predetermined timing. That is, the timing of one horizontal scanning cycle which is reset by the horizontal synchronizing signal H-SYC, counts a clock of a fixed cycle, and activates the S driver 7 and the H driver 8 based on the output of the H counter which operates in one horizontal scanning cycle. Generate a pulse. Then, it is reset by the vertical synchronizing signal V-SYC, counts the horizontal synchronizing signal H-SYC, and activates the V driver 6 and the S driver 7 based on the output of the V counter operating in one vertical scanning cycle. Is generated. At the same time, the signal processing circuit 9
The sampling pulse, the clamp pulse, and the like required in the above are generated so as to coincide with the operation timing of the CCD image sensor 1, and are supplied to the signal processing circuit 9. Thus, the video signal output from the signal processing circuit 9 can be synchronized with the horizontal synchronization signal H-SYC and the vertical synchronization signal V-SYC.

[0005]

It is well known to use an image scanner that scans and scans a subject document when image data is taken into a device such as a personal computer or a word processor. It has been considered to use an image sensor that can cope with the above. For example, the imaging apparatus as described above is configured to convert an output video signal into digital data, and transfer the digital data to the device side in units of one screen. However, in a monitor screen of a computer device, since the arrangement of display pixels on the screen is predetermined, when an image sensor whose number of pixels in the vertical direction and the horizontal direction does not match the monitor screen is used, horizontal scanning is performed. , The video data obtained from the image sensor cannot be displayed correctly.

In order to cope with this, it has been considered that the number of pixels of video data obtained from the image sensor is converted to match the number of pixels of the monitor screen. As a general method of converting the number of pixels, it is known that video data for one screen is fetched into a field memory and the image data is processed using a digital signal processor (DSP). However, there is a problem that a circuit configuration of a field memory or the like becomes large. As a method not using the field memory, the image sensor is intermittently driven at a predetermined cycle to obtain intermittent video data, and the missing data is interpolated with other data to thereby reduce the number of pixels of the monitor screen. Is generated. However, if the image sensor is driven intermittently at a fixed cycle, noise due to the start and stop of driving of the image sensor becomes pattern noise and is superimposed on the video data, which causes deterioration in the image quality of the reproduction screen. .

Accordingly, it is an object of the present invention to prevent putter noise from being superimposed on video data when an image sensor is driven intermittently.

[0008]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is characterized by the fact that each light-receiving pixel of a solid-state imaging device in which a plurality of light-receiving pixels are arranged in a matrix. In a method of driving a solid-state imaging device for transferring and outputting information charges in units of one horizontal line every horizontal scanning period, the information charges are transferred to n pixels in n clock periods (n is an integer) with a pause period of an appropriate number of clock periods interposed therebetween. The purpose of the present invention is to intermittently transfer and output data in units, and to make the setting timing of the pause period different between successive horizontal scanning periods.

[0009]

According to the present invention, the period in which the driving of the image pickup device is suspended is set at random in each horizontal scanning period.
The periodicity of noise caused by the intermittent operation of the image sensor is eliminated. For this reason, although the noise ratio (S / N ratio) itself does not change, the pattern noise is eliminated, and the deterioration of the image quality of the reproduction screen is prevented.

[0010]

FIG. 1 is a timing chart for explaining a method of driving a solid-state imaging device according to the present invention, and FIG. 2 is a block diagram of an imaging device to which the driving method is applied. In this figure, C
The CD image sensor, the drivers 6, 7, 8 and the timing control circuit 10 are the same as those in FIG. 7, and transfer the information charges generated in the imaging unit 2 to the storage unit 3 in response to an instruction from the timing control circuit 10. Then, the data is transferred from the storage unit 3 to the output unit 5 via the horizontal transfer unit 4 in units of horizontal lines.

A feature of the present invention is that the H driver 8 drives the horizontal transfer unit 4 intermittently at regular intervals, so that the set timing of the idle period is not matched in each horizontal scan period. It is in. That is, the transfer clock φ _{H in} which an idle period of an appropriate number of clocks is set for every n clocks,
By giving the timing to the horizontal transfer unit 4 at a timing shifted by one to an appropriate number of clocks every horizontal scanning period, the period during which the output of the signal of the CCD image sensor 1 is paused varies in each horizontal scanning period. For example, as shown in FIG. 1, with respect to a transfer clock φ _{H in} which an idle period of one clock is set every four clocks, when the transition from the first horizontal scanning period (1H) to the next horizontal scanning period (2H), 1
Try to advance the clock timing. Then, every time the horizontal scanning period advances, the timing of the transfer clock φ _H is set to 1
Early each clock back to the fifth transfer clock phi _H at the same timing as the first horizontal scanning period (1H) when moving from a horizontal scanning period (5H) 6 th horizontal scanning period of the next (6H). Thereafter, similarly, the first horizontal scanning period (1
H) from the transfer clock φ _H for the fifth horizontal scanning period (5
Repeatedly applied to the transfer clock φ _H of H).

The intermittent CCD output from the intermittently driven CCD image sensor 1 is input to an analog signal processing circuit 21 for processing such as sample hold, automatic gain control (AGC), and gamma correction. And output as a video signal. Furthermore, the video signal is analog-
The video data X input to the digital (A / D) conversion circuit 22 and corresponding to each light receiving pixel of the CCD image sensor 1
(n). For this video data X (n),
This corresponds to the CCD output obtained from the CCD image sensor 1. In the case shown in FIG. 1, the data is intermittent data in which four blocks constitute one block. The intermittent video data X (n) in units of four is input to the digital signal processing circuit 23 and converted into five video data Y (n). This 5
The pieces of video data Y (n) are output in a total of five clock periods of four clock periods in which the video data X (n) is input and a pause period for one clock.

In the digital signal processing circuit 23, as shown in FIG.
(n) is output as the first video data Y (1) as it is, and then the first video data X (1) is output.
The composite data of (1) and the second video data X (2) is output as the second video data Y (2). Similarly, composite data of video data X (2) and X (3) and video data X
The combined data of (3) and X (4) are sequentially output as third and fourth video data Y (3) and Y (4), respectively. Further, the fourth video data X (4) is output as the fifth video data Y (5) with a delay of one clock period. As a result, continuous video data Y (n) is obtained without interruption for intermittent video data X (n).

FIG. 3 is a block diagram showing a configuration of the H driver 8 in which the period during which the driving of the horizontal transfer unit 4 is stopped is shifted by one clock every horizontal scanning period. The preset counter 24 counts up by a synchronization signal HD of a horizontal scanning cycle, and supplies the count value to the counter 25 as preset data. Counter 25, after the preset data is set at the beginning of the timing of each horizontal scanning period, that is incremented by the reference clock CLK of the transfer clock phi _H the same period,
The count value is supplied to the decoder 26. Decoder 2
6 decodes the count value of the counter 25, resets the counter 25 based on the decoding result, and stops the output of the pulse generation circuit 27 for one clock period. The pulse generation circuit 27 generates a two-phase transfer clock φ having a predetermined duty ratio based on the reference clock CLK.
_H, and outputs the transfer clock φ _H in accordance with the instruction of the decoder 26.

For example, when the count value of the counter 25 indicates "5", the decoder 26
Is stopped, and the counter 25 is reset. Therefore, the output of the pulse generation circuit 27 is stopped at five clock cycles, and as shown in FIG. 1, a transfer clock φ _H is output in units of four clocks with a pause of one clock. . At this time,
With the preset data incremented for each horizontal scanning period, the pause period is set at a timing shifted by one clock in each horizontal scanning period.

FIG. 5 is a block diagram showing a configuration example of the digital signal processing circuit 23 for converting the number of pixels, and FIG. 6 is a timing chart for explaining the operation. First multiplier 31
Represents 5 of “0” to “4” in the input video data X (n).
Each type of multiplier is multiplied, and the multiplication result is input to the first selector 32. The multiplication process in the first multiplier 31 is easily executed by the following process. When the multiplier is "0", 0 is output regardless of the video data X (n), and when the multiplier is "1", the input video data X (n) is output.
Is output as is. If the multiplier is “2”, the video data X (n) is shifted by one bit to the upper side and output. If the multiplier is “3”, the multiplication result of the multiplier “1” and the multiplier “2” are output.
Is added to the result of the multiplication and output. And the multiplier "4"
In this case, the video data X (n) is shifted by 2 bits to the upper side and output. The first selector 32 controls the control clock C
At a timing according to K, one of the five types of multiplication results of the first multiplier 31 is selected in a predetermined order and sequentially output. Second
Of the video data X (n−1) delayed by one clock period by the delay circuit 33
The multipliers are multiplied by the respective types of multipliers, and the result of the multiplication is input to the second selector 35. The multiplication process of the second multiplier 34 follows the multiplication process of the first multiplier 31. Like the first selector 32, the second selector 35 selects and outputs one of the five types of multiplication results of the second multiplier 34 in a predetermined order at a timing according to the control clock CK. Then, the adder 36 adds the multiplication result k ₁ · X (n) output from the first selector 32 and the multiplication result k ₂ · X (n-1) output from the second selector 35. , And outputs the addition result as video data Y (n).

When video data X (1) is first input,
The data 4.X (1) multiplied by the multiplier "4" is output from the first selector 32, and this data is directly used as the adder 3
6 is output as video data Y (1). At this time,
The video data X (1) is not input to the second multiplier 34, and the second selector 35 selects the multiplier “0” and outputs data 0. Subsequently, when the video data X (2) is input, data 3 · X (2) multiplied by the multiplier “3” is output from the first selector 32, and the second selector 35
Video data X (1) input one clock period after
Is multiplied by a multiplier "1" to output data 1.X (1). Then, these data are added by the adder 36,
It is output as video data Y (2). Thereafter, in the same manner,
When the video data X (3) and X (4) are sequentially input, the data 2 · X (3) and 1 · X (4) are output from the first selector 32 and the second selector 35 outputs the data. Data 2 · X
(2), 3 · X (3) are output, and these are added to each other by the adder 36 and output as video data Y (3), Y (4). Further, after the video data Y (4) is output,
Data 4 · X (4) obtained by multiplying the video data X (4) delayed by one clock period by the multiplier “4” is output from the second selector 35 and output from the adder 36 as video data Y (5). Is done. At this time, no data is input to the first multiplier 31, and the first selector 32 selects the multiplier “0” and outputs data 0. According to the above calculation processing, Y (5n−4) = 4 · X (4n−3) Y (5n−3) = 3 · X (4n−2) + 1 · X for the video data X (n) (4n-3) Y (5n-2) = 2.X (4n-1) + 2.X (4n-2) Y (5n-1) = 1.X (4n) + 3.X (4n-1) Y The arithmetic processing of (5n) = 4.X (4n) is repeated at five clock cycles, and five video data Y (n) are calculated from the four video data X (n) as shown in FIG. You.

In the above embodiment, the case where the idle period of the image sensor is shifted by one clock every horizontal scanning period has been exemplified. However, the idle period is set to be shifted by two clocks or more in one horizontal scanning period, or each horizontal scanning period is set. The pause period may be set at random.

[0019]

According to the present invention, even when the image sensor is driven intermittently, noise is not superimposed at the same timing in each horizontal scanning period, and the occurrence of pattern noise can be suppressed. Therefore, it is possible to prevent deterioration of the image quality of the reproduction screen reproduced by the video data obtained from the image sensor.

[Brief description of the drawings]

FIG. 1 is a timing chart illustrating a method for driving a solid-state imaging device according to the present invention.

FIG. 2 is a block diagram of an imaging apparatus that employs a method for driving a solid-state imaging device according to the present invention.

FIG. 3 is a block diagram of a driver that generates a horizontal transfer clock.

FIG. 4 is a diagram showing the correspondence between input data and output data of a digital signal processing circuit.

FIG. 5 is a block diagram of a digital signal processing circuit.

FIG. 6 is a timing chart showing the operation of the digital signal processing circuit.

FIG. 7 is a block diagram of a conventional imaging device.

FIG. 8 is a timing chart showing an operation of a conventional imaging device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 CCD image sensor (imaging element) 2 imaging unit 3 storage unit 4 horizontal transfer unit 5 output unit 6 V driver 7 S driver 8 H driver 9 signal processing circuit 10 timing control circuit 21 analog signal processing circuit 22 analog / digital conversion circuit 23 Digital signal processing circuit 24 Preset counter 25 Counter 26 Decoder 27 Pulse generation circuit 31 First multiplier 32 First selector 33 Delay circuit 34 Second multiplier 35 Second selector 36 Adder

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/335

Claims (1)

(57) [Claims] 1. A method for driving a solid-state imaging device for transferring and outputting information charges generated in each of the light-receiving pixels of a solid-state imaging device in which a plurality of light-receiving pixels are arranged in a matrix in units of one horizontal line every horizontal scanning period. With a pause between clock periods,
A solid-state imaging device according to claim 1, wherein the information charges are intermittently transferred and output in units of n pixels in n clock periods (n is an integer), and the setting timing of the idle period is made different in successive horizontal scanning periods. Drive method.