JP3196385B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high integration and high speed operation, such as an EPROM,
The present invention relates to a nonvolatile semiconductor memory device such as a flash EEPROM.

[0002]

2. Description of the Related Art Non-volatile semiconductor memory devices are required to operate at a higher speed in addition to higher integration. However, if the current capability of elements can be increased, the speed at the time of reading can be increased. It is also known that the circuit margin is improved. In order to achieve such an object, the gate length L of the storage element may be reduced or the gate width W may be increased. However, in order to reduce the gate length L, it is necessary to improve finer processing technology and to secure element characteristics such as withstand voltage. In addition, if the gate width W is increased without changing the coupling ratio, the cell area is inevitably increased. If the cell area is not changed, the coupling ratio is reduced, and the writing characteristics are degraded. In addition, the current capability is not improved as expected.

[0003]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and is intended to be formed in a semiconductor memory device so as to surround an element region.
Focusing on the fact that the COS oxide film has a role of securing the coupling ratio together with the element isolation function, and that the LOCOS oxide film is formed by a large size,
It is an object of the present invention to provide a non-volatile semiconductor memory device in which the current capacity of the device is improved by using the substrate region under the LOCOS oxide film, and the operation of the device can be speeded up with high integration of the device. .

[0004]

SUMMARY OF THE INVENTION The present invention relates to a semiconductor substrate.
Formed on the surface of the device so as to surround the element region.
A COS oxide film and one surface area of an element region of the semiconductor substrate;
Overlap with the LOCOS oxide film.
And the floating gate
It is formed on the loading gate via an insulating film.
And a control gate. And the LOCO
The one overlapping the floating gate of the S oxide film;
Formed in the region of the semiconductor substrate below the portion;
The region has the same conductivity type as the one surface region of the element region.
Lower concentration and applied to the control gate
A channel is formed in the area by the read voltage,
Low-concentration impurity layers to increase the effective gate width
Provided.

[0005]

In the nonvolatile semiconductor memory device configured as described above, when a read voltage is applied to the control gate at the time of reading, a low-concentration impurity layer formed on the semiconductor substrate causes the low-concentration impurity layer to be applied to the control gate. The channel is formed by inversion by the applied voltage. Therefore, the effective gate width of the device is widened, and the current capability is improved without changing the cell area.

[0006]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a cross-sectional configuration of an EPROM.
A LOCOS oxide film 12 is formed on the surface of a semiconductor substrate 11 made of silicon or the like so as to surround an element region. A floating gate 14 is formed on the semiconductor substrate 11 via a gate oxide film 13.

[0007] In this case, the central portion of the floating gate 14 is intended to face set on the surface of the semiconductor substrate 11 via a gate oxide film 13, and this floating gate
The outer edge of the 14 is LOCOS
It is formed so as to overlap with oxide film 12. And
A control gate 16 is formed over the floating gate 14 with an insulating film 15 interposed therebetween.

Here, reference numeral 17 denotes a channel stop region of the P region, and a floating region under the LOCOS oxide film 12.
At a portion corresponding to the region under the gate 14, a low-concentration region 18 of P ^{− −} lower than immediately below the gate oxide film 13 is formed. Then, a gate region G is formed corresponding to the gate oxide film 13, and a LOCOS region L is set so as to surround the gate region.

FIG. 2 shows a plan layout of an EPROM constructed as described above. For example, a control gate 16 made of polysilicon in which phosphorus is diffused at a high concentration is used.
Is formed, and the floating gate 14 is formed so as to be electrically insulated from the control gate 16 and the substrate 11 forming the word line. The isolation area is constituted by the LOCOS oxide film 12, for example, the source line 21 is formed by a high concentration diffusion of arsenic, also is to drain 22 is formed in the same manner, the bit line and the drain 22 (not shown), the contact 23, a portion indicated by 24 surrounded by this figure corresponds to a unit cell, and one EP
This constitutes a ROM element.

FIGS. 3 and 4 sequentially show the steps of manufacturing the EPROM thus constructed. FIG. 3 shows a cross-sectional structure of a portion corresponding to line 3-3 in FIG.
FIG. 4 shows a cross-sectional configuration taken along line 4-4 in FIG.

First, as shown in FIG. 1A, a layer of a gate oxide film 13 of a semiconductor substrate 11 is formed, and a nitride film 31 is formed on the oxide film 13 corresponding to an element region. And this nitride film
LOCOS oxidation is performed using 31 to form a LOCOS oxide film 12
To form At this time, although P-type boron is diffused into the semiconductor substrate 11 made of silicon, the surface concentration thereof is set to be low enough to form a channel even under the LOCOS oxide film 12. When the LOCOS oxide film 12 is formed, the concentration under the LOCOS oxide film 12 is automatically reduced below that of the gate by taking in the SiO ₂ constituting the LOCOS oxide film 12 by oxidation.

When the LOCOS oxide film 12 is thus formed, the nitride film 31 is removed to expose the gate oxide film 13 as shown in FIG. In order to set the threshold voltage in the region to a desired value, N-type ions 32 are implanted with the LOCOS oxide film 12 being self-aligned. At the time of this ion implantation, by selecting the ion implantation amount and implantation energy,
S under the bird's beak 121 of the LOCOS oxide film 12
The ion implantation amount into the semiconductor substrate 11 can be reduced as the distance from the gate region increases due to the difference in thickness of iO ₂ . Therefore, the threshold voltage of the bird's beak 121 can be controlled.

Next, as shown in FIG. 2C, a polysilicon is formed on the surface and is etched using a mask made of a predetermined resist 33 to form a floating gate.
Form a sheet 14. Thereafter, the channel 33 is formed in the semiconductor substrate 11 by ion implantation using the resist 33 as a mask.

After the channel stop region 17 is thus formed, the resist 33 is removed as shown in FIG. 3D, and then the insulating film 15 is formed on the floating gate 14.
Further, a layer of the control gate 16 is formed by polysilicon, and a gate structure of the EPROM is formed by photo-etching. Then, as shown in FIG. ^7E, a source 21 and a drain 22 are respectively formed of N ⁺ , an interlayer insulating film 34, an electrode 35, and a passivation film 36 are sequentially formed, thereby completing the EPROM.

In the EPROM manufactured as shown in FIG. 1 manufactured as described above, the impurity concentration on the surface of the semiconductor substrate 11 under the bird's beak 121 of the LOCOS oxide film 12 or under the LOCOS oxide film 12 is determined. The thickness of the oxide film 12 is thicker than the gate oxide film 13 in the gate region, but is set to be smaller with respect to the substrate concentration immediately below the gate, so that a portion of the bird's beak 121 can be formed. Alternatively, the threshold voltage Vt (LO
COS) can be set to “0 <Vt (LOCOS) <Vg”.
Here, Vg is a voltage applied to the gate when reading the EPROM.

With such a configuration, as shown in FIG.
A current path 37 parallel to the gate channel 40 having the highest resistance is formed as shown in FIG.
The current capability can be improved.

Although the above embodiment has been described as an EPROM, a flash EEPROM having a similar configuration can also have a similarly effective configuration. Also, in order to reduce the substrate concentration below the bird's beak 121 of some LOCOS oxide films 12 or below some LOCOS oxide films 12, it is necessary to implant ions for channel stoppers away from the gate region. Instead of being implanted into the floating gate and the self-alignment as shown in the embodiment, the implantation may be performed before or after the formation of the LOCOS oxide film using a resist.

FIG. 6 shows another embodiment, in which a region sandwiched between channel stop regions 17 of a P-type semiconductor substrate 11 is defined as a P ⁻ region 41 and a gate insulating film 13 in this region.
The portion in contact with is defined as a P ⁻ region 42. That is, the substrate
Since the surface concentration of 11 is a problem, a structure in which the substrate concentration at a deep position is changed by epitaxial growth or ion implantation may be used.

[0019]

As described above, according to the nonvolatile semiconductor memory device of the present invention, the gate channel is formed by using the substrate region below the LOCOS oxide film formed so as to surround the element region. Since parallel current paths are formed, current capability is effectively improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional configuration diagram illustrating a nonvolatile semiconductor memory device according to one embodiment of the present invention.

FIG. 2 is a diagram showing a planar layout of the semiconductor memory device.

FIGS. 3A to 3E sequentially illustrate a manufacturing process of the storage device, and correspond to a section taken along line 3-3 in FIG. 2;

FIGS. 4A to 4E sequentially illustrate a manufacturing process of the storage device, and correspond to a section taken along line 4-4 in FIG. 2;

FIGS. 5A and 5B are plane layouts for explaining a current path of a conventional example and an example of the present invention in comparison.

FIG. 6 is a sectional view illustrating another embodiment of the present invention.

[Explanation of symbols]

11 semiconductor substrate, 12 LOCOS oxide film, 13 gate oxide film, 14 floating gate , 15 insulating film, 16 control gate, 17 channel stop region, 18 low concentration region.

──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Shigemitsu Fukatsu 1-1-1 Showa-cho, Kariya-shi, Aichi Japan Inside Denso Co., Ltd. (56) References JP-A-63-196078 (JP, A) JP-A-5- 136429 (JP, A) JP-A-59-58868 (JP, A) JP-A-1-225168 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8247 H01L 27 / 115 H01L 29/788 H01L 29/792

Claims (1)

(57) [Claims] A LOCOS oxide film formed on a surface portion of the semiconductor substrate so as to surround an element region; and a LOCOS oxide film overlapping one surface region of the element region of the semiconductor substrate.
To, a floating gate above is formed so as to overlap a portion of the LOCOS oxide film, a control gate are laminated via an insulating film on the floating gate, and the floating gate of the pre-Symbol L LOCOS oxide film Weight
Formed in the region of the semiconductor substrate below the portion
And the region is defined as the one surface region of the element region.
Lower concentration with the same conductivity type as that of the control gate
Reading and channel in the area by the voltage applied to the
Low concentration to form and widen the effective gate width
A nonvolatile semiconductor memory device comprising: an impurity layer .