JP3197410B2 - DMA bus master module device and control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA bus master module device and a control method suitable for a bus master busy control for adjusting use of an internal bus of a bus master module which occupies a system bus and executes burst transfer.

[0002]

2. Description of the Related Art Direct memory access control is widely used in information processing apparatuses for automating data transfer between memories and input / output devices. In FIG.
A block diagram of a main part of such a general information processing apparatus is shown. This device comprises a main memory 2 for a system bus 1.
And a configuration in which a main processor 3 and a DMA bus master module 4 are connected. The DMA bus master module 4 incorporates a DMA controller. In addition, an input / output device 5 is connected to the system bus 1.

In such an apparatus, the main processor 3
Is received by the DMA bus master module 4, and processes data transfer between the input / output device 5 and the main memory 2. In order to perform such data transfer collectively by a predetermined amount, a means called burst transfer is employed. In performing such a burst transfer, when the DMA bus master module 4 acquires the bus right of the system bus 1, a considerable amount of data transfer processing is continuously performed at once.

However, when such a burst transfer is executed unconditionally, the system bus 1 is kept for a long time during that time.
Occupied by DMA bus master module 4. In this case, other modules connected to the system bus 1, for example, the main processor 3, cannot acquire the bus right of the system bus 1 during that time. For example, system bus 1
If the RS232C port is connected, an overrun error or the like of the port may occur. As a method to prevent such a problem from occurring,
In addition to the method of restricting the line speed and the number of lines of the RS232C port, there is a method of not continuously giving the bus right to the DMA bus master module 4.

FIG. 3 is an explanatory diagram showing the relationship between the burst transfer in which the bus right is restricted and the system bus right.
As shown in FIG. 3A, for example, the DMA bus master module 4 shown in FIG. 2 performs a burst transfer from time T1 to time T4.

However, the DMA bus master module 4
During this time, as shown in FIG. 3B, the bus right is abandoned and the system bus 1 is released each time data is transferred. When such a method is adopted, the DMA bus master module 4 can be used between the time T2 and the time T3 shown in FIG.
Relinquishes the bus right, so that another module can acquire the bus right of the system bus 1.

[0007]

Since the DMA bus master module 4 periodically relinquishes the bus right of the system bus before the completion of the burst transfer during the burst transfer as described above, the burst transfer execution is performed. During this time, there is a possibility that another I / O instruction is issued to the DMA bus master module 4 from another module. Even in such a case, the DMA bus master module 4 has a function of interrupting the burst transfer currently being executed, accepting a new input / output instruction, and restarting the interrupted burst transfer after executing the input / output instruction. There is. In such a DMA bus master module, forced interruption can be performed by masking a HOLD ACK signal generated when the DMA controller occupies the internal bus of the module.

However, there is also a DMA bus master module having a configuration in which burst transfer cannot be forcibly interrupted. With such a module, the above-described bus master busy control becomes impossible. The present invention has been made by paying attention to the above points. In a system employing a DMA bus master module in which a burst transfer once started cannot be forcibly externally interrupted by masking a HOLD ACK signal, another module is used. , DMA
It is an object of the present invention to provide a DMA bus master module device and a control method capable of preferentially acquiring a bus right of a system bus at a timing when an internal bus of a bus master module is released.

[0009]

According to a first aspect of the present invention, a bus right is released at a predetermined timing while a burst transfer is being performed by occupying a system bus, thereby enabling another module to occupy the system bus. A direct memory access controller, and detecting the release of the internal bus by the direct memory access controller, and before the direct memory access controller regains the bus right of the internal bus, the A mask circuit for performing a mask process so as to cut off a supply path of a bus right permission signal of a bus; and a sense circuit for holding a status signal for notifying the other module of the end of the mask process by the mask circuit. And a DMA bus master module device.

According to a second aspect of the present invention, there is provided a direct memory access method which releases a bus right at a predetermined timing during a burst transfer while occupying a system bus, thereby enabling another module to occupy the system bus. A controller and a bus permission signal for the internal bus before detecting the release of the internal bus by the direct memory access controller and before the direct memory access controller acquires the bus right of the internal bus again A mask circuit for performing a masking process so as to cut off the supply path of the device, and a sense circuit for holding a status signal for notifying the other module of the end of the masking process by the masking circuit. After rejecting another module's interrupt to its own module, Requesting activation of the mask circuit at the released timing, reading the sense circuit, and recognizing the end notification of the mask processing, issues an input / output instruction to the direct memory access controller. DMA bus master module control method.

According to a third aspect of the present invention, in the above method, when another module reads the sense circuit and recognizes the notification that the mask processing has not been completed, the other module transmits another module to its own module. The feature is to cancel the interrupt exclusion measures of the above.

According to a fourth aspect of the present invention, there is provided a direct memory access method for releasing a bus right at a predetermined timing during burst transfer while occupying a system bus, thereby enabling another module to occupy the system bus. When an I / O instruction is issued from another module in the controller and the timing when the bus right of the system bus is released,
During the execution of the burst transfer, the input / output instruction is invalidated,
The present invention relates to a DMA bus master module device comprising a result display circuit for validating the input / output command after the completion of the burst transfer and displaying the result.

A fifth aspect of the present invention is a direct memory access method which releases a bus right at a predetermined timing during execution of a burst transfer by occupying a system bus, thereby enabling another module to occupy the system bus. When an I / O instruction is issued from another module in the controller and the timing when the bus right of the system bus is released,
During the execution of the burst transfer, the input / output instruction is invalidated,
After the end of the burst transfer, a result display circuit for validating the input / output instruction and displaying the result is provided, and the other module performs the read cycle after the input / output instruction is issued to the direct memory access controller. The present invention relates to a DMA bus master module control method characterized by reading a result display circuit.

According to a sixth aspect of the present invention, there is provided a direct memory access method which releases a bus right at a predetermined timing during execution of a burst transfer by occupying a system bus, thereby enabling another module to occupy the system bus. When an I / O instruction is issued from another module in the controller and the timing when the bus right of the system bus is released,
During the execution of the burst transfer, the input / output instruction is invalidated,
After the end of the burst transfer, a result display circuit for validating the input / output instruction and displaying the result is provided, and the other module is provided with the result display circuit for DMA data output from the direct memory access controller. And a method for controlling a DMA bus master module, which reads the data including the output of the DMA bus master module.

[0015]

When the mask activation circuit is turned on to activate the mask circuit, the apparatus of the first invention monitors the invalidation of the HOLD REQ signal and detects the release of the internal bus. The detection result is output to the sense circuit as a state signal. When the burst transfer ends, the mask circuit immediately starts HOLD ACK.
Blocks signals from being provided to the DMA controller.
Thus, other modules, such as the main processor,
After detecting the release of the internal bus through the sense circuit, the I / O instruction can be executed preferentially to the DMA controller.

In the method of the second invention, after the main processor eliminates an interrupt of another module with respect to its own module in advance, it activates the mask circuit and waits for the end of the mask processing. Therefore, after the activation of the mask circuit, another module interrupts the main processor, so that the DMA controller does not have to wait for a long time while being masked.

In the third invention, before the main processor activates the mask circuit, the interrupt of another module is eliminated as described above, and as a result of reading the sense circuit, it is determined that the mask processing has not been completed yet. Immediately release another module's interrupt elimination measures. As a result, it is possible to prevent a situation in which an interrupt to the main processor by another module is not accepted at all before the main processor issues an input / output instruction to the DMA controller.

In the fourth invention, when another module issues an I / O instruction to the DMA controller, the I / O instruction is invalidated during the burst transfer, and the I / O instruction is validated after the end of the burst transfer. The result is read by another module via the result display circuit. Thus, the end of the burst transfer of the DMA controller can be recognized with a small number of dynamic steps.

In the fifth invention, the end of the burst transfer shown in the fourth invention is executed in the read cycle after the issuance of the input / output instruction, and the dynamic step can be minimized. According to the sixth aspect, when DMA data is output from the DMA controller, information indicating the end of the burst transfer is included in the DMA data, so that it is not necessary to perform a special process for reading the result display circuit.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the embodiments shown in the drawings. FIG. 1 is a block diagram showing an embodiment of a DMA bus master module device according to the first invention. In this device, a main memory 2, a main processor 3, and a DMA bus master module 10 are connected to a system bus 1. DMA bus master module 10 has D
An MA controller 11 is provided. The system bus 1 includes a mask activation circuit 12 and a sense circuit 13.
And the bidirectional buffer 14 are connected. The DMA controller 11 is connected to the bidirectional buffer 14 via the internal bus 15 so that the DMA controller 11 can mutually transfer data.

The mask activation circuit 12 is connected to a mask circuit 20. The mask activation circuit 12 includes a register for storing a one-bit signal for activating the mask circuit 20. The mask circuit 20 includes an AND gate 21, a flip-flop 22, and an OR gate 23.
And a flip-flop 24, which are connected in order. The output of the flip-flop 24 is input to one terminal of the AND gate 21, and the AND gate 21 is opened and closed by the output of the mask activation circuit 12.

The output of the flip-flop 22 is connected so as to be input to the sense circuit 13. The output of the flip-flop 22 is used as a state signal,
When 0 is completed, the mask processing is a 1-bit signal of a high level, otherwise, it is a 1-bit signal of a low level. Sense circuit 13
Is composed of registers for storing such signals. The HOLD REQ signal of the DMA controller is input to the OR gate 23 of the mask circuit 20 via the flip-flop 16. The output of the flip-flop 22 is input to the OR gate 23, and the logical sum of both is input to the flip-flop 24 and the HOLD A of the DMA controller 11.
It is configured to be sent to the CK signal input terminal. In this embodiment, the HOLD REQ of the DMA controller 11 is used.
The signal and the HOLD ACK signal are both low active signals that are valid at low level.

When such a circuit occupies the system bus 1, the DMA controller 11 executes a predetermined burst transfer. During the burst transfer, an operation of releasing the bus right of the system bus 1 is performed every data transfer. The circuit for controlling this operation is the same as the conventional one, and is not shown. When the DMA controller 11 starts a burst transfer, the HOLD
Even if the ACK signal is invalidated, its operation cannot be interrupted. The present invention is effectively used for such a DMA controller 11.

The mask circuit 20 includes a mask activation circuit 1
When another module, for example, the main processor 3 shown in FIG. 2 sets a signal for activating the mask circuit 20, a mask process is started. In this case, when the HOLD REQ signal output from the DMA controller 11 is valid, the mask circuit 20 inputs this signal to the HOLD ACK signal input terminal of the DMA controller 11 through the OR gate 23. At this time, a low-level signal is input to the flip-flop 24, and the AND gate 21 does not allow the output of the mask activation circuit 12 to pass therethrough.
2 holds a low-level signal. Therefore, the state signal becomes low level, and the sense circuit 13 holds the low level signal. The output of the OR gate 23 is also held at the low level. As described above, when the HOLD REQ signal is valid, the interruption of the main processor 3 is not recognized.

On the other hand, when the DMA controller 11 terminates the burst transfer and invalidates the HOLD REQ signal, the output of the OR gate 23 of the mask circuit 20 becomes high level, and the high level signal is stored in the flip-flop 24.
Since the HOLD ACK signal is low active, it becomes invalid at this stage. On the other hand, the signal stored in the flip-flop 24 is supplied to the AND gate 21, and the high-level signal stored in the mask activation circuit 12 is supplied to the flip-flop 22. As a result, the output of the flip-flop 22 becomes a high level, which is stored in the sense circuit 13 as a state signal. This state is a state in which the main processor 3 can issue an input / output instruction to the DMA controller 11.

In this state, the flip-flop 22
The high level signal is stored in the OR gate 23.
Is supplied to the flip-flop 24 through
Thereafter, even if the HOLD REQ signal becomes valid and a low-level signal is supplied to the OR gate 23 through the flip-flop 16, the HOLD ACK signal is not low, that is, not valid, by itself. As a result, the next burst transfer operation by the DMA controller 11 is masked by the mask circuit 20. The main processor 3 detects that the storage signal of the sense circuit 13 has become high level and can issue an input / output instruction to the DMA controller 11.

FIG. 4 shows an operation flowchart of the second invention. In the device according to the first aspect of the invention, the mask activation circuit 12 is turned on to enable the operation of the mask circuit 20, and thereafter, the state signal stored in the sense circuit 13 is monitored. An input / output instruction to the DMA controller 11 is executed.

However, when such an operation is performed, the burst transfer is once terminated, and when the mask circuit 20 completes the masking process, the DMA controller 11 thereafter transmits the next D signal.
The MA transfer cannot be executed. For example, if another module interrupts the main processor 3 during this time and the main processor 3 executes the interrupt processing first, the DMA controller 1
No. 1 is waiting for the operation. This hinders DMA transfer or the like by another module using the DMA controller 11, and may cause overrun or underrun.

Therefore, before the main processor 3 turns on the mask activation circuit 12, it is preferable to take measures to eliminate an interrupt by another module. The second invention has been made for such a purpose, and its processing will be sequentially described with reference to the flowchart of FIG. That is, in step S1, the main processor 3 takes an interrupt exclusion measure by another module. This is performed by a well-known interrupt control of the processor itself.

Thereafter, in step S2, the main processor 3 inputs a high-level signal to the mask activation circuit 12 and turns it on. Thereafter, the mask circuit 20 operates as described above, and the main processor 3 reads the state signal of the sense circuit 13 (step S3). Then, in step S4, it is determined whether or not the mask processing has been completed.
Is repeated.

Thereafter, when the masking process is completed, the process proceeds to step S5, where an I / O command is executed for the DMA controller 11. Then, when the processing of the necessary input / output instruction is completed, in step S6, the interrupt exclusion measure executed first is released.

FIG. 5 shows an operation timing chart of the second invention. The second invention described above is specifically executed at such timing. (A) of the figure shows the state of the mask activation circuit, where the low level is off and the high level is on. FIG. 3B shows a state signal of the sense circuit. A low level indicates that the mask processing is being performed, and a high level indicates that the mask processing is completed. (C) is a HOLD REQ signal, (d)
Indicates a HOLD ACK signal, in which the high level is invalid and the low level is valid. (E) shows the operation of the DMA controller, and (f) shows the timing at which the main processor 3 reads the state information.

First, at time T1, when the HOLD REQ signal becomes valid, the HOLD ACK signal becomes valid subsequently. Here, at time T2, the mask activation circuit 12 is turned on by the main processor 3, and thereafter, at times T3, T4,
At the timing of T6, the state information of the sense circuit 13 is read by the main processor 3. FIG. 5 (c)
As shown in (5), at time T5, when the burst transfer of the DMA controller 11 is completed and the HOLD REQ signal is invalidated, the HOLD ACK signal is subsequently invalidated. On the other hand, as a result, the state information of the sense circuit 13 becomes high level, and the end of the mask processing is notified to the main processor. When the main processor 3 reads the state information at time T6 as shown in (f), the end of the mask processing is recognized by the main processor 3, and the main processor 3 thereafter executes the input / output instruction at time T8.

As described above, for example, at time T
7 Even if the HOLD REQ signal becomes valid, the mask circuit 2
0 operates and this signal is masked, so that the HOLD ACK signal is held invalid until time T9. When the mask activation circuit 12 is turned off, the output of the AND gate 21 goes to a low level regardless of whether the output of the flip-flop 24 is at a high level. Therefore, a low-level signal is stored in the flip-flop 22. . Therefore, when the HOLD REQ signal goes low thereafter, the OR gate 2
The output of 3 becomes low level, and the HOLD ACK signal becomes valid. Further, the state signal output from the flip-flop 22 becomes low level, and this is stored in the sense circuit 13.

FIG. 6 shows an operation flowchart of the third invention. In the second invention, when the mask activation circuit 12 is turned on, the main processor 3 monitors the state signal of the sense circuit 13 and executes the input / output instruction after the end of the burst transfer. However, if the time from the turning on of the mask activation circuit 12 to the end of the burst transfer is long, the main processor 3 prohibits the interrupt by another module during that time, and prevents the operation of another module.

According to the third aspect of the invention, in order to improve this point, after reading the state signal of the sense circuit 13, the process for activating the mask is temporarily terminated, and the measure for eliminating the interrupt is released. That is, as shown in steps S1 and S2 in FIG. 6, the main processor 3 first executes the interrupt exclusion measure, and then turns on the mask activation circuit 12. Then, when the state information of the sense circuit 13 is read (step S3), it is determined in step S4 whether or not the mask processing has been completed. If the mask processing has not been completed, the process proceeds to step S5, and the mask activation circuit 1
Turn 2 off. After that, in step S6, the interrupt exclusion measure is released, and a state in which an interrupt by another module can be accepted is set.

On the other hand, after an appropriate time has elapsed, the flow returns to step S1 again, and a series of processes from interrupt exclusion to turning on the mask activation circuit are repeated. When it is detected in step S4 that the mask processing has been completed, an input / output instruction to the DMA controller is executed in step S7, and an operation similar to that of the second invention, such as releasing the interrupt exclusion measure in step S8, is performed. Execute. This eliminates the risk that the main processor 3 will continue the interrupt prohibition measures for a long time.

FIG. 7 shows a timing chart of the third invention. According to the third aspect, the device operates at the timing shown in FIG. The explanation of the signals (a) to (f) in the figure is the same as that shown in FIG. As shown in this figure, at time T1, the HOLD REQ signal becomes valid,
When the ACK signal becomes valid, as shown in FIG.
A burst transfer is performed. Here, when the mask activation circuit is turned on at time T2, the state information is read by the main processor 3 at time T3.

Here, in the third invention, when the end of the mask processing is not detected, the mask activation circuit is turned off at time T4. Thereafter, when the HOLD REQ signal becomes invalid at time T5, the HOLD ACK signal subsequently becomes invalid. Then, at time T6, the mask activation circuit is turned on again, and when the state information is read at time T7, the end of mask processing of the mask circuit is recognized by the main processor 3 here.
Then, as shown in (e), the input / output instruction of the DMA controller is executed at time T8. The operation in which the HOLD ACK signal is held in an invalid state until time T9 is the same as that described with reference to FIG.

FIG. 8 shows a block diagram of the device of the fourth invention. The device of the fourth invention is different from the device of the first invention in that the HOLD
The end of the burst transfer is detected by an input / output command without masking the ACK signal. The device in this figure is
1, a main memory 2, a main processor 3, and a DMA bus master module 30 are connected to a system bus 1 in the same manner as in the apparatus of FIG.

The DMA bus master module 30 has a DM
An A controller 11 is provided. Further, the DMA bus master module 30 is provided with an I / O decoder 31 for receiving the address bus of the system bus 1. The I / O decoder 31 outputs a chip select signal input through an address bus to a result display circuit 32 or a DM
This is a circuit for supplying to the A controller 11.

The result display circuit 32 receives the input / output instruction from the module such as the main processor 3 in the second invention.
A circuit for displaying an invalid state when issued during the burst transfer operation by the MA controller 11, and for indicating a valid state when issued after the end of the burst transfer, for example, a register for storing a 1-bit signal. Consists of In this example, the result display circuit 32
Is high, the input / output instruction is valid, and if the signal is low, the input / output instruction is invalid. Also, the HOLD REQ signal and the HOLD ACK of the DMA controller 11
In this example, the signal is valid when it is at a high level.

The OR gate 41 and AND gates 42 and 43
The flip-flops 52, 53, 54 and AND gate 45 constitute a control circuit for supplying a chip select signal from the I / O decoder 31 to the DMA controller 11. AND gate 45 is a flip-flop 54
Is high, the chip select signal input from the I / O decoder 31 is transmitted to the DMA controller 11.
To start the operation. The flip-flop 55, the AND gate 44, and the flip-flops 56 and 57 constitute a circuit for holding the HOLD REQ signal output from the DMA controller 11, generating a HOLD ACK signal, and supplying the HOLD ACK signal to the DMA controller. I have.

The OR gate 41 is connected to the I / O decoder 3
1 is provided to guide the chip select signal of the result display circuit 32 output from the result display circuit 32 to the result display circuit 32. Furthermore,
The flip-flop 51 is provided to hold a reset signal of the result display circuit 32. Also, the control signal of the system bus 1 is input to the AND gate 42, and the chip select signal output from the I / O decoder 31 is input to the result display circuit 32 depending on whether the system bus 1 is a read cycle or a write cycle. I try to control. That is, in this example, in the case of a read cycle, a high-level signal is input from the system bus 1 to the AND gate 42, and the chip select signal of the I / O decoder 31 is supplied to the result display circuit 32 through the OR gate 41. Configuration.

Also, the AND gate 43 provided on the output side of the flip-flop 52 and the AND gate 44 provided on the output side of the flip-flop 55 are connected to each other when one of the output signals is at a high level. The chip select signal is not supplied from the flip-flop 52 to the flip-flop 53 when the HOLD REQ signal is valid at a high level. Is valid, the HOLD REQ signal is blocked by the AND gate 44 and the flip-flop 55 is controlled so as not to be supplied to the flip-flop 56. Thereby, the control of the DMA controller 11 by the main processor 3 is suppressed during the burst transfer in which the HOLD REQ signal is enabled, and once the control of the DMA controller 11 is started by the main processor 3, the HOLD REQ signal is masked.

Between the DMA controller 11 and the system bus 1, bidirectional buffers 33, 34 and 35 are inserted. The bidirectional buffer 35 connects the internal bus of the DMA bus master module 30 and the data bus of the system bus 1. In this example, the data bus has a 16-bit configuration. In this example, D
The internal bus of the MA bus master module 30 has 8 bits.

The bidirectional buffer 33 is a buffer for holding input / output instructions transferred on the internal bus, and the bidirectional buffer 34 is a buffer for holding DMA data transferred on the internal bus. Bidirectional buffer 33
Are connected so as to hold the input / output command when the signal output from the flip-flop 54 is at a high level. Further, the bidirectional buffer 35 is configured to receive a 1-bit output signal from the result display circuit 32 in order to include the output of the result display circuit 32 in the DMA data as described later.

The apparatus according to the fourth aspect of the present invention operates as follows. FIG. 9 shows an operation timing chart of the device of the fourth invention. 3A shows the operation timing of the main processor, FIG. 3B shows the DMA access operation timing of the main memory, and FIG. 3C shows the HOLD REQ signal of the DMA controller. As described above, this signal is a signal whose low level is invalid and whose high level is valid. Also,
(D) shows a HOLD ACK signal of the DMA controller, and similarly, the low level is invalid and the high level is valid. (E) shows the chip select output of the I / O decoder, which is valid when it is at a high level and invalid when it is at a low level. (F) indicates the input of the chip select signal of the result display circuit. Similarly, the signal is valid when the signal is at the high level and invalid when the signal is at the low level. (G) indicates a chip select input signal of the DMA controller, which also has a low level invalid and a high level valid. (H) indicates an output signal of the result display circuit 32. When the signal is low, it indicates that the input / output command is invalid, and when the signal is high, it indicates that the input / output command is valid.

As shown in this figure, first, at time T1, when the HOLD REQ signal of the DMA controller becomes valid, the HOLD ACK signal of the DMA controller becomes valid, and burst transfer starts ((c), (c) d),
(B)). Here, at time T2, the main processor executes an I / O read for the DMA controller. At this time, a chip select signal is output from the I / O decoder 31 and supplied to the AND gate 42 and the AND gate 45.

During this time, the main processor 3 accesses the DMA controller 11. Then, an I / O read is executed at time T2. In this I / O read cycle, it is confirmed whether the I / O instruction executed immediately before is valid or invalid. In this read cycle, the timing signal input from the system bus 1 to the AND gate 42 shown in FIG. 8 becomes valid, the chip select signal output from the I / O decoder 31 is input to the result display circuit 32, and Processing result of I / O instruction is bidirectional buffer 3
5 is output. The result display circuit 32 is periodically cleared by the flip-flop 51 and the I / O
If the instruction is not processed effectively, the flip-flop 53
Is also low level, the output of the result display circuit 32 is low level. This is input to the bidirectional buffer 35,
The data is read by the main processor 3 via the system bus 1.

As a result, the main processor 3 sets the I
It recognizes that the / O instruction was invalid. In this case, the chip select signal output from the I / O decoder 31 goes high and is input to the AND gate 45.
The output signal of the flip-flop 54 is at a low level due to the mask effect of the AND gate 43,
No chip select signal is input to the A controller 11 (FIG. 9 (g)).

Note that the output of the result display circuit 32 input to the bidirectional buffer 35 is
In the bit data bus, it is fixed which position to set. Therefore, the main processor 3 selects and reads the contents, and determines whether the input / output command is valid or invalid.

Thereafter, the same processing is repeated at times T3 and T4. During this time, the DMA controller 11 executes burst transfer to the main memory 2. At the time T4, when the burst transfer ends, if an I / O instruction is executed in the next write cycle, the I / O instruction immediately after the time T5
In the / O read cycle, the flip-flop 54 shown in FIG.
Becomes high level, and a chip select signal is input to the DMA controller 11 through the AND gate 45 (FIG. 9 (g)). At the same time, the output signal of the result display circuit 32 also goes high, and the main processor 3 recognizes this. Then, the main processor 3 executes the I / O write instruction at the time T6, and
To process input / output instructions.

Thereafter, at time T7, main processor 3 executes an operation for reading the processing result of the input / output instruction. In this case, a chip select signal is input from the I / O decoder 31 to the result display circuit 32 via the OR gate 41. As a result, a 1-bit signal indicating the result of the input / output command is output from the result display circuit 32 to the bidirectional buffer 35. The reading of the output of the result display circuit 32 at the time T7 is performed by a method different from the processing performed between the times T2 and T5.

FIG. 10 shows a fifth example of the above processing.
4 shows an I / O read operation flowchart of the invention. In the fifth invention, the success or failure of an input / output instruction is recognized with the smallest number of dynamic steps using the device as shown in FIG. That is, as shown in step S1 of FIG. 10, the main processor 3 executes an I / O read for the DMA controller 11. Here, the main processor 3 reads the output of the result display circuit 32 from the bidirectional buffer 35. Then, in step S2, the result display bit in this output is recognized. Thus, the DMA controller 11
It is possible to immediately recognize whether or not the burst transfer is being executed by only the I / O read for the, so that the efficiency and speed of the processing are improved.

FIG. 11 shows a flowchart of an I / O write operation according to the fifth invention. It is most efficient to recognize the result display bit by the processing shown in FIG. However,
The recognition can also be performed by a method as shown in FIG. First, in step S1, measures are taken to prohibit interrupts of the main processor itself.

Next, in step S2, an I / O write to the DMA controller is executed. When the I / O write is executed, a chip select signal is input to the result display circuit 32 from the I / O decoder 31 shown in FIG. The result of the display bit is read by such a method, and step S4
In, it is determined what the display bit is.

If the result display bit indicates that the input / output instruction is unsuccessful, in step S5, the interrupt disabled state is temporarily released, and the flow returns to step S1 again at an appropriate interval. In order to set the interrupt disabled state in this way, immediately after executing the input / output instruction to the DMA controller, another interrupt occurs, and the contents of the result display circuit 32 of the DMA bus master module 30 are rewritten during the processing. This is to prevent the situation. If it is determined in step S4 that the execution result of the input / output command is valid, the process proceeds to step S6, and the process proceeds to another process after canceling the interrupt prohibition measures so far.

FIG. 12 is an explanatory diagram of the DMA data format of the sixth invention. As described above, the main processor 3 can accept the result indicating bit indicating whether the input / output instruction is valid or invalid at the time of the I / O read operation and the I / O write operation. Here, according to the present invention, as shown in FIGS.
In the case of O read, the DMA controller 11
Is stored in the bidirectional buffer 35 in combination with the DMA data and the like output by the main processor 3, and is read by the main processor 3.

That is, when a 16-bit data bus is provided, for example, the DMA read data is set to 8 bits, and one bit of the result display bit is included. At the time of I / O write, since the purpose is only to recognize the result display bit, the other parts are unused indefinite data. This makes it possible for the main processor 3 to recognize that the input / output instruction is valid or invalid without occupying the system bus 1 in the DMA read cycle. Note that the configuration of the result display circuit shown in FIG. 8 and the circuits for storing and outputting the result display bits and the like may be replaced with various circuits having similar functions.

[0061]

According to the DMA bus master module device and control method of the present invention described above, the following effects can be expected. In the first invention, the release of the internal bus by the DMA controller is detected, and before the release of the bus right is acquired again, mask processing is performed so as to cut off the supply path of the bus right permission signal. Since the completion of processing is notified to other modules such as the main processor, it is possible to use the bus immediately after the release of the internal bus with priority, and to overrun or underrun other modules. Can be prevented. This is particularly effective for a DMA controller having a configuration in which the burst transfer is not terminated even when the HOLD ACK signal is forcibly turned off during the execution of the burst transfer.

According to the second aspect of the present invention, the mask circuit of the DMA controller is activated after the interrupt of another module for its own module is once eliminated. It is possible to prevent a failure such as an interrupt from the module causing the DMA controller to wait for a long time. Also,
According to the third invention, after the interrupt is once inhibited by the second invention, if the DMA controller does not release the internal bus yet, the interrupt measure is released, so that an interrupt from another module to another module is made. Can be prevented.

According to the fourth invention, when an input / output instruction is issued, the input / output instruction is invalidated during the burst transfer, and after the burst transfer is completed, the input / output instruction is validated and the result is displayed. Thus, information such as the end of burst transfer can be obtained with a smaller number of dynamic steps than in the case where the activation of the mask circuit is recognized.

According to the fifth aspect, the result display circuit is read in the read cycle after the issue of the input / output instruction to determine whether the input / output instruction is valid or invalid. Therefore, the result can be recognized in a very short dynamic step. . Furthermore, according to the sixth aspect, since the result of the input / output command is output in combination with the DMA read data, information for recognizing the validity / invalidity of the input / output command is obtained without occupying the system bus. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram of a DMA bus master module device of the first invention.

FIG. 2 is a block diagram of a main part of a general information processing apparatus.

FIG. 3 is an explanatory diagram showing a relationship between burst transfer and a system bus right.

FIG. 4 is an operation flowchart of the second invention.

FIG. 5 is a timing chart of the second invention.

FIG. 6 is an operation flowchart of the third invention.

FIG. 7 is a timing chart of the third invention.

FIG. 8 is a block diagram of the device of the fourth invention.

FIG. 9 is an operation timing chart of the device of the fourth invention.

FIG. 10 is a flowchart of an I / O read operation according to the fifth invention.

FIG. 11 is a flowchart of an I / O write operation according to the fifth invention.

FIG. 12 is an explanatory diagram of a data format for DMA according to the sixth invention.

[Explanation of symbols]

 Reference Signs List 1 system bus 2 main memory 3 main processor 10 DMA bus master module 11 DMA controller 15 internal bus 20 mask circuit

Continuation of the front page (56) References JP-A-61-260346 (JP, A) JP-A-60-239855 (JP, A) JP-A-4-276845 (JP, A) JP-A-58-203535 (JP) JP-A-2-280261 (JP, A) JP-A-4-52848 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 13/28 G06F 13/362

Claims (6)

(57) [Claims] 1. A direct memory access controller for releasing a bus right at a predetermined timing during a burst transfer while occupying a system bus, thereby enabling another module to occupy the system bus. Before detecting the release of the internal bus by the direct memory access controller and before the direct memory access controller acquires the bus right of the internal bus again, the supply path of the bus right permission signal of the internal bus A DMA bus master module, comprising: a mask circuit for performing a mask process so as to cut off the data; and a sense circuit for holding a status signal for notifying the other module of the end of the mask process by the mask circuit. apparatus. 2. A direct memory access controller for releasing a bus right at a predetermined timing during execution of a burst transfer while occupying a system bus, thereby enabling another module to occupy the system bus. Before detecting the release of the internal bus by the direct memory access controller and before the direct memory access controller acquires the bus right of the internal bus again, the supply path of the bus right permission signal of the internal bus A mask circuit for performing a mask process so as to cut off, and a sense circuit for holding a status signal for notifying the other module of the end of the mask process by the mask circuit, wherein the other module has its own module in advance. After eliminating another module's interrupt, the system bus is released. And the activation of the mask circuit requires timing, reads the sense circuit recognizes the completion notification of the mask processing, the direct
A method of controlling a DMA bus master module, which issues an input / output instruction to a memory access controller. 3. When another module reads the sense circuit and recognizes that the mask processing has not been completed, the other module cancels another module's interrupt elimination measures for its own module. 3. The method of controlling a DMA bus master module according to claim 2, wherein: 4. A direct memory access controller for releasing a bus right at a predetermined timing during execution of a burst transfer by occupying a system bus, thereby enabling another module to occupy the system bus. At the time when the bus of the system bus is released,
When an I / O instruction is issued from another module, the I / O instruction is invalidated during the execution of the burst transfer,
A DMA bus master module device comprising a result display circuit for validating the input / output instruction after the completion of the burst transfer and displaying the result. 5. A direct memory access controller for releasing a bus right at a predetermined timing during a burst transfer while occupying a system bus, thereby enabling another module to occupy the system bus. At the time when the bus of the system bus is released,
When an I / O instruction is issued from another module, the I / O instruction is invalidated during the execution of the burst transfer,
After the end of the burst transfer, a result display circuit for validating the input / output instruction and displaying the result is provided, and the other module performs the read cycle after the issuance of the input / output instruction to the direct memory access controller. A method for controlling a DMA bus master module, comprising reading a result display circuit. 6. A direct memory access controller for releasing a bus right at a predetermined timing during execution of a burst transfer by occupying a system bus, thereby enabling another module to occupy the system bus. At the time when the bus of the system bus is released,
When an I / O instruction is issued from another module, the I / O instruction is invalidated during the execution of the burst transfer,
After the end of the burst transfer, a result display circuit for validating the input / output instruction and displaying the result is provided, and the other module includes a result display circuit for DMA data output from the direct memory access controller. A DMA bus master module control method for reading the data including the output of the DMA bus master module.