JP3198200B2 - Method of manufacturing vertical MOS transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a vertical MOS transistor, and more particularly to a vertical MOS transistor (MOSFE) disclosed in Japanese Patent Application Laid-Open No. 4-229662.
T) Instability of the drain-source breakdown voltage characteristics (walk o
ut phenomenon).

[0002]

2. Description of the Related Art FIG. 11 is a cross-sectional view schematically showing an example of the structure of a conventional vertical MOS transistor having a two-stage gate structure (Japanese Patent Laid-Open No. 4-229662).

In FIG. 1, reference numeral 1 denotes an N ⁺ type semiconductor substrate, 2 denotes an N ⁻ type impurity diffusion region (hereinafter referred to as an impurity region) serving as a drain region formed on the substrate 1 by epitaxial growth, and 3 denotes a channel portion. P ⁺ -type impurity region serving as a base region including 3a; N ^{+ serving as a} source region;
In the present specification, for the sake of convenience, a stacked structure of the base 1 and the regions 2 to 4 is referred to as a semiconductor substrate.

[0004] A trench 5 is dug from the main surface of the semiconductor substrate, and the side wall of the trench 5 is formed by the exposed source region 4, channel portion 3 a and N ⁻ drain region 2.
The second gate electrode 6 is connected to the external gate terminal G via the metal electrode 6a, and is opposed to the channel portion 3a with a thin second gate insulating film 7 interposed therebetween, and performs a main gate function of the vertical MOSFET. Form the structure. The upper portion of the first gate electrode 9 provided in the trench 5 is capacitively coupled to the second gate electrode 6 via the capacitor insulating film 8, and the lower portion thereof has a larger thickness than the second gate insulating film 7. Opposing the N ⁻ drain region 2 with the first gate insulating film 10 interposed therebetween, and having a relatively small electric field effect.
Form the structure. The source electrode 11 has an N ⁺ source region 4
And P ⁺ base region 3, and are ohmically connected to these regions and connected to external source terminal S. The drain electrode 12 on the back surface of the substrate is ohmic-connected to the N ⁺ drain region 1 and has an external drain terminal D
Connected to. Reference numeral 13 denotes an interlayer insulating film.

FIGS. 12 to 17 show the vertical MOSF.
FIG. 4 is a cross-sectional view showing the formation of a trench / gate and the like of the ET in the order of steps.

In FIG. 12, N ⁺ source region 4, P ⁺
A semiconductor substrate is prepared by laminating a base region 3, an N ⁻ drain region 2 and an N ⁺ drain region 1 by a known method. A trench 5 is dug vertically from the main surface of the substrate (in the thickness direction of the substrate). Next, the first insulating film 10a is thermally oxidized.
To form

[0007] In FIG. 13, an undoped polysilicon film 9 a is deposited on the entire surface of the substrate to fill the trench 5.

In FIG. 14, the deposited undoped polysilicon film 9a is etched back using the first insulating film 10a as a stopper, and the height in the trench is set to the N ⁺ source region 4.
At the same level as the upper surface of Thus, the undoped polysilicon layer left in the trench forms the first gate electrode 9.

In FIG. 15, the first gate insulating film 10 is formed by etching and removing the first insulating film 10a to a depth where the channel portion 3a on the side wall is exposed. At the same time, the N ⁺ source region 4 on the trench side wall and the channel portion 3a
, And a groove 14 is formed between the first gate electrode 9 and the opposing first gate electrode 9.

Referring to FIG. 16, a second insulating film 15 having a thickness smaller than that of the first gate insulating film 10 is formed on the surface of the substrate including the inner surface of the groove 14 by thermal oxidation. In FIG. 17, undoped polysilicon is deposited, impurities (phosphorus) are diffused to form phosphorus-doped polysilicon, and the second gate electrode 6 is formed by patterning. The second insulating film 1 sandwiched between the second gate electrode 6 and the channel portion 3a on the side wall of the trench
5 is the second gate insulating film 7, and the second gate electrode 6 and the first
The second insulating film 15 sandwiched between the gate electrodes 9 is referred to as a capacitor insulating film 8.

FIG. 10 is an equivalent circuit diagram of the vertical MOSFET. 11 denote corresponding parts. Reference numeral 16 denotes a MOS structure with the thin second gate insulating film 7 interposed therebetween, and performs a main gate function of the present MOSFET. Symbol 17
Is a MOS structure sandwiching the thick first gate oxide film 10, and N ⁻
This contributes to a change in conductance of the drain region 2. C ₁
A capacitor to the thin capacitor insulating film 8 of the dielectric, since C ₂ is a capacitor for the thick first gate oxide film 10 as a dielectric, C ₁ is very large compared to the C _2, thus the The potential of the first gate electrode 9 is very close to the potential of the second gate electrode 6.

In general, a vertical MOSFET has a high driving capability, occupies a small area on a substrate, and can easily obtain a high degree of integration. Also, in the above conventional example, the gate electrode has a two-stage structure including the first and second gate electrodes,
The thickness of the gate insulating film on the bottom surface of the trench and a part of the side wall connected to the bottom surface can be easily increased, and the withstand voltage at the corner of the trench is significantly improved. Even if the on-resistance is lowered by increasing the depth of the trench, the problem of electric field concentration can be prevented and a sufficient withstand voltage can be obtained.

However, the above-mentioned MOSFET has a drawback that the drain-source breakdown voltage (V _DSS ) is unstable (called a walk-out phenomenon). As you know, MO
The withstand voltage between the drain and the source of the SFET is such that the gate and the source have the same potential (the channel is in an off state),
By applying a forward voltage V _DS between the source and the drain current (I _D)
There was a breakdown voltage value V _DS of when it reaches the 1 mA, symbol V _DSS
Expressed by

FIG. 18 shows V _DS -I in a state where the source electrode and the gate electrode have the same potential and the channel is turned off.
_It shows a _D characteristic curve. When V _DS is small, I
_D but hardly flows exceeds a critical value which is V _DS when I
_D surges, leading to dielectric breakdown. V _DS -I _D characteristic curve a, b, c, d are, for particular the MOSFET, are those measured by the elapsed time, reproducibility is very poor, unstable drain-source breakdown voltage characteristic Is shown.

Next, the vertical MOSFET shown in FIG. 11 is formed, the depth of the trench 5 is set to 10 μm, and the depth of the second gate insulating film 7 from the upper surface of the N ⁺ source region 4 (substantially the second gate electrode 6 The depth of the drain)
The source breakdown voltage (V _DSS ) was measured. The result is shown in FIG.
Shown in The horizontal axis represents the depth (μm) of the second gate insulating film,
The vertical axis indicates the drain-source breakdown voltage V _DSS (V)
Is shown. ● mark, the initial value of V _DSS, ○ mark indicates the V _DSS when the V _DSS has caused a walk out (walk out) phenomenon to move by the time change.

[0016]

As described above, the above-described conventional vertical MOSFET has a two-stage gate structure in which the gate electrode is composed of the first and second gate electrodes, and is continuous with the bottom surface of the trench. Since the thick first gate oxide film is provided in contact with a part of the side wall, the withstand voltage at the corner of the trench is improved, and even if the on-resistance is reduced by increasing the depth of the trench, the electric field is concentrated. And a sufficient pressure resistance was obtained. However, the reproducibility of the drain-source withstand voltage (V _DSS ) characteristic is poor, the V _DSS is unstable, and a so-called drain-source withstand voltage walk-out phenomenon occurs.

An object of the present invention is to provide a manufacturing method capable of improving the instability (walk out phenomenon) of drain-source breakdown voltage (V _DSS ) characteristics in a conventional vertical MOSFET having a two-stage gate structure. .

[0018]

According to the present invention, there is provided a method of manufacturing a vertical MOS transistor, comprising: (a) a first impurity region of one conductivity type (eg, an N source region) exposed on a main surface of a semiconductor substrate;
A second impurity region of the opposite conductivity type (eg, a P base region including a channel portion) provided below the first impurity region; and a third impurity region of one conductivity type provided below the second impurity region. (E.g., an N drain region); and (b) forming a trench extending from the main surface of the semiconductor substrate to the third impurity region through the first and second impurity regions. (C) a step of forming a first insulating film on the inner surface of the trench by thermal oxidation; and (d) a first insulating film (an unnecessary portion is removed in a later step (f) to form a first gate oxide film). ) Is repeated a plurality of times of depositing undoped polysilicon and then doping impurities on the inner surface of the trench in which the undoped polysilicon is formed, or this deposition is repeated a plurality of times to further deposit undoped polysilicon. Filling the trench with a polysilicon layer; and (e) forming the polysilicon layer so that the height of the top surface of the polysilicon layer in the trench does not exceed the height of the first impurity region on the trench sidewall. Forming a first gate electrode by etching back; and (f) at least a second impurity region (channel portion) on a trench side wall.
Forming a first gate insulating film and a groove reaching the insulating film by etching and removing the first insulating film to a depth at which is exposed; and (g) forming the first gate film between the trench sidewall and the first gate electrode. A second insulating film having a thickness smaller than that of the first gate insulating film is formed by thermal oxidation on the inner surface of the groove and the top surface of the first gate electrode, and then the groove is filled with a conductive material to form a second insulating film. While facing the second impurity region (channel portion) via the insulating film (second gate insulating film),
Forming a second gate electrode facing the first gate electrode with a second insulating film (insulating film for a capacitor) interposed therebetween.

Among the above means, the step described in item (d) is different from that of the prior art (Japanese Patent Laid-Open No. 4-229662), and the other steps are the same as those of the above prior art.

[0020]

[Function] The cause of the instability of the drain-source breakdown voltage is as follows.
It was presumed to be caused by the instability of the depletion layer formed in the third impurity region (eg, N ⁻ drain region) facing the first gate electrode.

In the prior art, the first gate electrode is formed of an undoped polysilicon layer. However, if the conductivity of the first gate electrode is increased by doping an impurity (phosphorus), the above-mentioned drain-source withstand voltage may become unstable. The qualitative (walkout phenomenon) was found to be improved.

In the step (c), since the relatively thick first insulating film is formed on the inner peripheral surface of the trench, the opening surface of the trench is narrower than the depth. If the trench is filled with an undoped polysilicon layer instead of the step (d), and the impurity is doped, the conductivity of the first gate electrode is increased, but the first gate electrode is reduced from the narrow opening surface. It is difficult to dope a sufficient amount of impurities to the bottom of the substrate.

As described in (d), after depositing an appropriate amount of undoped polysilicon (an amount that can easily dope impurities), a film forming operation of doping impurities from the surface is repeated a plurality of times, or By repeating this film forming operation several times, for example, and then depositing undoped polysilicon, it is possible to provide sufficient conductivity to the bottom of the first gate electrode. Thereby, the walk-out phenomenon between the drain and the source could be solved.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a manufacturing method according to the present invention will be described below with reference to FIGS. 11 to 17 indicate the same parts.

In FIG. 1, an N ^-- type epitaxial layer is grown on the surface of an N ⁺ -type single crystal semiconductor substrate (usually called a substrate or wafer) 1 and impurities are diffused from the surface to form a P-type semiconductor including a channel portion. ^A second impurity region 3 serving as a base region and a first impurity region 4 serving as an N ⁺ source region are formed in this order. In this embodiment, the third impurity region is formed by adding N ⁻ to the N ⁺ substrate 1 serving as the N ⁺ drain region.
This is a region where the drain region 2 is stacked. A substrate on which an epitaxial layer is grown on the base 1 is called a semiconductor substrate.
The thickness of the N ⁺ source region 4 is 0.5 μm and the P ⁺ base region 3
Shall have a thickness of 2.5 μm.

In FIG. 2, N ⁺ source region 4 and P ⁺
A trench 5 reaching the N ⁻ drain region 2 through the base region 3 is formed to a width of 1 μm by anisotropic etching such as RIE.
m and a depth of 3 μm.

In FIG. 3, a first insulating film (SiO ₂ film) 1 is formed on the substrate surface including the inner peripheral surface of the trench 5 by thermal oxidation.
0a is formed. The film thickness is desirably 0.2 μm or more, and in this embodiment, it is 0.4 μm.

In FIG. 4, LPCVD (low pressure CVD)
The film forming step of doping impurities (phosphorus) after applying undoped polysilicon by
The doped polysilicon layer 20a is laminated until the thickness becomes 0.4 μm.

Referring to FIG. 5, an undoped polysilicon layer 20b is deposited to a thickness of 0.4 μm by LPCVD to fill the trench.

In FIG. 6, the stacked doped polysilicon layer 20a and undoped polysilicon layer 20b are
CD using the first insulating film (oxide film) 10a as a stopper
Etch back by E method (chemical dry etching method), the top surface of the polysilicon layer left in the trench is N
⁺ Make the same height as the upper surface of the source region 4. The remaining polysilicon layer including the stacked doped polysilicon layer and the undoped polysilicon layer forms the first gate electrode 20.

In FIG. 7, a first insulating film (oxide film) 10 is wet-etched using ammonium fluoride.
By etching a, the first insulating film is removed at least to a depth at which the channel portion 3a in the base region of the trench side wall is exposed, and a groove 14 sandwiched between the trench side wall and the first gate electrode 20 is formed. The first insulating film left in the N ⁻ drain region 2 is a first gate insulating film (0.4 μm thick).
) 10 is formed. Next, a second insulating film 15 having a thickness of 0.05 μm, which is thinner than the first gate insulating film 10, is formed on the inner surface of the groove 14 and the top surface of the first gate electrode 20 by thermal oxidation.

Referring to FIG. 8, undoped polysilicon is deposited on the substrate surface to a thickness of 0.25 μm, impurities (phosphorus) are diffused, and the trench 14 is buried in the doped polysilicon layer 6b. By the method described above, the second gate electrode 6 shown in FIG. 9 is formed by patterning. 8 or 9, the portion of the second insulating film 15 sandwiched between the doped polysilicon layer 6b (or the second gate electrode 6) and the channel portion 3a is the second gate insulating film 7
Is formed, and the portion of the second insulating film 15 sandwiched between the doped polysilicon layer 6b (or the second gate electrode 6) and the first gate electrode 10 forms the capacitor insulating film 8.

Referring to FIG. 9, an interlayer insulating film 13 is deposited on the surface of the substrate by a known method, a contact hole is opened, and a source electrode 11 and an ohmic connection to the N ⁺ source region 4 and the P ⁺ base region 3 are formed. 2 A gate electrode 6a connected to the gate electrode 6 is formed. Next, a metal film is deposited on the back surface of the semiconductor substrate to form a drain electrode 12. Symbols D, G, and S are external connection terminals for the drain, gate, and source, respectively.

The vertical MOSFET manufactured according to the above embodiment.
At T, the drain-source breakdown voltage instability (walk out
Phenomenon) has disappeared. This is the first gate electrode 2
This is because the depletion layer formed in the N ⁻ drain region 2 facing 0 is stabilized. FIG. 20 shows the drain-source breakdown voltage (V) obtained by the vertical MOSFET before dicing formed on the wafer by the manufacturing method of the above embodiment.
₃ shows an example of distribution data in the wafer plane of _DSS ). The horizontal axis indicates the arrangement order of the pellets counted in the orientation flat direction from the center of the wafer, and the vertical axis indicates V _DSS (V). When the depth of the second gate electrode 6 from the substrate surface is 4 μm and the depth of the trench 5 is 10 μm,
Occurrence of instability of the trench-source breakdown voltage V _DSS is nil, the average value of the breakdown voltage V _DSS is made slightly weaker than MOSFET for generating a conventional walk-out at about 60V.

The above description has been directed to preferred embodiments, and the invention is not limited thereto. For example, the first gate electrode and the second gate electrode are capacitively coupled, but both electrodes can be electrically connected after manufacturing. In the embodiment, the bottom surface of the trench 5 is located in the N ⁻ drain region 2, but is further deepened so that the N ⁺ substrate 1 serving as the third impurity region is formed.
May be reached.

In the embodiment, the height of the top surface of the first gate electrode is the same as the height of the top surface of the first impurity region, which is desirable for flattening the substrate surface, but lower than this if desired. No problem.

In the present embodiment, the outer peripheral layer of the first gate electrode is formed of doped polysilicon and undoped polysilicon is embedded therein. However, the first gate electrode may be entirely formed of doped polysilicon.

[0038]

As described above, according to the present invention, in a conventional vertical MOSFET having a two-stage gate structure, the instability (walk out phenomenon) of the drain-source breakdown voltage (V _DSS ) characteristic can be improved. A method could be provided.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing an embodiment of a manufacturing process of a vertical MOS transistor of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing step following FIG. 1;

FIG. 3 is a cross-sectional view showing a manufacturing step following FIG. 2;

FIG. 4 is a cross-sectional view showing a manufacturing step following FIG. 3;

FIG. 5 is a sectional view showing a manufacturing step following FIG. 4;

FIG. 6 is a cross-sectional view showing a manufacturing step following FIG. 5;

FIG. 7 is a cross-sectional view showing a manufacturing step following FIG. 6;

FIG. 8 is a cross-sectional view showing a manufacturing step following FIG. 7;

FIG. 9 is a schematic partial sectional view of a vertical MOS transistor according to a manufacturing method of the present invention.

FIG. 10 is an equivalent circuit diagram of the vertical MOS transistor of the present invention and the conventional vertical MOS transistor.

FIG. 11 is a schematic partial cross-sectional view of a conventional vertical MOS transistor.

FIG. 12 is a cross-sectional view showing a step of manufacturing the conventional vertical MOS transistor shown in FIG.

FIG. 13 is a cross-sectional view showing a manufacturing step following FIG. 12;

FIG. 14 is a cross-sectional view showing a manufacturing step following FIG. 13;

FIG. 15 is a cross-sectional view showing a manufacturing step following FIG. 14;

FIG. 16 is a cross-sectional view showing a manufacturing step following FIG. 15;

FIG. 17 is a cross-sectional view showing a manufacturing step following FIG. 16;

FIG. 18 shows the drain / drain of a conventional vertical MOS transistor.
Is I _D -V _DS characteristic curve for explaining instability phenomena source breakdown voltage.

FIG. 19 shows a drain / drain of a conventional vertical MOS transistor.
FIG. 4 is a characteristic diagram showing a relationship between a width of a source-to-source breakdown voltage (V _DSS ) walkout and a depth of a second gate insulating film.

FIG. 20 is a diagram showing a distribution of a drain-source breakdown voltage (V _DSS ) of a vertical MOS transistor in a wafer surface according to the manufacturing method of the present invention.

[Explanation of symbols]

1 N ⁺ third impurity regions (N ⁺ substrate) 2 N ^- third impurity region (N ^- drain region) 3 P ⁺ second impurity region (P ⁺ base regions) 3a P second impurity region (channel portion) 4 N ⁺ First impurity region (N ⁺ source region) 5 trench 6 second gate electrode 7 second gate insulating film (second insulating film) 8 capacitor insulating film (second insulating film) 10 first gate insulating film 10a first Insulating film 11 Source electrode 14 Groove 15 Second insulating film 20 First gate electrode 20a Stacked doped polysilicon layer 20b Undoped polysilicon layer

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-4-229662 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/78

Claims (1)

(57) [Claims] (A) a first impurity region of one conductivity type exposed on a main surface of a semiconductor substrate; a second impurity region of an opposite conductivity type provided below the first impurity region; Forming a semiconductor substrate having a third impurity region of one conductivity type provided below the region; and (b) a third impurity region extending from the main surface of the semiconductor substrate through the first and second impurity regions. Forming a trench reaching
(C) forming a first insulating film on the inner surface of the trench by thermal oxidation; and (d) depositing undoped polysilicon on the inner surface of the trench where the first insulating film is formed and then doping impurities. Filling the trench with a polysilicon layer by repeating the operation a plurality of times or repeating the film forming operation a plurality of times and depositing undoped polysilicon; and (e) forming a top of the polysilicon layer in the trench. Forming a first gate electrode by etching back the polysilicon layer so that the height of the surface does not exceed the height of the first impurity region on the trench sidewall; (f)
By etching and removing the first insulating film to a depth at which the second impurity region on the trench side wall is exposed,
(G) forming a first gate insulating film and a groove reaching the insulating film; and (g) thermally oxidizing the inner surface of the groove and the top surface of the first gate electrode sandwiched between the trench side wall and the first gate electrode. After forming a second insulating film having a thickness smaller than that of one gate insulating film, the trench is filled with a conductive material,
Forming a second gate electrode facing the second impurity region via the second insulating film and facing the first gate electrode via the second insulating film. Method of manufacturing type MOS transistor.