JP3198766B2 - Conductivity modulation type transistor - Google Patents
Conductivity modulation type transistorInfo
- Publication number
- JP3198766B2 JP3198766B2 JP32939193A JP32939193A JP3198766B2 JP 3198766 B2 JP3198766 B2 JP 3198766B2 JP 32939193 A JP32939193 A JP 32939193A JP 32939193 A JP32939193 A JP 32939193A JP 3198766 B2 JP3198766 B2 JP 3198766B2
- Authority
- JP
- Japan
- Prior art keywords
- type
- region
- type region
- forbidden band
- band width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
- H10D12/411—Insulated-gate bipolar transistors [IGBT]
- H10D12/441—Vertical IGBTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/82—Heterojunctions
- H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
Landscapes
- Junction Field-Effect Transistors (AREA)
- Bipolar Transistors (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、電導度変調型トランジ
スタに関し、立ち上り電圧を下げるようにしたものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electric conductivity modulation type transistor, in which a rising voltage is reduced.
【０００２】[0002]
【従来の技術】従来の電導度変調型トランジスタとして
は、例えば図５に示すようなものがある。高濃度のＰ型
基板１上には実質的にドレインとして機能する低濃度の
Ｎ型ドリフト領域３が形成され、Ｎ型ドリフト領域３の
表面側の所定箇所にＰ型ボディ領域４が形成され、さら
にＰ型ボディ領域４の表面側の所定箇所に高濃度のＮ型
ソース領域５が形成されている。またＮ型ソース領域５
とＮ型ドリフト領域３の間におけるＰ型ボディ領域４上
には、Ｐ型ボディ領域４の表面側にチャネルを誘起させ
るためのゲート電極６がゲート酸化膜を介して形成され
ている。上記の基板及びＰ型、Ｎ型の各領域はＳｉ半導
体材料で形成されている。2. Description of the Related Art As a conventional conductivity modulation type transistor, for example, there is one as shown in FIG. A low-concentration N-type drift region 3 substantially functioning as a drain is formed on the high-concentration P-type substrate 1, and a P-type body region 4 is formed at a predetermined position on the surface side of the N-type drift region 3. Further, a high-concentration N-type source region 5 is formed at a predetermined position on the surface side of P-type body region 4. N-type source region 5
A gate electrode 6 for inducing a channel on the surface side of P-type body region 4 is formed on P-type body region 4 between N-type drift region 3 and a gate oxide film. The substrate and each of the P-type and N-type regions are formed of a Si semiconductor material.
【０００３】そしてドレイン電極Ｄに所要値の正電圧が
加えられ、ゲート電極６に閾値以上のゲート電圧が印加
されると、ゲート電極６直下のＰ型ボディ領域４の表面
層にチャネルが誘起されてＮ型ソース領域５からＮ型ド
リフト領域３へ電子が流れる。それに従って高濃度のＰ
型基板１からＮ型ドリフト領域３へ正孔が注入され、Ｎ
型ドリフト領域３内には高濃度の電子と正孔が存在する
ことになって電導度変調が起きる。その結果、動作時の
オン抵抗が減少し、電力損失が小さくなる。但し従来の
電導度変調型トランジスタでは、Ｐ型基板１とＮ型ドリ
フト領域３の間にできているＰＮ接合はＳｉで形成され
ているため、図６（ｂ）に示すように、このＰＮ接合に
約１ｅＶの障壁が存在している。従ってＰ型基板１から
Ｎ型ドリフト領域３へ正孔が注入されて電流が流れるた
めには、上記のＰＮ接合間に約１Ｖの電圧をかける必要
がある。その結果、図６（ａ）に示されているように、
電流が流れるためには、約１Ｖの立ち上り電圧Ｖf が必
要になる。When a required positive voltage is applied to the drain electrode D and a gate voltage higher than a threshold value is applied to the gate electrode 6, a channel is induced in the surface layer of the P-type body region 4 immediately below the gate electrode 6. As a result, electrons flow from the N-type source region 5 to the N-type drift region 3. Accordingly, a high concentration of P
Holes are injected from the mold substrate 1 into the N-type drift region 3,
The presence of high concentrations of electrons and holes in the drift region 3 causes conductivity modulation. As a result, the on-resistance during operation is reduced, and the power loss is reduced. However, in the conventional conductivity modulation type transistor, since the PN junction formed between the P-type substrate 1 and the N-type drift region 3 is formed of Si, as shown in FIG. Has a barrier of about 1 eV. Therefore, in order for holes to be injected from the P-type substrate 1 to the N-type drift region 3 to cause a current to flow, it is necessary to apply a voltage of about 1 V between the PN junctions. As a result, as shown in FIG.
In order for the current to flow, a rising voltage Vf of about 1 V is required.
【０００４】[0004]
【発明が解決しようとする課題】従来の電導度変調型ト
ランジスタは、電流を流すには約１Ｖの立ち上り電圧が
必要となっていたため電力損失（電流×立ち上り電圧）
を十分小さくすることが難しいという問題があった。The conventional conductivity modulation type transistor requires a rise voltage of about 1 V in order to flow a current, so that power loss (current × rise voltage)
There is a problem that it is difficult to make the size sufficiently small.
【０００５】本発明は、このような従来の問題に着目し
てなされたもので、立ち上り電圧を下げて電力損失を十
分小さくすることができるとともに、立ち上り電圧を下
げるために禁制帯幅の小さい半導体材料を用いても動作
可能最高温度を低下させることのない電導度変調型トラ
ンジスタを提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of such a conventional problem, and it is possible to sufficiently reduce power loss by lowering a rising voltage, and to reduce a forbidden band width to reduce a rising voltage. It is an object of the present invention to provide a conductivity modulation type transistor which does not lower the maximum operable temperature even when a material is used.
【０００６】[0006]
【課題を解決するための手段】上記課題を解決するため
に、本発明は、第１の電位が印加される第１のＰ型領域
と、１のＰ型領域に隣接する第１のＮ型領域と、１のＮ
型領域に隣接する第２のＮ型領域と、第２のＮ型領域に
隣接する第２のＰ型領域と、２のＰ型領域に隣接し前記
第１の電位より低い第２の電位が印加される第３のＮ型
領域とを有する電導度変調型トランジスタであって、第
１及び第２のＮ型領域は、第１のＮ型領域よりも第２の
Ｎ型領域の方を禁制帯幅の大きい半導体材料で形成し、
かつ第１のＰ型領域及び第２のＰ型領域は、第１のＰ型
領域と第１のＮ型領域の接合による第１のＰ型領域から
第１のＮ型領域へ正孔の障壁に対し、第２のＮ型領域と
第２のＰ型領域の接合による第２のＮ型領域から第２の
Ｐ型領域への正孔の障壁の方が高くなるような半導体材
料で形成してなることを要旨とする。According to the present invention, there is provided a first P-type region to which a first potential is applied.
, A first N-type region adjacent to one P-type region, and a first N-type region
A second N-type region adjacent to the type region and a second N-type region
An adjacent second P-type region and an adjacent second P-type region
A third N-type to which a second potential lower than the first potential is applied
A conductivity-modulated transistor having a region,
The first and second N-type regions are more second than the first N-type region.
The N-type region is formed of a semiconductor material having a large forbidden band width,
And the first P-type region and the second P-type region are the first P-type region.
From the first P-type region by joining the region and the first N-type region
The first N-type region has a hole barrier, and the second N-type region
From the second N-type region by joining of the second P-type region to the second
The gist of the present invention is that it is formed of a semiconductor material in which a hole barrier to a P-type region is higher .
【０００７】[0007]
【０００８】[0008]
【作用】上記構成により、電流が流れ出す立ち上がり電
圧が低くなって電力損失を十分に小さくすることが可能
となる。また禁制帯幅の小さい半導体材料を用いた場
合、真性化温度が低くなるが、第２のＮ型領域は第１の
Ｎ型領域の禁制帯幅よりも大きな禁制帯幅の半導体材料
で形成するため、第２のＮ型領域と第２のＰ型領域の接
合による第２のＮ型領域から第２のＰ型領域への正孔の
障壁を第１のＰ型領域の接合による第２のＮ型領域から
第２のＰ型領域への正孔の障壁を第１のＰ型領域と第１
のＮ型領域の接合によるそれより高くすることで、第１
のＮ型領域に禁制帯幅の小さい半導体材料を用いても動
作可能最高温度を低下させることがない。According to the above configuration, the rising voltage at which the current flows is reduced, and the power loss can be sufficiently reduced. When a semiconductor material having a small forbidden band width is used, the intrinsic temperature is low, but the second N-type region is
Semiconductor material with a forbidden bandwidth larger than the forbidden bandwidth of the N-type region
The contact between the second N-type region and the second P-type region.
Of holes from the second N-type region to the second P-type region due to
Barrier from the second N-type region by the junction of the first P-type region
The hole barrier to the second P-type region is
By making it higher than that by the junction of the N-type region,
Even if a semiconductor material having a small forbidden band width is used for the N-type region , the maximum operable temperature does not decrease.
【０００９】[0009]
【００１０】[0010]
【実施例】以下、本発明の実施例を図面に基づいて説明
する。図１は、本発明の第１実施例を示す図である。な
お、図１及び後述の第２実施例を示す図において前記図
５における部材及び部位と同一ないし均等のものは、前
記と同一符号を以って示し、重複した説明を省略する。
図１（ａ）に示すように、本実施例ではＮ型ドリフト領
域におけるＰ型基板１と接する側の大部分の領域２が禁
制帯幅の小さいＳｉＧｅで形成され、それ以外の各領域
はＳｉで形成されている。禁制帯幅の小さい半導体材料
としてはＧｅを用いることもできる。したがってＰ型基
板１とＮ型ドリフト領域との間には、そのＰ型基板１と
禁制帯幅の小さいＮ型ドリフト領域２との間にＰＮ接合
ができている。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a first embodiment of the present invention. In FIG. 1 and the drawings showing a second embodiment to be described later, members that are the same as or equivalent to those in FIG. 5 are denoted by the same reference numerals, and redundant description is omitted.
As shown in FIG. 1A, in this embodiment, most of the region 2 on the side in contact with the P-type substrate 1 in the N-type drift region is formed of SiGe having a small forbidden band width, and other regions are formed of SiGe. It is formed with. Ge can also be used as a semiconductor material having a small forbidden band width. Therefore, a PN junction is formed between the P-type substrate 1 and the N-type drift region 2 between the P-type substrate 1 and the N-type drift region 2 having a small forbidden band width.
【００１１】次に、上述のように構成された電導度変調
型トランジスタの作用を説明する。図１（ｂ）は、同図
（ａ）の構造のエネルギーバンド図を示す。Ｐ型基板１
と接する側の大部分のＮ型ドリフト領域２が禁制帯幅の
小さい半導体材料で形成されているために、そのＰ型基
板１とＮ型ドリフト領域２の間にできるＰＮ接合の、Ｐ
型基板１からの正孔の注入に対する障壁が小さくなる。
禁制帯幅の小さい半導体材料としてＳｉＧｅ（又はＧ
ｅ）が用いられ、それ以外の材料としてＳｉが用いられ
ているので、その障壁は０．５ｅＶ以下にできる。その
結果、電流が流れ出す立ち上り電圧を従来の約１Ｖから
０．５Ｖ以下に減少させることができて電力損失を半分
以下に下げることが可能となる。また、禁制帯幅の小さ
い半導体材料を用いた場合、真性化温度が低くなるが、
図１（ａ）に示す構造の中には、禁制帯幅の大きいＳｉ
半導体材料で形成されたＮ型ドリフト領域３とＰ型ボデ
ィ領域４間及びＰ型ボディ領域４とＮ型ソース領域５間
に障壁の高いＰＮ接合が残るので、ＰＮＰＮ構造におけ
る内側領域の一部に禁制帯幅の小さい半導体材料を用い
ても動作可能最高温度は低下することがない。さらに、
禁制帯幅の小さいＮ型ドリフト領域２の厚さを２０〜３
０μｍ程度にすれば、ソースＳ、ドレインＤ間の耐圧は
６００Ｖ程度になるので、耐圧の点でも装置動作上支障
はない。Next, the operation of the conductivity modulation type transistor configured as described above will be described. FIG. 1B shows an energy band diagram of the structure shown in FIG. P-type substrate 1
Since most of the N-type drift region 2 on the side in contact with is formed of a semiconductor material having a small forbidden band width, the P-type junction formed between the P-type substrate 1 and the N-type drift region 2 has
The barrier against hole injection from the mold substrate 1 is reduced.
As a semiconductor material having a small forbidden band width, SiGe (or G
Since e) is used and Si is used as the other material, the barrier can be set to 0.5 eV or less. As a result, the rising voltage at which a current flows can be reduced from about 1 V in the related art to 0.5 V or less, and the power loss can be reduced to half or less. In addition, when a semiconductor material having a small forbidden band width is used, the intrinsic temperature is lowered,
In the structure shown in FIG. 1A, Si having a large forbidden band width is included.
Since a PN junction having a high barrier remains between the N-type drift region 3 and the P-type body region 4 and between the P-type body region 4 and the N-type source region 5 formed of a semiconductor material, the PN junction remains at a part of the inner region in the PNPN structure. Even when a semiconductor material having a small forbidden band width is used, the maximum operable temperature does not decrease. further,
The thickness of the N-type drift region 2 having a small forbidden band width is set to 20 to 3
If the thickness is about 0 μm, the withstand voltage between the source S and the drain D is about 600 V, so that there is no problem in the operation of the device in terms of the withstand voltage.
【００１２】図２には、本実施例の電導度変調型トラン
ジスタの製造方法例を示す。まず、高濃度のＰ型Ｓｉ基
板１上にエピタキシャル法により禁制帯幅の小さいＮ型
ドリフト領域２となるＮ型のＳｉＧｅ層を形成し、さら
にＳｉのＮ型ドリフト領域３であるＮ型のＳｉ層を形成
する（図２（ａ））。Ｎ型ドリフト領域３の表面側の所
定箇所にＰ型ボディ領域４を形成し、Ｐ型ボディ領域４
の表面側の所定箇所に高濃度のＮ型ソース領域５を形成
し、さらにゲート酸化膜、ゲート電極を形成する。最後
に所要の金属配線を行う（図２（ｂ））。FIG. 2 shows an example of a method of manufacturing the conductivity modulation type transistor of this embodiment. First, an N-type SiGe layer serving as an N-type drift region 2 having a small bandgap is formed on a high-concentration P-type Si substrate 1 by an epitaxial method. A layer is formed (FIG. 2A). A P-type body region 4 is formed at a predetermined position on the surface side of N-type drift region 3, and P-type body region 4 is formed.
A high-concentration N-type source region 5 is formed at a predetermined position on the surface side of the substrate, and a gate oxide film and a gate electrode are further formed. Finally, necessary metal wiring is performed (FIG. 2B).
【００１３】図３には、本発明の第２実施例を示す。本
実施例では、高濃度のＰ型基板１１も、禁制帯幅の小さ
いＮ型ドリフト領域２と同様に、禁制帯幅の小さいＳｉ
Ｇｅ又はＧｅで形成されている。このような構成によっ
てもＰ型基板１１とＮ型ドリフト領域２の間にできるＰ
Ｎ接合の、Ｐ型基板１１からの正孔の注入に対する障壁
を小さくすることが可能になる。本実施例の製造方法例
としては、Ｐ型基板１１とＮ型ドリフト領域２が形成さ
れているＳｉＧｅ基板と、Ｎ型ドリフト領域３となるＳ
ｉ基板とを直接接合法を用いて接合し、次いでＰ型ボデ
ィ領域４及びＮ型ソース領域５を形成するという方法が
ある。FIG. 3 shows a second embodiment of the present invention. In this embodiment, the high-concentration P-type substrate 11 also has a small forbidden band, like the N-type drift region 2 having a small forbidden band.
It is made of Ge or Ge. With such a configuration, the P formed between the P-type substrate 11 and the N-type drift region 2 can be formed.
It is possible to reduce the barrier to the injection of holes from the P-type substrate 11 at the N junction. As an example of the manufacturing method of the present embodiment, a SiGe substrate on which a P-type substrate 11 and an N-type drift region 2 are formed, and an S-type substrate serving as an N-type drift region 3
There is a method in which the i-type substrate is bonded to the i-type substrate using a direct bonding method, and then the P-type body region 4 and the N-type source region 5 are formed.
【００１４】図４には、本発明の第３実施例を示す。本
実施例は、サイリスタに適用したものである。図４
（ａ）に示すように、サイリスタのＰＮＰＮ構造におけ
るＮ型ドリフト領域１２，１３の一部の領域１２を禁制
帯幅の小さいＳｉＧｅを用いて構成したものである。図
４（ｂ）には、その静特性を示す。この場合もサイリス
タがターンオンしても障壁分だけの電圧Ｖf が残るが、
本実施例では、前述の各実施例と同様に、このＶf の値
を下げることができる。また、このような構造として
も、前記と同様に、動作可能最高温度を低下させること
がない。FIG. 4 shows a third embodiment of the present invention. This embodiment is applied to a thyristor. FIG.
As shown in (a), a part of the N-type drift regions 12, 13 in the thyristor PNPN structure is formed using SiGe having a small forbidden band width. FIG. 4B shows the static characteristics. Even in this case, even when the thyristor is turned on, the voltage Vf corresponding to the barrier remains,
In this embodiment, the value of Vf can be reduced as in each of the above-described embodiments. In addition, even with such a structure, the maximum operable temperature does not decrease as described above.
【００１５】なお、以上述べた電導度変調型トランジス
タの各実施例では、Ｎチャネル型のものについて説明し
たが、Ｐチャネル型のものにも適用できる。この場合ド
リフト領域はＰ型となる。In each of the embodiments of the conductivity modulation type transistor described above, the N-channel type is described. However, the present invention can be applied to a P-channel type. In this case, the drift region becomes P-type.
【００１６】[0016]
【発明の効果】以上説明したように、本発明によれば、
第１及び第２のＮ型領域は、第１のＮ型領域よりも第２
のＮ型領域の方を禁制帯幅の大きい半導体材料で形成
し、かつ第１のＰ型領域及び第２のＰ型領域は、第１の
Ｐ型領域と第１のＮ型領域の接合による第１のＰ型領域
から第１のＮ型領域へ正孔の障壁に対し、第２のＮ型領
域と第２のＰ型領域の接合による第２のＮ型領域から第
２のＰ型領域への正孔の障壁の方が高くなるような半導
体材料で形成したため、電流が流れ出す立ち上がり電圧
が低くなり、電力損失を十分に小さくすることができ
る。また禁制帯幅の小さい半導体材料を用いた場合、真
性化温度が低くなるが、第２のＮ型領域は第１のＮ型領
域の禁制帯幅よりも大きな禁制帯幅の半導体材料で形成
し、第２のＮ型領域と第２のＰ型領域の接合による第２
のＮ型領域から第２のＰ型領域への正孔の障壁を第１の
Ｐ型領域と第１のＮ型領域の接合によるそれより高くす
ることで、第１のＮ型領域に禁制帯幅の小さい半導体材
料を用いても動作可能最高温度を低下させることがな
い。As described above, according to the present invention,
The first and second N-type regions are more second than the first N-type region.
N-type region is made of a semiconductor material with a larger forbidden band width
And the first P-type region and the second P-type region
First P-type region by joining P-type region and first N-type region
To the first N-type region from the hole barrier to the second N-type region.
From the second N-type region due to the junction of the region and the second P-type region.
2 is made of a semiconductor material in which the hole barrier to the P-type region is higher, so that the rising voltage at which a current flows is reduced, and the power loss can be sufficiently reduced. When a semiconductor material having a small forbidden band width is used, the intrinsic temperature is lowered, but the second N-type region is formed in the first N-type region.
Semiconductor material with a larger forbidden bandwidth than the forbidden bandwidth of the region
The second N-type region and the second P-type region
The hole barrier from the N-type region to the second P-type region
Higher than that due to the junction of the P-type region and the first N-type region
Accordingly, even when a semiconductor material having a small forbidden band width is used for the first N-type region, the maximum operable temperature does not decrease.
【００１７】[0017]
【図１】本発明に係る電導度変調型トランジスタの第１
実施例を示す縦断面図及びエネルギーバンド図である。FIG. 1 shows a first example of a conductivity modulation type transistor according to the present invention.
It is a longitudinal section and an energy band diagram showing an example.
【図２】上記第１実施例の製造方法の一例を示す工程図
である。FIG. 2 is a process chart showing an example of the manufacturing method of the first embodiment.
【図３】本発明の第２実施例を示す縦断面図である。FIG. 3 is a longitudinal sectional view showing a second embodiment of the present invention.
【図４】本発明の第３実施例を示す縦断面図及び静特性
を示す図である。FIG. 4 is a longitudinal sectional view showing a third embodiment of the present invention and a diagram showing static characteristics.
【図５】従来の電導度変調型トランジスタの縦断面図で
ある。FIG. 5 is a longitudinal sectional view of a conventional conductivity modulation type transistor.
【図６】上記従来例の静特性及びエネルギーバンド図で
ある。FIG. 6 is a diagram showing a static characteristic and an energy band of the conventional example.
１ Ｐ型基板 ２ 禁制帯幅の小さい半導体材料で形成されたＮ型ドリ
フト領域 ３ 禁制帯幅の大きい半導体材料部分のＮ型ドリフト領
域 ４ Ｐ型ボディ領域 ５ Ｎ型ソース領域 １１ 禁制帯幅の小さい半導体材料で形成されたＰ型基
板REFERENCE SIGNS LIST 1 P-type substrate 2 N-type drift region formed of semiconductor material having small forbidden band width 3 N-type drift region of semiconductor material portion having large forbidden band width 4 P-type body region 5 N-type source region 11 Small forbidden band width P-type substrate made of semiconductor material
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 29/78 H01L 29/74 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 29/78 H01L 29/74
Claims (1)
と、 該第１のＰ型領域に隣接する第１のＮ型領域と、 該第１のＮ型領域に隣接する第２のＮ型領域と、 該第２のＮ型領域に隣接する第２のＰ型領域と、 該第２のＰ型領域に隣接し前記第１の電位より低い第２
の電位が印加される第３のＮ型領域とを有する電導度変
調型トランジスタであって、 前記第２のＮ型領域の禁制帯幅は、前記第１のＮ型領域
の禁制帯幅よりも大きく、かつ前記第１のＰ型領域及び
前記第２のＰ型領域は、前記第１のＰ型領域と前記第１
のＮ型領域の接合による正孔に対する障壁に比し、前記
第２のＮ型領域と前記第２のＰ型領域の接合による前記
正孔に対する障壁の方が高くなるような半導体材料で形
成したことを特徴とする 電導度変調型トランジスタ。 1. A first P-type region to which a first potential is applied
A first N-type region adjacent to the first P-type region, a second N-type region adjacent to the first N-type region, and a second N-type region adjacent to the second N-type region. And a second P-type region adjacent to the second P-type region and lower than the first potential.
And a third N-type region to which a potential is applied.
A tunable transistor, wherein the forbidden band width of the second N-type region is equal to the first N-type region.
Greater than the forbidden band width of the first P-type region and
The second P-type region includes the first P-type region and the first P-type region.
Compared to the barrier to holes due to the junction of
The bonding of the second N-type region and the second P-type region
Semiconductor material with a higher barrier to holes
A conductivity modulation type transistor characterized by being formed .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32939193A JP3198766B2 (en) | 1993-12-27 | 1993-12-27 | Conductivity modulation type transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32939193A JP3198766B2 (en) | 1993-12-27 | 1993-12-27 | Conductivity modulation type transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07193232A JPH07193232A (en) | 1995-07-28 |
| JP3198766B2 true JP3198766B2 (en) | 2001-08-13 |
Family
ID=18220916
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32939193A Expired - Fee Related JP3198766B2 (en) | 1993-12-27 | 1993-12-27 | Conductivity modulation type transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3198766B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10048437A1 (en) | 2000-09-29 | 2002-04-18 | Eupec Gmbh & Co Kg | Method for producing a body from semiconductor material with a reduced mean free path and body produced with the method |
| JP2007005723A (en) * | 2005-06-27 | 2007-01-11 | Toshiba Corp | Semiconductor device |
| CN102760759B (en) * | 2011-04-29 | 2016-02-03 | 比亚迪股份有限公司 | A kind of semiconductor power device |
| CN102810562B (en) * | 2011-05-31 | 2015-07-22 | 比亚迪股份有限公司 | Semiconductor device and manufacturing method thereof |
| JP7059547B2 (en) * | 2017-09-21 | 2022-04-26 | 富士フイルムビジネスイノベーション株式会社 | Laminated structures, light emitting components, printheads and image forming equipment |
| CN108428707B (en) * | 2017-02-13 | 2023-08-11 | 富士胶片商业创新有限公司 | Light emitting member, light emitting device, and image forming apparatus |
-
1993
- 1993-12-27 JP JP32939193A patent/JP3198766B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07193232A (en) | 1995-07-28 |
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