JP3199016B2 - Phase comparison circuit and phase comparator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase comparator comprising a phase comparator and a charge pump circuit, and a phase comparator used for the phase comparator.

[0002]

2. Description of the Related Art FIG. 8 is a circuit diagram showing a conventional phase comparator in which a phase comparator and a charge pump circuit are combined. The phase comparator used in the conventional phase comparator shown in FIG. 8 has input terminals Sig and Ref and an output terminal U.
p and Down, and the circuit is a two-input NAND
Circuits 11, 12, 13, 14, 15, 16 and 3 inputs N
The circuit includes AND circuits 17 and 18 and a delay circuit 20. The delay circuit 20 includes a four-input NAND circuit 1
9 and a combination of inverters Q1 to Qm (m is an even number).

In the conventional example shown in FIG. 8, a charge pump circuit 21 to which an Up terminal and a Down terminal of a phase comparator are connected is a current-type or voltage-type charge pump circuit. Down
The circuit functions as a circuit that converts a phase difference signal input from a terminal into a voltage or a current for controlling the next-stage oscillator.

A current-type charge pump circuit outputs a constant positive current (hereinafter referred to as an Up current) to an output terminal during a period when a Low signal is input from an Up terminal of a phase comparator.
During a period in which the Low signal is input from the Down terminal of the phase comparator, the phase comparator operates so as to output a constant negative current (hereinafter, referred to as a Down current) to the output terminal.
The magnitudes of the current and the Down current are set equal.

When a phase comparator composed of a combination of a phase comparator and a charge pump circuit is used in a PLL frequency synthesizer, the PLL loop is locked and signals having the same phase are input to the Ref terminal and the Sig terminal of the phase comparator. In the state, there is a period in which the Up signal and the Down signal of the phase comparator are simultaneously in the Low state.

At this time, in an ideal charge pump circuit, the ON and OFF operations of the Up current and the Down current of the phase comparator are performed at the same time. The current and the Down current are canceled, and the output current becomes 0. That is, there is no change in the output voltage of the filter circuit connected to the next stage, and the voltage-controlled oscillator of the PLL frequency synthesizer oscillates at a certain frequency.

[0007]

However, in an actual charge pump circuit, the NMO
Due to the difference between the switching characteristics and the frequency characteristics of the S and PMOS transistors, a difference occurs in the switching characteristics between the Up operation and the Down operation. This causes the Ref signal and the Sig signal to the phase comparator to have the same phase. Regardless, a phenomenon occurs in which the output of the charge pump circuit does not become 0.

That is, since there is a difference in switching time and frequency characteristics between the NMOS transistor and the PMOS transistor constituting the actual charge pump circuit, the charge pump circuit is operated at the same timing using the phase comparator according to the conventional example shown in FIG. Even if the Up operation and the Down operation of 21 are performed, there is a difference between the period when the Up current and the Down current in the charge pump circuit 21 are turned on after being turned on.

That is, even when the PLL loop is locked and the Ref signal and the Sig signal of the phase comparator have the same phase, the output of the charge pump circuit does not become 0. This causes fluctuations in the oscillation frequency of the voltage controlled oscillator, causing reference leakage and phase noise.

In order to eliminate the cause of the occurrence of the reference leak and the increase of the phase noise, the phase comparator needs to operate so that the Up signal and the Down signal are simultaneously in the Low state for the same period. The phase comparator shown is
At present, it is not configured to perform such an operation, and it has not yet been possible to eliminate the causes of the above-described occurrence of reference leak and increase in phase noise.

SUMMARY OF THE INVENTION An object of the present invention is to provide a phase comparator which operates so that an Up signal and a Down signal are simultaneously kept in a Low state for the same period in order to eliminate the cause of the occurrence of reference leak and an increase in phase noise, and a phase comparator thereof. Is to provide a phase comparison circuit using the same.

[0012]

In order to achieve the above object, a phase comparator according to the present invention is a phase comparator comprising a phase comparator and a charge pump circuit. The position output from the phase comparator depends on the characteristic difference of the switching time of the Down operation.
The trailing edge timing of the pulse of the phase difference signal is defined as the Up side and Down.
The switching time can be adjusted individually on the
The characteristic difference is corrected.

The phase comparator used in the phase comparison circuit according to the present invention is a phase comparator which constitutes a phase comparison circuit in combination with a charge pump circuit, wherein the charge pump circuit switches between an Up operation and a Down operation. It has an Up-side and Down-side delay circuit that outputs a signal for performing an operation, and the Up-side and Down-side delay circuits are separated into independent individual circuits, and are connected to the Sig terminal and the Ref terminal of the phase comparator. When the in-phase signal is input, the width of the pulse output to the Up terminal and the Down terminal of the phase comparator is
A switch between the Up operation and the Down operation of the charge pump circuit.
Do and Do so as to correct the characteristic difference of the switching time.
This is set individually on the wn side.

Further, as the elements of the Up side and Down side delay circuit, by using an even number of inverters is changed the delay amount continuously a current control from the outside, or
Or use an even number of inverters to reduce the number to 2.
By changing to the unit, or even the number of MOS transistors
Channel length or channel width using transistors
Is changed , the Sig terminal of the phase comparator and Re
When an in-phase signal is input to the f terminal, the phase comparator U
The widths of the pulses output to the p terminal and the Down terminal are individually adjusted on the Up side and the Down side.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 1 is a circuit diagram showing a phase comparison circuit according to Embodiment 1 of the present invention.

In the drawing, the phase comparator according to the present invention has a basic configuration as a phase comparator comprising a phase comparator and a charge pump circuit, and the switching time between the Up operation and the Down operation of the charge pump circuit. Between the Up signal output from the phase comparator and Dow
The correction is performed by individually adjusting the pulse width of the n signal.

The phase comparator used in the phase comparator according to the present invention is a digital type phase comparator.
The p-side and down-side delay circuits have independent circuit configurations, and the delay time of each delay circuit is set to the up-side and the down-side.
The pulse width output to the Up and Down terminals can be set individually when the in-phase signal is input to the Sig terminal and the Ref terminal by adopting a circuit configuration in which adjustment is performed independently on the n side. It is characterized by the following.

Next, a specific example of the present invention will be described as a first embodiment with reference to FIG. The phase comparator used in the phase comparator according to the first embodiment of the present invention shown in FIG. 1 has input terminals Sig and Ref and output terminals Up and Down, and the circuit is a two-input NAND circuit 1, 2, 3, 3. 4,
5 and 6, three-input NAND circuits 7 and 8, and a delay circuit.

The delay circuit according to the first embodiment of the present invention
It is characterized by comprising a four-input NAND circuit 9 and an Up-side delay circuit 10 and a Down-side delay circuit 11 each having an independent circuit configuration.

The number of the upstream delay circuits 10 is m (m is an even number).
, And the Down-side delay circuit is composed of n (n is an even number) serially connected inverters Qd1 to Qdn.

Further, the phase comparator according to the first embodiment of the present invention includes the above-described phase comparator and the Up comparator of the phase comparator.
And a charge pump circuit 12 connected to the Down terminal.

The phase comparator used in the phase comparator according to the first embodiment of the present invention is a current-type or voltage-type charge pump circuit, and the phase difference inputted from the Up terminal or the Down terminal of the phase comparator. The circuit functions as a circuit that converts a signal into a voltage or a current that controls a next-stage oscillator.

Next, the operation of the phase comparator according to the first embodiment of the present invention shown in FIG. 1 will be described.

When the phase of the signal S input to the Sig terminal is ahead of the reference signal R input to the Ref terminal, the phase comparator shown in FIG. Outputs a low-level signal from
When the phase of the signal S input to the Sig terminal is delayed from the reference signal R input to the Ref terminal, a low-level signal is output from the Up terminal during a period proportional to the phase delay.

When the phases of the signals S and R input to the Sig terminal and the Ref terminal respectively match (P
When the LL loop is locked), the Up terminal and D
A low level signal is output from both of the own terminals.
At this time, during the period when the Up terminal outputs a Low-level signal, the inverter Qu1 constituting the Up-side delay circuit 10
Is determined by the delay time Tu of ~ Qum.
The period during which the low-level signal is output is determined by the delay time Td of the inverters Qd1 to Qdn forming the down-side delay circuit 11.

That is, the Up-side delay circuit 10 and Down
Inverters Qu1 to Qu1 constituting each of the side delay circuits 11
Qum, the number n of inverters Qd1 to Qdn and m (n,
m is an even number), and the inverters Qu1 to Qu
When m and the inverters Qd1 to Qdn are composed of MOS transistors, the channel length and the channel width are changed to adjust the extension times of the Up-side and Down-side delay circuits 10 and 11, thereby increasing the Sig. When the in-phase signals S and R are input to the terminal and the Ref terminal, the circuit configuration is such that the pulse width of the Low level signal output to the Up terminal and the Down terminal can be determined.

Next, the operation of the phase comparator shown in FIG.
This will be described with reference to the timing chart shown in FIG. In this case, for the sake of simplicity, it is assumed that the delay time of the logic element is only in the inverters constituting delay circuits 10 and 11.

First, the input terminal R of the phase comparator shown in FIG.
A steady state in which ef and Sig are at the Hig level will be described. 2
Assuming that the outputs of the input NAND circuits 1 and 6 are both at the low level, the output of the four-input NAND circuit 9 is at the high level because two of the four inputs are at the low level, and the output of the inverter Qu1 is Both outputs of Qd1 become High level.

Since the input of the two-input NAND circuits 2 and 5 receives the low level output of the NAND circuits 1 and 6, respectively, the output becomes high level. The NAND circuit 3 receives the High-level output of the NAND circuit 2 and the High-level output of the inverter Qu1, so that the output is at the Low level. NA
The ND circuit 4 receives the High-level output of the NAND circuit 5 and the High-level output of the inverter Qd1, so that the output is at the Low level.

The input of the NAND circuit 7 is NAN.
Low-level output of the D circuit 1 and Hi of the NAND circuit 2
Since the high-level output and the high-level output of the inverter Qu1 are input, the output terminal U of the phase comparator
p becomes High level. The input of the NAND circuit 8 has the output of the low level of the NAND circuit 6 and the NAN.
Since the High-level output of the D circuit 5 and the High-level output of the inverter Qd1 are input, the output terminal Down of the phase comparator becomes High level, and the phase comparator settles in a stable state.

Next, as shown in FIG.
Fall, and the input signal S falls after a delay of T time.

In response to the fall of the input signal R, two inputs N
The output of the AND circuit 1 changes to High level,
Since the output of the NAND circuit 6, which is the input of the input NAND circuit 9, is at the low level, the output of the NAND circuit 9 is at the H level.
There is no change at the high level, and the outputs of the delay circuits 10 and 11 do not change at the high level.

The output of the NAND circuit 2 does not change at the high level because the output of the NAND circuit 1 as one input changes to the high level, but the output of the NAND circuit 3 is at the low level.

Therefore, as for the output of the NAND circuit 7, the Up terminal of the phase comparator changes to the Low level because all three inputs are at the High level, and the Dow of the phase comparator is changed to the Low level.
The n terminal is kept at the high level because the input state of the NAND circuit 8 does not change.

Thereafter, when the input signal S falls with a delay of the time T, the output of the two-input NAND circuit 6 changes to the high level, and all the inputs of the NAND circuit 8 change to the high level. Is once Low
Change to a level. The output of the NAND circuit 6 is Hi.
Since the input has changed to the gh level, the inputs of the four-input NAND 9 all go to the high level, and the outputs thereof change to the low level.

Do receiving output of 4-input NAND circuit 9
The output of the inverter Qd1 on the output side of the wn-side delay circuit 11 becomes low after the delay time of the plurality of inverters Qd1 to Qdn connected in series.

The output of the inverter Qd1 on the output side of the down-side delay circuit 11 becomes low, the output of the NAND circuit 6 is at a high level, and the output of the NAND circuit 5 is at a high level.
Therefore, the Down terminal of the phase comparator, which is the output of the NAND circuit 8, changes to the high level again.

That is, the input signal S of the phase comparator is Low.
The time from when the Down terminal of the phase comparator once becomes Low level to when it returns to High level is equal to the delay time Td of the inverters Qd1 to Qdn, and is the Low level pulse output to the Down terminal of the phase comparator. The width is Td.

The output of the inverter Qu1 on the output side of the Up-side delay circuit 10 receiving the output of the four-input NAND circuit 9 becomes low after the delay time of the plurality of inverters Qu1-Qum connected in series.

The output of the inverter Qu1 becomes Low,
Since the output of the NAND circuit 1 is at the high level and the output of the NAND circuit 2 is at the high level, the Up terminal of the phase comparator, which is the output of the NAND circuit 7, is at the high level.

That is, the time when the Up terminal of the phase comparator is at the Low level is the time T from when the input signal R goes to the Low level until the input signal S goes to the Low level, and the plurality of inverters Qu1 connected in series. The delay time T of ~ Qum
u, and the phase difference between the input signals R and S is reflected.

Thereafter, the phase comparator enters a stable state through the following states. That is, the outputs of the NAND circuits 3 and 4 receiving the low outputs of the inverters Qu1 and Qd1 change to the high level, and the outputs of the NAND circuits 2 and 5 have the two inputs both at the high level.
ow level.

The outputs of the NAND circuits 1 and 6 are Hi.
Since the outputs of the NAND circuits 2 and 5 are at the low level, the output of the four-input NAND circuit is in the high state, and the inverters Qu1 and Q2 receiving the outputs are at the high level.
The output of d1 also becomes High state, and the phase comparator settles in a stable state.

Next, the input terminals Ref and Si of the phase comparator
The case where the input signals R and S are simultaneously at the Low level while both of the g are stable at the High level will be described.

When the input signals R and S go low at the same time, the outputs of the NAND circuits 1 and 6 go from low to high.
Since the input changes to the high level and the inputs of the NAND circuits 7 and 8 are all at the high level, the Up terminal and the Down terminal of the phase comparator temporarily change from the high level to the low level.

However, at this time, the output of the NAND circuit 9 is Low because all four inputs change to High level.
Level, and the input of the NAND circuit 7 is changed from Qu1 to Q
A Low level is input after a delay time Tu of u2,
Thereby, the Up terminal changes to the High level again.

Since the Low level is input to the input of the NAND circuit 8 after the delay time Td of the plurality of inverters Qd1 and Qd2 connected in series, the Down terminal of the phase comparator changes to the High level again. .

That is, when a signal having the same phase as the input signals R and S is input, the Up terminal of the phase comparator has a width equal to the delay time Tu of the inverters Qu1 to Qum constituting the Up-side delay circuit 10. A low-level pulse is output, and a low-level pulse having a width equal to the delay time Td of the inverters Qd1 to Qdn included in the down-side delay circuit 11 is output to the Down terminal of the phase comparator.

Finally, the operation of the phase comparator composed of the phase comparator and the charge pump circuit according to the first embodiment of the present invention shown in FIG. 1 will be briefly described.

When the charge pump circuit 12 shown in FIG. 1 is a current-type charge pump circuit, the charge pump circuit 12 supplies a positive constant current during a period when the Low signal is output from the Up terminal of the phase comparator. Iup (hereinafter referred to as Up current) is output, and a negative constant current (hereinafter referred to as D) is input during a period in which the Low signal is input from the Down terminal of the phase comparator.
(referred to as “own current”). At this time, the magnitudes of the currents Iup and Idown are set equal.

When a Low-level signal having the same width is input to the Up terminal and the Down terminal of the charge pump circuit 12, the time from the start of the flow of the Up current Iup to the end of the flow is Tup, and the flow of the Down current Idown is performed. The time from the start to the end of the flow is defined as Tdown.

If Tup is longer than Tdown, the number n of the inverters Qd1 to Qdn of the down-side delay circuit 11 of the phase comparator is increased, so that Dow is increased.
The delay time Td of the n-side delay circuit 11 is increased, and the time when the Down signal of the phase comparator becomes Low is lengthened.

If Tdown is longer than Tup, increasing the number m of the inverters Qu1 to Qum of the Up-side delay circuit 10 of the phase comparator increases
The delay time Tu of the side delay circuit 10 is increased, and the time when the Up signal of the phase comparator becomes Low is increased.

That is, by performing the above adjustment,
Tup and Tdown can be set equal.

Therefore, if the above adjustment is performed, the period in which Iup and Idown flow in a situation where the in-phase signal is input to the Ref terminal and the Sig terminal of the phase comparator becomes equal, and the magnitude of Iup and Idown is small. Since the directions are equally opposite, the output of the charge pump circuit 12 is Iu
p and Idwon are offset to zero.

FIG. 3 is a circuit diagram showing an example of a configuration when the phase comparison circuit according to the first embodiment of the present invention is used in a PLL frequency synthesizer.

First, the inverter Q forming the Up-side and Down-side delay circuits 10 and 11 of the phase comparator shown in FIG.
A case where the numbers m and n of u1 to Qum and Qd1 to Qdn are equal will be described.

The current type charge pump circuit 1 shown in FIG.
2 is a PMOS transistor under the control of the driver circuit 12a during the period when the Low signal is output from the Up terminal of the phase comparator.
The transistor Qp is turned on to output a positive constant current (hereinafter referred to as “up current”) Iup to an output terminal. During a period in which a Low signal is input from the Down terminal of the phase comparator, the NMOS circuit is controlled by the driver circuit 12a. The transistor Qn is turned on to output a constant negative current (hereinafter referred to as Down current) Idown from the output terminal.

At this time, since the current sources V1 and V2 of the charge pump circuit 12 are set equal, Iup and Id
The magnitude of the own current is also equal.

When the PLL loop is locked and the in-phase signal is input to the Ref terminal and the Sig terminal of the phase comparator, the phase comparator sets the Low state to the signal at the Up terminal and the Down terminal simultaneously for the same period. It works to become. In an ideal charge pump circuit 12,
Up current Iup and Down current Idown of the phase comparator
Perform the ON / OFF operation at the same timing, so that Iup and
n is offset to zero.

That is, since the voltage charged in the capacitor of the filter circuit LPF connected to the next stage does not change, the voltage controlled oscillator VCO oscillates at a constant frequency.

Next, problems occurring in the actual operation will be described. In the actual charge pump circuit 12, based on the phase difference information from the phase comparator, the Up current Iu
Even if the switching operation of p and the Down current Idown is performed at the same timing, there is a difference in the switching time between the PMOS transistor Qp and the NMOS transistor Qp, so that a difference occurs in the period in which Iup and Idown flow,
Input signals S to the Ref terminal and Sig terminal of the phase comparator,
Although R is in phase, the charge pump circuit 12
A situation occurs in which the output current does not become zero.

This causes the oscillation of the oscillation frequency of the voltage controlled oscillator VCO in the locked state of the PLL loop, and causes the reference leak and the phase noise to increase.

Next, in Embodiment 1 of the present invention, in order to eliminate reference leak and phase noise, the phase comparator shown in FIG.
A case where the wn-side delay circuits 10 and 11 are properly adjusted will be described.

If the low-level pulse signal having the same pulse width is input to the Up input terminal and the Down input terminal of the charge pump circuit 12 before the adjustment, the Up current from the phase comparator is turned on. And then OF
It is assumed that the time Tup until F is longer than the time Tdown from when the Down current is turned on to when it is turned off.

In this case, if the number of inverters Qd1 to Qdn forming Down-side delay circuit 11 of the phase comparator is increased, or if inverters Qd1 to Qdn are formed of MOS transistors, the channel length and channel width thereof Is changed, the delay time Td of the Down-side delay circuit 11 is increased, the time during which the Down signal becomes Low is increased, and the Up current of the charge pump circuit 12 and the Do current are increased.
The period Tup is set to be equal to Tdown while the wn current is ON.

By performing such adjustment, the charge pump circuit 1 in the case where the PLL loop is locked and the input signals S and R of the Sig terminal and the Ref terminal of the phase comparator are in phase.
The current on the two output side becomes 0 because the Up current and the Down current are offset. That is, since the voltage charged in the capacitor of the filter circuit LPF connected to the next stage does not change, the voltage-controlled oscillator VCO oscillates at a constant frequency, thereby reducing reference leak and phase noise. .

(Embodiment 2) FIGS. 4 and 5 are views showing Embodiment 2 of the present invention. Embodiment 2 of the present invention is shown in FIG.
As shown in the above, by using an inverter capable of continuously changing the delay amount by external control as an element of the Up-side and Down-side delay circuits 10 and 11 of the phase comparator,
When an in-phase signal is input to the Sig terminal and the Ref terminal of the phase comparator, the widths of the pulses output to the Up terminal and the Down terminal of the phase comparator are individually set on the Up side and the Down side, respectively.
In addition, the adjustment is continuously performed.

More specifically, inverters Qu1 to Qum and Qd1 to Qdn forming delay circuits 10 and 11 of the phase comparator shown in FIG.
1 to Qum and Qd1 to Qdn and current control circuits 13a and 13b.

As shown in FIG. 5, each of the variable delay time inverters Qu1-Qum and Qd1-Qdn has
Transistors Q1, Q2, Q3, Q4, Q5, Q6, Q7;
Each of the delay time variable inverters Qu1 to Qum and Qd1 to Qdn is controlled by the current control circuits 13a and 13b to control the operating current I0 so that the delay time can be varied as shown in FIG. Circuit configuration. In FIG. 5, the current value Ip and the current value In are set equal.

As shown in FIGS. 4 and 5, in the second embodiment of the present invention, variable delay time inverters Qu1 to Quum
And Qd1 to Qdn and the current control circuit 13a,
13b and the phase comparator U
By configuring the p-side and down-side delay circuits 10 and 11, the up-side and down-side delay circuits 1
Since the delay times of 0 and 11 are continuously varied, when the input terminals Ref of the phase comparator and the input signals S and R to the Sig are in phase, the output terminals Up and D of the phase comparator are changed.
The width of the low-level pulse output to each of the own can be set to a desired value by external control. That is, the Up operation of the charge pump circuit 12 and the Do
The characteristic difference of the switching time of the wn operation can be corrected by external control.

FIG. 7 is a diagram showing a simulation result of the phase comparator shown in FIG. The simulation shown in FIG. 7 is based on the Up delay circuit 10 and the Down delay circuit 11.
The number of the delay time variable inverters is 6, and the operating current I0 of the inverter of the Up-side delay circuit 10 is 25 μA, D
The operating current I0 of the inverter of the own side delay circuit 11 is set to 1
00 μA, respectively, and the input terminal Re of the phase comparator
This is a simulation result of pulse waveforms output to the output terminals Up and Down of the phase comparator when signals in phase are input to f and Sig, respectively.

Since the operating current I0 of the inverter of the Up-side delay circuit 10 is set smaller than the operating current I0 of the Down-side delay circuit 11, the delay amount of the Up-side delay circuit 10 becomes D
The delay amount is larger than the delay amount of the own side delay circuit 11, and the pulse width of the Low level of the Down terminal of the phase comparator is larger than that of the Up side.

[0075]

As described above, according to the present invention, the difference between the switching time between the Up operation and the Down operation of the charge pump circuit is determined by the Up signal output from the phase comparator and the D signal.
To individually adjust and correct the pulse width of the own signal,
The difference in the switching characteristics between the Up operation and the Down operation is absorbed by the difference in the switching characteristics and frequency characteristics of the NMOS and PMOS transistors constituting the charge pump circuit, and the phases of the Ref signal and the Sig signal to the phase comparator are in phase. In some cases, the output of the charge pump circuit can be made zero.

In the digital phase comparator used in the phase comparator, the Up-side and Down-side delay circuits are formed as independent circuits, and the delay time of the delay circuit is set to the Up-side and the D-side.
By adopting a circuit configuration that can be adjusted independently on the own side, when an in-phase signal is input to the Sig terminal and the Ref terminal of the phase comparator, the Up terminal of the phase comparator and the Down
The width of the pulse output to the terminal can be set individually.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a phase comparison circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of the phase comparator shown in FIG.

FIG. 3 shows a phase comparison circuit according to a first embodiment of the present invention;
FIG. 9 is a circuit diagram illustrating an example of a configuration when used in an L frequency synthesizer.

FIG. 4 is a circuit diagram illustrating a phase comparison circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a variable delay time inverter shown in FIG. 4;

FIG. 6 is a diagram showing characteristics of the variable delay time inverter shown in FIG. 5;

FIG. 7 is a diagram showing a simulation result of the phase comparison circuit shown in FIG. 4;

FIG. 8 is a circuit diagram showing a phase comparison circuit according to a conventional example.

[Explanation of symbols]

 1, 2, 3, 4, 5, 6 2-input NAND circuit 7, 8 3-input NAND circuit 9 4-input NAND circuit 10 Up-side delay circuit 11 Down-side delay circuit 12 Charge pump circuit Qu1-Qum, Qd1-Qdn Inverter 13a , 13b Current control circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-9-252239 (JP, A) JP-A 7-177027 (JP, A) JP-A 63-269822 (JP, A) JP-A 59-252 221122 (JP, A) JP-A-63-263819 (JP, A) JP-A-11-195982 (JP, A) JP-A-7-86927 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03L 7/089 H03K 5/26

Claims (5)

(57) [Claims] 1. A phase comparison circuit comprising a phase comparator and a charge pump circuit, wherein a difference in switching time characteristic between an Up operation and a Down operation of the charge pump circuit is detected.
The phase difference signal output from the phase comparator
Adjust trailing edge timing separately on the Up and Down sides
A phase comparison circuit for correcting the characteristic difference of the switching time . 2. A phase comparator constituting a phase comparison circuit in combination with a charge pump circuit, wherein an Up side for outputting a signal for performing a switching operation of an Up operation and a Down operation of the charge pump circuit is connected to Down. , And separates the Up-side and Down-side delay circuits into independent separate circuits. When an in-phase signal is input to the Sig terminal and the Ref terminal of the phase comparator, the phase comparator The width of the pulse output to the Up terminal and the Down terminal of the charge pump circuit is determined by the Up operation and the Down operation of the charge pump circuit.
A phase comparator characterized in that it is individually set on the Up side and the Down side so as to correct the characteristic difference of the switching time . As an element wherein the Up side and Down side delay circuit, a phase according to claim 2, characterized by using an even number of inverters is changed the delay amount continuously a current control from the outside Comparator. 4. The elements of the Up-side and Down-side delay circuits.
, Use an even number of inverters,
Set the delay time by changing the unit
The phase comparator according to claim 2, wherein: 5. The elements of the Up-side and Down-side delay circuits.
Using an even number of MOS transistors,
Change the channel length or channel width of the S transistor
Request to set a delay time
Item 3. The phase comparator according to Item 2.